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JPS5847854B2 - semiconductor equipment - Google Patents
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JPS5847854B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5847854B2
JPS5847854B2 JP56024303A JP2430381A JPS5847854B2 JP S5847854 B2 JPS5847854 B2 JP S5847854B2 JP 56024303 A JP56024303 A JP 56024303A JP 2430381 A JP2430381 A JP 2430381A JP S5847854 B2 JPS5847854 B2 JP S5847854B2
Authority
JP
Japan
Prior art keywords
insulating film
layer
film
wiring layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56024303A
Other languages
Japanese (ja)
Other versions
JPS56124246A (en
Inventor
修 笠原
清威 樽岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56024303A priority Critical patent/JPS5847854B2/en
Publication of JPS56124246A publication Critical patent/JPS56124246A/en
Publication of JPS5847854B2 publication Critical patent/JPS5847854B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特にその半導体装置は基板
とアルミニウムとの間に高融点金属膜を介在させた高周
波用トランジスタ(またはIC)を対象とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular, the semiconductor device is directed to a high frequency transistor (or IC) in which a high melting point metal film is interposed between a substrate and aluminum.

一般に高周波用のトランジスタまたはICでは通常、不
純物の拡散層は非常に浅く、0.3μ以下に形成される
In general, in high frequency transistors or ICs, the impurity diffusion layer is usually very shallow, and is formed to have a thickness of 0.3 μm or less.

このような浅い拡散層を用いた場合に、通常のアルミニ
ウムを用いて電極配線を形戒すると、素子の製造工程中
の温度上昇によりアルミニウムとシリコンとが相互に拡
散し、浅いベース・エミツタ接合を短絡する問題かある
If such a shallow diffusion layer is used and the electrode wiring is made of ordinary aluminum, the aluminum and silicon will diffuse into each other due to the temperature rise during the device manufacturing process, resulting in a shallow base-emitter junction. There is a problem with short circuit.

そこで上記のような相互拡散を防止する必要かあり、そ
の手段としてアルミニウム蒸着膜とシリコン基体との間
にモリブデン、チタンあるいはクロム等の高融点金属膜
を介在させることか行われている。
Therefore, it is necessary to prevent the above-mentioned mutual diffusion, and as a means for this purpose, a high melting point metal film such as molybdenum, titanium or chromium is interposed between the aluminum vapor deposited film and the silicon substrate.

上記のチタンおよびクロムはアルミニウムと低温、例え
ば400〜450℃で反応し、金属間化合物を形或する
ので、配線の導体抵抗か増加する。
The above-mentioned titanium and chromium react with aluminum at a low temperature, for example, 400 to 450° C., forming an intermetallic compound, thereby increasing the conductor resistance of the wiring.

このため、この温度でアルミニウムと反応しないモリブ
デンを使用する。
For this reason, molybdenum is used, which does not react with aluminum at this temperature.

しかしながら、上記したアルミニウムとモリブデンとの
重ね膜により配線を形威し、配線の一部をボンデイング
パッド(外部接続部)として、ここに超音波ポンデイン
グによりアルミニウム線ヲ接続しようとすると、基板の
表面絶縁膜とモリブデンとの間でパッド部分か剥雛し、
ボンデイング不良を発生した。
However, if you try to shape the wiring using the above-mentioned layered film of aluminum and molybdenum, use a part of the wiring as a bonding pad (external connection part), and connect the aluminum wire here by ultrasonic bonding, the surface insulation of the board The pad part is peeled off between the membrane and molybdenum,
Bonding failure occurred.

このようなギンデイング不良のあることは、特にペレッ
ト当りのポンデイング数の多いIC,LSI等において
は大きな問題となった。
Such poor binding has become a big problem, especially in ICs, LSIs, etc., where the number of pounds per pellet is large.

かかるパッド部分の剥離の原因について調査した結果、
モリブデンと絶縁膜の主体であるシリコン酸化物との接
着強度が小さいために、超音波ボンデイングの際に作用
する太きなせん断力により一層剥かれやすくなることか
明らかにされた。
As a result of investigating the cause of such peeling of the pad part, we found that
It has been revealed that because the adhesive strength between molybdenum and silicon oxide, which is the main component of the insulating film, is weak, it becomes easier to peel off due to the large shear force that is applied during ultrasonic bonding.

そこで本発明はホンデイングパッドの都分を配線と異な
らせることにより、接着強度を向上させたものである。
Therefore, the present invention improves adhesive strength by making the wiring pad different from the wiring.

したがって本発明の目的は半導体装置において配線材料
を使ったボンデイングパッドの基板への接着強度を向上
させることである。
Therefore, an object of the present invention is to improve the adhesive strength of a bonding pad using a wiring material to a substrate in a semiconductor device.

以下、本発明を実施例にそって具体的に説明する。The present invention will be specifically described below with reference to Examples.

実施例 第1図は本発明をICの一層配線の製造工程に適用した
場合の例である。
Embodiment FIG. 1 shows an example in which the present invention is applied to the manufacturing process of single-layer IC wiring.

(a) 公知の方法によりSi(シリコン)基体1上
にトランジスタのベース領域2、エミツタ領域3を形成
し基体表面の熱酸化またはCVD(気相化学反応)法に
よるSiO2膜4を形成し、エミツタ領域に対し上記S
iO2膜にコンタクト用穴5をあける。
(a) A base region 2 and an emitter region 3 of a transistor are formed on a Si (silicon) substrate 1 by a known method, and an SiO2 film 4 is formed by thermal oxidation or CVD (vapor phase chemical reaction) on the surface of the substrate, and the emitter region is The above S for the area
A contact hole 5 is made in the iO2 film.

(b) 上記Si基体に通常の真空蒸着法により白金
(Pt)を堆積する。
(b) Platinum (Pt) is deposited on the Si substrate by a normal vacuum evaporation method.

その後400℃程度で数分加熱しSiとの低抵抗オーミ
ツクコンタクト層としてPt−Si(白金シリサイド)
層6を形成する。
After that, Pt-Si (platinum silicide) was heated at about 400℃ for several minutes to form a low resistance ohmic contact layer with Si.
Form layer 6.

なお、SiO2膜4の表面のPtはエッチングにより取
り除く。
Note that Pt on the surface of the SiO2 film 4 is removed by etching.

(c) 次に通常のスビックリング装置で全面にMo
をスパッタリングし約1 000人の厚さMo膜7を堆
積する。
(c) Next, use a normal Subickling device to coat the entire surface with Mo.
A Mo film 7 with a thickness of about 1000 nm is deposited by sputtering.

このMo膜7を形戒する理由は、Pt−Si層6に直接
Al膜を形或するとPt−Si層6中のSiとそのAl
とが相互拡散するという問題を解決するためである。
The reason for this Mo film 7 is that if an Al film is formed directly on the Pt-Si layer 6, the Si in the Pt-Si layer 6 and its Al
This is to solve the problem of mutual diffusion.

(d) Si基板1上にSiO2膜4、Mo膜7が形
成されたものの上にAlを全面に蒸着し、約6000〜
7000人の厚さにAl膜9を形成する。
(d) Al is deposited on the entire surface of the Si substrate 1 on which the SiO2 film 4 and the Mo film 7 are formed.
An Al film 9 is formed to a thickness of 7000 mm.

(e) ホトエッチングにより第1層の配線パターン
を形成する。
(e) Form a first layer wiring pattern by photoetching.

この際にボンデイングパッドは形成せず、パッドとの接
続部分までの配線を形成する。
At this time, bonding pads are not formed, but wiring is formed up to the connection portion with the pads.

すなわち、Mo膜7とAl膜9との重ね膜を同時パター
ンニングして第1層配線層を形成する。
That is, the overlapping film of the Mo film 7 and the Al film 9 is simultaneously patterned to form a first wiring layer.

(0 層間絶縁膜、たとえはCVD法によるSiO2膜
10を6000〜7000人の厚さに形成する。
(0) An interlayer insulating film, for example a SiO2 film 10, is formed by CVD to a thickness of 6,000 to 7,000 layers.

(g) 層間絶縁膜にホトエッチングによりコンタク
トホール(スルーホール)11.10aを形成する。
(g) Contact holes (through holes) 11.10a are formed in the interlayer insulating film by photoetching.

このスルーホールは後からこの上に形成するボンデイン
グバツド用のA/の下層かSiO2と十分に接触するよ
うに形或する。
This through hole is shaped to make sufficient contact with the lower layer of SiO2 for bonding pads to be formed later on.

(h) 全面にAlを蒸着、1〜1.5μのAl膜1
2を形成する。
(h) Vapor depositing Al on the entire surface, Al film 1 with a thickness of 1 to 1.5μ
form 2.

(i) ホトエッチングにより第2層配線のパターン
12aを形成、このとき同時に第2層配線に接続するボ
ンデイングバツド12bも形成される。
(i) A pattern 12a of the second layer wiring is formed by photoetching, and at the same time, a bonding pad 12b connected to the second layer wiring is also formed.

以上実施例で説明したごとき本発明によれば下記の理由
でその目的を達成でき、かつその効果もたらし得る。
According to the present invention as explained in the embodiments above, the object can be achieved and the effects can be brought about for the following reasons.

(1)ボンデイングパッド部とSiO2膜との接合部は
大部分の面積で第2層目のAlとSiO2とが直接に接
続する構造となり、AlとSiO2とは接着強度が犬で
あるから、このボンデイングバツドにボンデイング線を
接続する際に、超音波ボンテ゛イングにより強い力が作
用してもボンテ゛イング部は剥れることはない。
(1) The bonding area between the bonding pad part and the SiO2 film has a structure in which the second layer Al and SiO2 are directly connected over most of the area, and since Al and SiO2 have the same adhesive strength, this When connecting the bonding wire to the bonding pad, the bonding portion will not peel off even if a strong force is applied by ultrasonic bonding.

また、このボンデイングパッド下の絶縁被膜か特に熱酸
化によって形成したSiO2である場合、そのSiO2
はCVD法によって形成したSiO2に比べて堅いため
、超音波ボンデイング時のSin2へのエネルギー吸収
か少くない。
In addition, if the insulating film under the bonding pad is SiO2 formed by thermal oxidation, the SiO2
Since SiO2 is harder than SiO2 formed by the CVD method, the amount of energy absorbed by SiO2 during ultrasonic bonding is considerable.

それゆえ、ホンデイングパッドに対してボンディング線
は確実に接続される。
Therefore, the bonding line is reliably connected to the bonding pad.

(2)従来のA13−Mo重ね構造ではボンデイングの
数の約1優のパッド剥れによる不良かあったか、本発明
により0.01%以下に減少した。
(2) In the conventional A13-Mo stacked structure, the number of defects due to pad peeling was approximately 1% of the number of bondings, but this was reduced to less than 0.01% by the present invention.

(3)本発明の如<Mo−A6の第1層配線とAlのみ
の第2層配線を用いた2層配線構造のICにおいても、
一般のAl配線IC”のボンデイングの場合を同じ歩留
りで製造することかできる。
(3) According to the present invention, even in an IC with a two-layer wiring structure using a first-layer wiring made of Mo-A6 and a second-layer wiring made only of Al,
It is possible to manufacture a general Al wiring IC with the same bonding yield.

前記実施例以外に本発明は下記のような形態で実施がで
きる。
In addition to the embodiments described above, the present invention can be implemented in the following embodiments.

(1)Mo膜すなわちSiO2に対して接着強度の大き
くない高融点金属は少なくとも半導体基体の電極コンタ
クト部を形成し、また、少なくともボンデイングパッド
部とSiO2との接着強度が十分であるに必要なklと
SiO2の接着面積を得る範囲内において形成する。
(1) Mo film, that is, a high-melting point metal that does not have a high adhesive strength to SiO2, forms at least the electrode contact part of the semiconductor substrate, and also has the kl required for sufficient adhesive strength between at least the bonding pad part and SiO2. and SiO2 within a range that provides a bonding area.

電極コンタクト部のホールからボンデイングパッドまで
の配線は抵抗を小さくするためにはAlまたはMoとA
lの2層とすることかのぞましく、Moを単独に用いる
とよいか、抵抗が著しく大きくなり望しくない。
The wiring from the electrode contact hole to the bonding pad should be made of Al or Mo and A to reduce resistance.
It is preferable to use two layers of Mo, but it is better to use Mo alone, which is not desirable because the resistance becomes significantly large.

この発明はトランジスタ、IC,LSI等のごとき半導
体装置の電極形戒の際にすべて適用でき、特に高周波用
および高速スイッチング用半導体装置への適用は有効で
ある。
The present invention can be applied to all electrode configurations of semiconductor devices such as transistors, ICs, and LSIs, and is particularly effective in application to high-frequency and high-speed switching semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を適用した半導体装置の製造工程時の断
面図である。 1・・・・・・Si基板、2・・・・・・ベース、3・
・・・・・エミツタ、4・・・・・・SiO2膜、5・
・・・・・コンタクト・ホール、6・・・・・・Pt−
Si層、7・・・・・・Mo膜、9・・・・・・配線(
第1層)用Al膜、9a・・・・・・配線、9b・・・
・・・ホンデイング゛ノくツド、9c・・・・・・接続
部、10・・・・・・層間絶縁層(SiO2)、10a
・・・・・・コンタクトホール、11・・・・・・スル
ーホール、12・・・・・・第2層Al膜、12b・・
・・・・ボンデイングパツド。
FIG. 1 is a cross-sectional view during the manufacturing process of a semiconductor device to which the present invention is applied. 1... Si substrate, 2... Base, 3...
...Emitta, 4...SiO2 film, 5.
...Contact hole, 6...Pt-
Si layer, 7... Mo film, 9... Wiring (
1st layer) Al film, 9a... wiring, 9b...
...Honda engine socket, 9c...Connection part, 10...Interlayer insulating layer (SiO2), 10a
...Contact hole, 11...Through hole, 12...Second layer Al film, 12b...
...Bonding pads.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体本体の一生面を選択的に露出するように上記
半導体本体の一生面に形成されたシリコン酸化物から戒
る第1の絶縁膜と、上記露出された半導体本体中に形成
され、PN接合によって区画された半導体領域に対して
電気的に接続さへかつ上記第一の絶縁膜上の一部に延在
する高融点金属の下層とアルミニウムの上層の2層から
或る第1の配線層と、上記第1の配線層の表面の1部を
露出し、その端部を含む他の表面部を覆うように形成さ
れた層間絶縁膜用の第2の絶縁膜と、上記第1の配線層
が形或されていない第1の絶縁膜上の他の部分を覆って
形成されたアルミニウムのボンデイングパツドと、上記
第2の絶縁膜から露出された上記第1の配線層の表面に
電気的に接続され、かつ上記第1の配線層の端部を覆う
第2の絶縁膜上に延在し上記ボンデイングパツドと電気
的に接続されたアルミニウムの第2の配線層と、上記ボ
ンデイングパッドに接続されたボンデイング線とから成
ることを特徴とする半導体装置。
1. A first insulating film formed on the entire surface of the semiconductor body so as to selectively expose the entire surface of the semiconductor body, and a PN junction formed in the exposed semiconductor body. A first wiring layer made of two layers, a lower layer of high melting point metal and an upper layer of aluminum, electrically connected to the semiconductor region partitioned by and extending over a part of the first insulating film. and a second insulating film for an interlayer insulating film formed to expose a part of the surface of the first wiring layer and cover other surface parts including the ends thereof, and the first wiring layer. An aluminum bonding pad is formed to cover the other portion of the first insulating film where no layer is formed, and an electrical conductor is applied to the surface of the first wiring layer exposed from the second insulating film. a second wiring layer made of aluminum, which is electrically connected to the bonding pad, and which extends over a second insulating film that covers an end of the first wiring layer and is electrically connected to the bonding pad; A semiconductor device comprising: a bonding wire connected to the semiconductor device;
JP56024303A 1981-02-23 1981-02-23 semiconductor equipment Expired JPS5847854B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56024303A JPS5847854B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56024303A JPS5847854B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48038735A Division JPS5756211B2 (en) 1973-04-06 1973-04-06

Publications (2)

Publication Number Publication Date
JPS56124246A JPS56124246A (en) 1981-09-29
JPS5847854B2 true JPS5847854B2 (en) 1983-10-25

Family

ID=12134401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56024303A Expired JPS5847854B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5847854B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4827496A (en) * 1971-08-10 1973-04-11

Also Published As

Publication number Publication date
JPS56124246A (en) 1981-09-29

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