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JPS6364898B2 - - Google Patents
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JPS6364898B2 - - Google Patents

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Publication number
JPS6364898B2
JPS6364898B2 JP56184771A JP18477181A JPS6364898B2 JP S6364898 B2 JPS6364898 B2 JP S6364898B2 JP 56184771 A JP56184771 A JP 56184771A JP 18477181 A JP18477181 A JP 18477181A JP S6364898 B2 JPS6364898 B2 JP S6364898B2
Authority
JP
Japan
Prior art keywords
film
layer
titanium
electrode
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56184771A
Other languages
Japanese (ja)
Other versions
JPS5886733A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP56184771A priority Critical patent/JPS5886733A/en
Publication of JPS5886733A publication Critical patent/JPS5886733A/en
Publication of JPS6364898B2 publication Critical patent/JPS6364898B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に金属電極のボ
ンデイング領域における構造の改良された半導体
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved structure in a bonding region of a metal electrode.

高周波帯において動作を要求される。半導体装
置においては極めて浅い不純物注入層への電極金
属のシンタリグによる接合破壊等の現像防止やシ
ヨツトキバリアダイオードを形成する為に使用さ
れるPt―Si層とアルミニウムの反応防止の為に、
通常、チタン―アルミニウム(Ti―Al)、チタ
ン・タングステン合金―アルミニウム(Ti・W
―Al)、チタン―白金―金(Ti―Pt―Au)等の
多層金属電極が用いられる。しかしながら、該
Ti,Ti・W等のブロツキング層は一般に二酸化
シリコン(SiO2)等の絶縁膜との接着強度が充
分でない為にSiO2膜上に引き出された状態で形
成されている上記多層構造の金属電極層のボンデ
イング領域に金(Au)線等のボンデイングを行
つた際に、その剥離強度が大幅にばらつき、極め
て弱いものが発生し、半導体装置の品質や製造歩
留り、信頼性を低下させるという問題があつた。
Requires operation in high frequency bands. In semiconductor devices, it is used to prevent development such as junction breakdown due to sintering of electrode metal into an extremely shallow impurity injection layer, and to prevent reaction between the Pt-Si layer used to form a shot barrier diode and aluminum.
Usually, titanium-aluminum (Ti-Al), titanium-tungsten alloy-aluminum (Ti/W)
-Al), titanium-platinum-gold (Ti-Pt-Au), etc., are used. However, the
Blocking layers such as Ti, Ti/W, etc. generally do not have sufficient adhesion strength with insulating films such as silicon dioxide (SiO 2 ), so they are formed on the SiO 2 film in a state where they are drawn out. Metal electrodes with the above multilayer structure When bonding gold (Au) wire, etc. to the bonding area of a layer, the peel strength varies widely and some are extremely weak, resulting in the problem of lowering the quality, manufacturing yield, and reliability of semiconductor devices. It was hot.

本発明の目的は上記従来の欠点を除き多層電極
と絶縁膜との接着強度の強い構造のボンデイング
領域を有する半導体装置を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a bonding region having a structure in which the adhesive strength between a multilayer electrode and an insulating film is strong, eliminating the above-mentioned conventional drawbacks.

即ち、本発明は、例えば半導体基板の所望領域
から半導体基板表面の絶縁上に引き出された電極
層にボンデイング領域の構造が、ボンデイング電
極と下層の絶縁膜との間にボンデイング電極層に
対して強い接着強度を有するプラズマSiN膜が存
在することを特徴とする。
That is, in the present invention, for example, the structure of the bonding region in the electrode layer drawn out from a desired region of the semiconductor substrate onto the insulation on the surface of the semiconductor substrate is strong against the bonding electrode layer between the bonding electrode and the underlying insulating film. It is characterized by the presence of a plasma SiN film with adhesive strength.

以下、本発明実施例を図面により詳細に説明す
る。半導体基板に公知の方法により各領域を形成
した後、プラズマSiN膜を被着しボンデイング領
域部のプラズマSiN膜が残る様に加工し、その
後、金属電極を形成することによりボンデイング
領域部構造を、プラズマSiN―チタン―アルミニ
ウム(P.SiN―Ti―Al)プラズマSiN―チタン・
タングステン合金―アルミニウム(P・SiN―
Ti・W―Al)、プラズマSiN―チタン―白金―金
(P・SiN―Ti―Pt―Au)構造となることを特徴
とする。
Embodiments of the present invention will be described in detail below with reference to the drawings. After forming each region on a semiconductor substrate by a known method, a plasma SiN film is deposited and processed so that the plasma SiN film remains in the bonding region, and then a metal electrode is formed to change the structure of the bonding region. Plasma SiN-Titanium-Aluminum (P.SiN-Ti-Al) Plasma SiN-Titanium
Tungsten alloy - Aluminum (P・SiN -
Ti/W-Al), plasma SiN-titanium-platinum-gold (P/SiN-Ti-Pt-Au) structure.

上記、本発明の構造を有する電極を形成する方
法は例えば次の方法がとられる。
For example, the following method may be used to form the electrode having the structure of the present invention.

第1―1図〜第1―3図は本発明の好ましい第
1の実施例で、まず公知の方法で半導体基板に各
領域を形成した後プラズマSiN膜を約5000Å全面
に被着し、公知の方法によりボンデイング部のみ
プラズマSiN膜が残る様にフオトリソグラフイー
技術により加工しプラズマSiN膜1―3を形成す
る(第1―1図)。その後、フオトリソグラフイ
ー技術によりコンタクトを開穴し全面にPtを被
着した後、該半導体基板を500℃に加熱した後、
SiO2膜、プラズマSiN膜上の未反応のPtを、王水
等により除去し第1―2図に示すようなコンタク
ト窓にPt―Siによるベースコンタクト層1―11
エミツタコンタクト層1―10シヨツトキバリア
ダイオード1―12を形成する(第1―2図)。
その後、スパツタリング等の方法により金属電極
層、例えば、Ti層を1000ÅAl層を1.5μmの厚さに
被着し、次いでフオトリソグラフイー技術の方法
によりTi―Al層を所望の形状に加工し配線及び
金属電極層1―13,1―14を形成することに
よりボンデイング領域が絶縁層(SiO2膜)―プ
ラズマSiN―チタン―アルミニウム(SiO2―P・
SiN―Ti―Al)の構造となる(第1―3図)。
1-1 to 1-3 show a preferred first embodiment of the present invention. First, each region is formed on a semiconductor substrate by a known method, and then a plasma SiN film is deposited on the entire surface with a thickness of approximately 5000 Å. Using the method described above, a plasma SiN film 1-3 is formed by photolithography so that the plasma SiN film remains only in the bonding area (Figure 1-1). After that, a contact hole was made using photolithography technology and Pt was coated on the entire surface, and the semiconductor substrate was heated to 500°C.
Unreacted Pt on the SiO 2 film and plasma SiN film is removed using aqua regia, etc., and a Pt-Si base contact layer 1-11 is formed in the contact window as shown in Figure 1-2.
An emitter contact layer 1-10 and a shot barrier diode 1-12 are formed (FIG. 1-2).
Thereafter, a metal electrode layer such as a Ti layer, such as a 1000 Å Al layer with a thickness of 1.5 μm is deposited by a method such as sputtering, and then the Ti-Al layer is processed into a desired shape by a method of photolithography to form wiring and By forming the metal electrode layers 1-13 and 1-14, the bonding region is formed by forming an insulating layer (SiO 2 film) - plasma SiN - titanium - aluminum (SiO 2 -P.
(SiN-Ti-Al) structure (Fig. 1-3).

第2―1図〜第2―6図は、本発明を2層配線
技術に実施した本発明の第2の実施例で、まず、
公知の方法で半導体基板にエミツタ領域以外の各
領域を形成した後、各領域のコンタクトとなる部
分2―3,2―4,2―5を開穴する(第2―1
図)。その後、全面に気相成長によりポリシリコ
ン膜2―6を約5000Å成長させ、さらに熱酸化に
より酸化膜2―7を500〜600Å成長させ、その
後、窒化膜2―8を1100Å成長させる(第2―2
図)。その後、フオトリソグラフイ技術により窒
化膜2―8の所望の部分をエツチングし、その
後、熱酸化をおこなうことにより窒化膜が表面に
被着していない部分のポリシリコン膜が酸化膜に
変わり所望のパターン2―9,2―10,2―1
1が形成される(第2―3図)。その後、フオト
リソグラフイ技術により、該所望パターン2―9
部のみの窒化膜、酸化膜を除去の方法によるエミ
ツタ拡散をおこないエミツタ2―12を形成す
る。又同様にして該所望パターン2―10,2―
11部にも抵抗を下げる為にP型・N型の物質を
拡散し、ベースP+2―13、コレクタN+2―1
4を形成する。その後、ポリシリコン表面の酸化
膜を完全に除去し、白金(Pt)を被着し、該基
板を500℃に加熱した後酸化膜上の未反応のPtを
王水等により除去し配線領域2―9′,2―1
0′,2―11′を形成する(第2―4図)。その
後、全面にプラズマSiN膜2―15を約1.0μm被
着し、さらに、フオトリソグラフイ技術を用いて
所望部にスルーホールを開穴し、その後、全面に
チタン(Ti)を約1000Å被着し、さらにTi膜2
―16の上部にAl膜2―17を約1.0μm被着する
(第2―5図)。その後、フオトリソグラフイ技術
を用いて所望の形状にTi―Al膜を加工し配線部
2―18、金属電極2―19を形成することによ
り、該金属電極部のボンデイング領域が絶縁層
(SiO2膜)―プラズマSiN膜(P・SiN)―チタ
ン(Ti)―アルミニウム(Al)構造となる。
Figures 2-1 to 2-6 show a second embodiment of the present invention in which the present invention is applied to two-layer wiring technology.
After forming each region other than the emitter region on a semiconductor substrate by a known method, holes 2-3, 2-4, and 2-5 are formed to become contacts in each region (2-1
figure). Thereafter, a polysilicon film 2-6 is grown to a thickness of approximately 5000 Å over the entire surface by vapor phase growth, an oxide film 2-7 is grown to a thickness of 500 to 600 Å by thermal oxidation, and then a nitride film 2-8 is grown to a thickness of 1100 Å (second -2
figure). Thereafter, a desired portion of the nitride film 2-8 is etched using photolithography technology, and then thermal oxidation is performed to convert the polysilicon film in the portion where the nitride film is not adhered to the surface into an oxide film, forming the desired layer. Pattern 2-9, 2-10, 2-1
1 is formed (Figures 2-3). Thereafter, the desired pattern 2-9 is formed using photolithography technology.
Emitter diffusion is performed by removing only the nitride film and oxide film in the area to form the emitter 2-12. Similarly, the desired pattern 2-10, 2-
P-type and N-type substances are also diffused into the 11th part to lower the resistance, making the base P + 2-13 and the collector N + 2-1.
form 4. After that, the oxide film on the polysilicon surface is completely removed, platinum (Pt) is deposited, the substrate is heated to 500°C, and unreacted Pt on the oxide film is removed with aqua regia etc. -9',2-1
0', 2-11' is formed (Figure 2-4). After that, a plasma SiN film 2-15 of approximately 1.0 μm is deposited on the entire surface, and through-holes are made in desired areas using photolithography technology, and then titanium (Ti) is deposited on the entire surface with a thickness of approximately 1000 Å. Furthermore, Ti film 2
2-16 is coated with an Al film 2-17 of approximately 1.0 μm (Figure 2-5). Thereafter, the Ti--Al film is processed into a desired shape using photolithography technology to form the wiring section 2-18 and the metal electrode 2-19, so that the bonding area of the metal electrode section is covered with an insulating layer (SiO 2 film) - plasma SiN film (P SiN) - titanium (Ti) - aluminum (Al) structure.

上記のような方法で形成した、本発明にかかる
金属電極構造にあたつては、ボンデイング領域に
おいては絶縁層(SiO2膜)と金属電極層の間に
はプラズマSiN膜層が存在し、絶縁層(SiO2膜)
―プラズマSiN膜(P・SiN)―チタン(Ti)―
アルミニウム(Al)の構造となり、該絶縁層
(SiO2膜)と該金属電極の最下膜を構成するチタ
ン層との間の接着強度が向上するため、該ボンデ
イング領域の剥離強度が大幅に向上し、又強度の
ばらつきも殆んどなくなる。
In the metal electrode structure according to the present invention formed by the method described above, a plasma SiN film layer exists between the insulating layer (SiO 2 film) and the metal electrode layer in the bonding region, and the insulating layer ( SiO2 film)
-Plasma SiN film (P・SiN) -Titanium (Ti)-
It has an aluminum (Al) structure and improves the adhesive strength between the insulating layer (SiO 2 film) and the titanium layer that constitutes the bottom film of the metal electrode, significantly improving the peel strength of the bonding area. Furthermore, variations in strength are almost eliminated.

上記実施例においては、配線電極のブロツキン
グ層としては、チタン以外にモリブデン(Mo)、
チタン・タングステン(Ti・W)が使用されて
もよい。又、上記実施例においては本発明を半導
体集積回路に実施した場合を説明したが、本発明
は他の半導体集積回路はむろん、トランジスタ等
に適用しても可能である。
In the above embodiment, the blocking layer of the wiring electrode is made of molybdenum (Mo) in addition to titanium.
Titanium/tungsten (Ti/W) may also be used. Further, in the above embodiments, the case where the present invention is applied to a semiconductor integrated circuit has been described, but the present invention can be applied not only to other semiconductor integrated circuits but also to transistors and the like.

以上説明した様に本発明の電極構造を有する半
導体装置はボンデイング強度が大幅に向上し、し
かも強度のばらつきも殆んどなくなるので半導体
装置の製造歩留及び信頼性の向上に対して極めて
有効である。
As explained above, the semiconductor device having the electrode structure of the present invention has significantly improved bonding strength and almost no variation in strength, so it is extremely effective in improving the manufacturing yield and reliability of semiconductor devices. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1―1図乃至第1―3図、第2―1図乃至第
2―6図は本発明による半導体装置の実施例を
各々工程順に示す断面図である。 なお図において、1―1……シリコン基板、1
―2……酸化膜、1―3……プラズマSiN膜、1
―4……エミツタ領域、1―5……ベース領域、
1―6……コレクタ領域、1―7……エミツタ・
コンタクト、1―8……ベース・コンタクト、1
―9……コレクタ・コンタクト、1―10……エ
ミツタPt―Siコンタクト、1―11……ベース・
Pt―Siコンタクト、1―12……シヨツトキバリ
アダイオード、1―3……配線・電極アルミニウ
ム、1―14……配線、電極チタン、2―1……
シリコン基板、2―2……酸化膜、2―3……エ
ミツタ・コンタクト、2―4……ベース・コンタ
クト、2―5……コレクタ・コンタクト、2―6
……ポリシリコン膜、2―7……酸化膜、2―8
……窒化膜、2―9,2―10,2―11……熱
酸化により形成されたパターン、2―9′,2―
10′,2―11′……配線領域部、2―12……
エミツタ領域、2―13……ベースP+領域、2
―13′……ベース領域、2―14……コレクタ
N+領域、2―14′……コレクタ領域、2―15
……プラズマSiN膜、2―16……チタン膜、2
―17……アルミニウム膜、2―18……配線
部、2―19……金属電極部、である。
FIGS. 1-1 to 1-3 and FIGS. 2-1 to 2-6 are cross-sectional views showing embodiments of a semiconductor device according to the present invention in the order of steps. In the figure, 1-1...silicon substrate, 1
-2...Oxide film, 1-3...Plasma SiN film, 1
-4...Emitsuta area, 1-5...Base area,
1-6...Collector area, 1-7...Emitsuta/
Contact, 1-8...Base contact, 1
-9...Collector contact, 1-10...Emitsuta Pt-Si contact, 1-11...Base
Pt-Si contact, 1-12... shot barrier diode, 1-3... wiring/electrode aluminum, 1-14... wiring, electrode titanium, 2-1...
Silicon substrate, 2-2... Oxide film, 2-3... Emitter contact, 2-4... Base contact, 2-5... Collector contact, 2-6
... Polysilicon film, 2-7 ... Oxide film, 2-8
...Nitride film, 2-9,2-10,2-11...Pattern formed by thermal oxidation, 2-9',2-
10', 2-11'...Wiring area section, 2-12...
Emitsuta area, 2-13...Base P + area, 2
-13'...Base area, 2-14...Collector
N + area, 2-14'... Collector area, 2-15
...Plasma SiN film, 2-16...Titanium film, 2
-17...aluminum film, 2-18...wiring part, 2-19...metal electrode part.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の所望領域から該半導体基板表面
に設けられた絶縁膜上に引き出された電極層にボ
ンデイング領域が形成されてなる半導体装置に於
いて、前記ボンデイング領域の前記電極層の最下
層がTiを有する金属層であり、かつ前記Tiを有
する金属層の前記ボンデイング領域と下層の前記
絶縁膜との間に窒化シリコン層が存在することを
特徴とする半導体装置。
1. In a semiconductor device in which a bonding region is formed in an electrode layer drawn out from a desired region of a semiconductor substrate onto an insulating film provided on the surface of the semiconductor substrate, the bottom layer of the electrode layer in the bonding region is made of Ti. What is claimed is: 1. A semiconductor device comprising: a metal layer having Ti, and a silicon nitride layer existing between the bonding region of the metal layer having Ti and the underlying insulating film.
JP56184771A 1981-11-18 1981-11-18 Semiconductor device Granted JPS5886733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56184771A JPS5886733A (en) 1981-11-18 1981-11-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56184771A JPS5886733A (en) 1981-11-18 1981-11-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5886733A JPS5886733A (en) 1983-05-24
JPS6364898B2 true JPS6364898B2 (en) 1988-12-14

Family

ID=16159024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56184771A Granted JPS5886733A (en) 1981-11-18 1981-11-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5886733A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682704B2 (en) * 1989-06-27 1994-10-19 株式会社東芝 Semiconductor device
KR100295240B1 (en) 1997-04-24 2001-11-30 마찌다 가쯔히꼬 Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5239378A (en) * 1975-09-23 1977-03-26 Seiko Epson Corp Silicon-gated mos type semiconductor device
JPS5323567A (en) * 1976-08-17 1978-03-04 Nec Corp Electrode structu re of semiconductor element
JPS57159035A (en) * 1981-03-26 1982-10-01 Yamagata Nippon Denki Kk Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS5886733A (en) 1983-05-24

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