JPS592993B2 - magnetic bubble memory chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to double-layer conductor magnetic bubble memory chips, and in particular to improvements in the chip structure.

Compared to other magnetic field-driven devices such as permalloy devices and continuous disk devices, conventional double-layer conductor bubble devices have the advantage of being able to operate at speeds of more than an order of magnitude. It is extremely promising as an auxiliary memory.

However, on the other hand, most of the power consumed is converted into heat directly on the surface of the medium, so if left unaddressed, this not only makes chip thermal design difficult and increases costs, but also impairs reliability. It has five defects. In contrast, in conventional devices, the entire chip is divided into a storage area and an input/output area and driven independently, or the chip is divided into a larger number of areas (
A method is used to reduce power consumption by dividing the memory into sectors (called sectors) and driving each sector only when necessary. 1
However, in the former method, it is necessary to make the chip elongated in order to match the current capacity of the drive circuit, and as a result, the balance between the major loop length and the minor loop length is lost, resulting in an increase in operating time.

On the other hand, in the latter case, since each sector is driven 15 separately, the number of drive circuits and the number of input/output pins per chip increase, resulting in an increase in chip mounting cost. Therefore, none of the conventional methods can provide a fundamental solution to the above-mentioned defects. The present invention has been made in view of the above points, and it is possible to suppress the increase in the number of input/output pins of the chip as much as possible, without impairing the operating speed of the chip.
The objective is to provide a chip that can selectively obtain the optimal chip configuration, which aims to reduce drive current (enable to drive even a circuit with a small current capacity) and power consumption. be.

Double-layer conductor magnetic bubble memory is known (for example, Nikkei Electronics Magazine, February 18, 1980, pp. 155-1).
81, 3/3 issue pp145-0166, 3/17 issue pp153-164, 3/31 issue pp112-13
(In particular, the conventional chip configuration described here is published in pp. 165-166 of issue 3/3.) However, prior to explaining the embodiments of the present invention, we will explain the information retention section 5 and 5. A transfer path that performs transfer, a bubble generator that writes information, a bubble detector that reads information, a swap gate that controls the exchange of information between loops or between transfer paths, and a replicate gate that copies information.
This section provides an overview of gates and memory chips made by combining them.

However, the present invention is not limited to the components described below, and other components may be used as long as they have equivalent functions. As shown in the first diagram, the transfer path is formed by forming the j-th conductor film 3 on the carrier 1 of the magnetic bubble B with a spacer 2 in between, and providing the second layer conductor film 5 on the soil with an insulating spacer 4 in between. Become.

The first and j-th conductor films 3 and 5 have a series of opening patterns 3a, . . . , 5a, . ... are arranged, and a pair of 3a and 5a forms one bit. These opening patterns are arranged in a constant overlapping relationship along the transfer direction T, as shown by virtual lines 3a'' and 5a7 projected onto the carrier 1 in FIG. 5 is shown in an exploded perspective view, of course, each adjacent layer is in close contact with each other in the vertical direction (arrow A).Furthermore, in FIG. 1, the opening patterns 3a and 5a are elliptical, but other The shape may be rectangular, rhombic, hexagonal, etc. Positive and negative current pulses 11 and 13 perpendicular to the propagation direction T are applied to the first layer conductor film 3 constituting the transfer path, and the same is applied to the second layer conductor film 5. By applying positive and negative current pulses 12, 14 in the direction of the arrows shown in FIG. 1 in a sequence such as that shown in FIG.
, 12, 13, 14, 1, ...... on the transfer path P1 → P2 → P3 → P4 → P1 → ...
and propagate.

Therefore, by applying one cycle of current pulses, that is, once each of 1 to 14, the bubble will be 1 bit (1 step).
move only. The bubble generator consists of a hairpin-shaped conductor 7 as shown in the third diagram (hereinafter, the opening pattern shape is assumed to be rectangular), and bubbles are generated by localized current pulses IG generated when applying a current pulse IG to this conductor. A vertical magnetic field is used.

The timing of applying this current pulse IG is determined by the opening pattern 3a.
, or determined by the relative arrangement of 5a and the hairpin-shaped conductor T, and in the case of the arrangement shown in FIG. 3, the timing must be as shown in FIG. 2B.
Since the presence or absence of a bubble corresponds to the information ゞ1 // and ゞ0 ``11r, normally, only when writing the information S1'', the NO IG is applied to generate a bubble, and when writing ゞ0/7t. is not applied.

In addition, when erasing information, a current pulse of opposite polarity -1G is used.
Apply and write ゞO'' (extinguish the bubble)
. The bubble detector consists of a permalloy thin film shown as d in Fig. 4 and a lead wire 6. In order to detect bubbles, the resistance of this thin film changes depending on the presence or absence of the leakage magnetic flux of the bubble, that is, the presence or absence of the bubble (magnetoresistive effect). ) is used.

This resistance change is taken out of the chip as a voltage change. Some swap gates have configurations as shown in Figures 5A and 5B, and are called an expander 7 type gate and a magnetic field gradient 7 type gate, respectively. Depending on the presence or absence of the application of mode can be selected.

If the swap gate is always set to "swap" mode, the two small loops connected by this gate will merge and function as one larger loop. In the swap gate section, first and second layer conductor films 3,
The corner portions of the small loops Mj-1 and Mj, which face each other with the slots 30 and 31 cut out at 5, are connected to each other by a pair of intersecting opening patterns 3b and 5b, and the corners of the small loops Mj-1 and Mj are connected to each other by a pair of crossed opening patterns 3b and 5b. is each transfer path or small loop Mj-1,m
j magnetic bubble capture point Pl, P2; P7l, "P"2 (
The pairs of P1 and P''1 and P2 and P'2 simultaneously act as bubble trapping points.) In FIG. Each transfer path or small loop M connected by this swap gate cross opening pattern pair is shown with a needle line.
j-1 and mj are provided in the first and second layer conductor films in a predetermined overlapping relationship as described above; Drive current 1,
When I'' is applied, currents of opposite polarity flow in adjacent regions with the slot as the boundary, so magnetic bubble trapping points P1 to P4, P5l to P/4 (P1 and Pll, P2
and P'2, P3 and P/3, and P4 and P! 4 pairs each become a capture point at the same timing) as shown in Figure 5. Bubbles in Mj-1 and Mj reach capture points Pl, P/ below the hole edge of the cross opening pattern 3b, respectively.
If a current pulse IG (which varies depending on the type of swap gate) is applied to the gate control conductor 20 at a predetermined timing when the current pulse reaches the vicinity of the swap gate, a swap operation occurs and information is exchanged between the loops. However, if IO is not applied, it is simply a propagation operation within each loop. The operation of the expander type swap gate and the magnetic field gradient type swap gate, respectively, will be described below. first,
The operation of the expander type gate will be explained with reference to FIGS. 6B and 7.

Bubble B in the upper loop with the slot as the boundary and bubble B'' in the lower loop (identical to the figure) is reached,
When the gate current pulse IGl is applied at the timing shown in Figure 6B, the bubbles B and Bl are enlarged to become A-2 in Figure 7 (time t is [2] on the time sequence shown in Figure 7B).
) is the state corresponding to when . Next, when a current pulse 102 of opposite polarity is applied at the timing shown in 6B at the moment when a bubble trapping point is formed at PI2 and P2, each bubble B and B/ rapidly shrink while moving to PC and P2, respectively. (state of A-3 in Figure 7A; time t in Figure 7B)
corresponds to case [3]), it returns to a stable circular shape (state A-4). As a result, bubbles B and B/, which were initially in the upper and lower loops, move simultaneously to the lower and upper loops, respectively, completing the information exchange between the loops, that is, the swap operation. If there is no bubble in the predetermined position at the beginning (that is, if the information ゜07/ is retained), it can be similarly explained by considering B or B/ as a virtual bubble with ゜empty 7. , it can be confirmed that the swap operation is performed even in this case. On the other hand, in the magnetic field gradient type swap gate shown in Figure 5B, each transfer path or small loop Mj, mj
-1 when the bubbles in the gate control conductor 2 reach the trapping points Pl and P/1 under the hole edge of the cross opening pattern 3b, respectively.
When a gate current of 1G is applied to create a bubble repulsion point between P1 and P2 and between Pll and PI2, and a bubble capture point between PG' and PG, each bubble moves from P1 to P1.
GI and P! 1 → Perform PG movement. Then PI2
And the gate current is 1G at the moment when the capture point is formed at P2.
If , the bubbles that were on the capture point PG' and PG move PG/→P/2, PG-)P2, respectively, and eventually the bubble that was on P1 moves to Pt via PG', The bubble that hit P7l is P. Since the transition goes to P2 via Attach the same symbol as above.

The replicate gate has the configuration shown in Figures 8A and 8B, but since they are all based on the same operating principle, they can be explained in the same way, so below we will use the configuration shown in Figure A as a representative example. 9 (positions of capture points, etc., other than bubbles B and B7 are given the same reference numerals as in FIG. 8A). One transfer path or small loop M
Above j...→P1→P2→P3→P4→...
. . . When the bubble that has progressed reaches the bottom P1 of the hole edge of the parallel opening pattern 30 cut out by the slots 30 and 31, the gate control conductor 21 is directed to expand the bubble at the timing shown in Figure 6C. When a current 1G1 of State A2; corresponds to when time t on the time sequence in Figure B is [2]). This bubble remains at this size according to the next transfer path 1 drive current 12 and moves to the next capture point P2, P! At this moment, if a current of 1G2 is applied to the gate control conductor 21 at the timing shown in No. 6C in the direction shown in FIG. It is divided into two in the vicinity (state A-3 in FIG. 9A; corresponds to the case where time t is [3] in FIG. 9B). Since these two bubble parts naturally return to a stable circular shape (the dimensions are the same as the original one), bubbles B and BO are generated on each transfer path or small loop Mj and M, respectively (
State A-4 in FIG. 9A; corresponds to the case where time t is [4] in FIG. 9B). If there is no bubble at the beginning, no new bubble is generated by the above sequence, so the information pattern on loop Mj is copied onto M as is. In this gate, when the bubble reaches the position P1 below the hole edge of the parallel opening pattern 3c, the bubble can be extinguished by applying a current pulse of the opposite polarity. That is, stored information can also be erased on Mj. The above is an overview of the main components of a memory chip: transfer paths, bubble generators, detectors, swap gates, and replicate gates.In order to perform memory operations, these must be organically combined to form a memory chip. There is a need to.

An example of an existing typical chip configuration is shown in FIG. This chip is divided into an input/output area (or major area) 10 and a storage area (or minor area) 11, which are driven independently of each other. When reading, first,
By applying the transfer path 1 drive current of a predetermined period to the region 11 (not applying to the region 10), the current is distributed and held on each of the minor loops Ml, m2, . . . , Mn. Transfer gate Tf
(a gate that outputs or inputs information, but cannot do both at the same time).

Subsequently, after outputting this information block to the medial loop Y via the gate Tf, the current application to the region 11 is stopped, and the current application to the region 10 is started, and the information is transferred to the detector D. , converted into an electrical signal (in this case, only the leakage magnetic flux of the bubble is converted into an electrical signal, so the bubble will not disappear). After the detection is completed, the above program (M'+.) is again transferred in the same direction, and when Tf is reached, it is returned to each minor loop via this, and the read operation is completed. On the other hand, when writing, the old information at the bit position to be written is first driven out onto M' by the same procedure as when reading, and midway through, the generator G converts it into new information and then returns it to the original bit position. (i.e., stores the new information) and ends the operation. As seen above, regions 10 and 11 are driven separately in any operation, and both are driven simultaneously only during gate operation. In other words, there is no need to drive the minor area during an input/output operation (while the information is in the major loop), and on the other hand, during an access operation (while the information held in the minor loop is Since there is no need to drive one area of the major area (until the transfer gate Tf is reached), power consumption can be saved compared to a method that drives the entire chip at the same time, and heat generation from the chip can be reduced accordingly. is possible. But? In the case of Priority is given to performance factors (such as making the chip long and thin to match the impedance), and
The secondary consideration must be to balance the loop length and the minor loop length to ensure efficient operation. Therefore, the access time and cycle time increase (the data transfer rate remains unchanged because it is determined only by the frequency of the transfer path drive current),
A defect occurs in which the performance of the chip is reduced. To deal with this, conventionally, the minor area 11 is divided into a large number of sectors 111 to 115 as shown in Figure 11 (the figure shows an example where the number of sectors is 5, but this number can be arbitrarily large). ), medium area 10 and sector 11
1, 112, .
(Nothing other than that disclosed in No. 6 has been proposed yet) are arranged to form small loops Mjl and Mj+1 (1
-1, 2,..., 4; i is any number from 1 to n)
By connecting between
A chip configuration method has been proposed that allows loop Mi to be configured.

In such a chip configuration, each drive circuit only needs to supply a current commensurate with the width of the sector rather than the width of the chip, which reduces the current by that amount.At the same time, since each sector is elongated, the electrical resistance is reduced. impedance matching between the circuit and the chip is also possible. In addition, since the transfer path drive current is applied to each sector separately, it is possible to drive only the areas on the chip that are essential for memory operation (sectors containing information to be transferred). Therefore, power consumption accompanying memory operation, that is, heat generation from the chip, is further reduced compared to the example shown in FIG. In this way, the above-mentioned two defects are improved, but a new defect arises: an increase in the mounting cost due to an increase in the number of drive circuits and the number of input/output pins of the chip. As we have seen above, in the conventional methods shown in Figures 10 and 11, improving one defect creates a new defect, so there is no fundamental solution to reducing chip heat generation mentioned at the beginning. It cannot be.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a chip which has performance equivalent to that of the conventional chip and which can reduce heat generation on the chip. To outline the present invention, first, the two-layer conductor film forming the transfer path is constructed using the same planar configuration as the multi-segmented chip (Japanese Patent Application No. 55101635), that is, an incomplete slot with the left or right end left uncut. In order to reduce the transfer path drive current by creating a global meandering conductor structure (14 in Fig. 13), some of the plurality of uncut portions mentioned above are made into phases and are blown out. Therefore, it is possible to select the optimum chip division method depending on the application.

If current is applied only to the area essential for memory operation (area containing the desired storage information) among the multiple connected conductor film areas formed as a result of phase fusing, heat generation on the chip can be reduced. reduction is possible. However, if the number of connecting conductor film regions increases too much, the same drawback as the conventional example shown in Figure 11 will occur, so the number of fusing points should be determined by the number of bonding points (corresponding to the number of input/output pins, not the number of bonding pads). ) and the increase in cost due to an increase in the number of drive circuits, and the effects of reducing heat generation (for example, improved reliability, simplification of the heat dissipation system, etc.) must be considered and determined. A first embodiment of the present invention is shown in FIG.

In this embodiment, slots 11 to 16 cover the entire chip.
(The number of bushes can be arbitrary, but here we will use 7 as an example)
The conductor film is divided into row regions, and phase F1 is applied between adjacent row regions.
〜F6, and a total of 14 transfer path bonding pads P1 to P, two for each row area.
14 (of the two-layer conductor film, only one is shown; therefore, the actual number of pads is doubled; the same holds true below). In addition, in the actual chip, each slot 1
The above-mentioned replicate gates or swap gates are arranged above 1 to 15, but the gates shown in FIG.
(Figure), this is omitted. The effects of this chip will be explained in detail below. FIG. 13 shows the phases Fl, F2, and F6 in the first embodiment of the present invention being blown out, with sectors 12 (power is supplied to this area via pads Pl and P2 shown in FIG. 12) and 13 (also pads P1 and P2 shown in FIG. P
3, power supplied via P4), meandering conductor region 14 (also supplied via P4), meandering conductor region 14 (also supplied via P4
6, power is supplied via Pl2; the bottom row area is not used), a replicate gate R is provided between the major area 12 and the cache area 13, and a swap gate is provided between the cash area 13 and the minor area 14. The gate Sc is also placed on all incomplete slots in region 14.
Gates S are arranged respectively, and each gate R, Sc, and S are driven independently of each other, while all of the plurality of gates S are driven dependently.

Therefore, among the small loop groups generated as a result of dividing the minor region 14 by incomplete slots (a small loop group similar to the minor region 11 in FIG. 11 is generated), the vertically adjacent ones are simultaneously connected and equivalently form one large loop, i.e., the minor one loop m1 (1=1
, 2, ..., n). Therefore, the logical configuration of the chip is as shown by the broken line in FIG. 13, as shown in FIG.
n) is a small loop (called a cash loop) m1
(1=1, 2c...,n) and a large loop Cm
I (1=1, 2c..., n), and these are connected by swap gates, that is,
It is an on-chip cache system.

In this chip, when reading, first the cache loop Mc (i can be any number from 1 to n, so it is omitted; hereinafter, m1 is also written as ml) is searched, and the desired information is found in the cache loop Mc. If found, cache area 13
After transferring this information to the replicate gate R by applying a current to the line M, R replicates the information onto the medium line M. Subsequently, only the measure area 12 is driven to continue information transfer on M, and the bubble detector D
The information (arriving sequentially) is read by the . When all the information has been read out, the current application to the medium area 12 is stopped to complete the readout operation.
If the first desired information is cash loop M. If it is not found in the negative region 14, apply a current to the minor region 14,
Swap this information to Swap Gate S. Transfer to. Next is S. After replacing this information with unnecessary information in Mc (determined by judgment outside the chip),
Application of current to the minor region 14 is stopped. After this, the read operation is performed according to the same sequence as described above. On the other hand, when writing, first, if old information is already held at the desired bit position on the minor loop or cache loop, it is replicated.
After data is transferred to gate R and erased (an example in which the replicate gate also has an erasing function was described above), area 1
Stop applying current to 3.

That is, cash loop M. Park the bit position of the sky 7 above at the gate. The above series of operations is called initialization. Subsequently, a desired information string is written by the bubble generator G, and a current is applied to the measure area 12 to transfer this information to the replicate gate R via the measure line M. The information copied by R is a cash loop M. However, the source information remains on the medium line M, so continue to apply current to area 12 to drive all the source information out of the chip, and then write. Complete the action. As we have seen above, driving the minor region (in the case shown in Figure 13, it is four times as large as the cash region, but normally it is about an order of magnitude larger), where power consumption (and therefore heat generation) is high, is as follows. The desired information is cash loop M.

Only when it does not exist within. However, when it comes to external memory references, there is generally a locality of reference (the property that information referenced within a certain period of time is usually localized in a small area within a contiguous address space within memory). , the desired data is cache loop M. The probability of not being found within is extremely low. For this reason, even if the configuration shown in Figure 13 is used instead of the configuration shown in Figure 11, the heat generated by the chip (especially when incorporated into an information processing system with high locality) can be reduced to the same extent as the former. The chip shown in FIG.
2. In the first embodiment of the present invention, phases F2 and F6 are fused, and a conductor film region is formed in which the medial region 12 and the cashier region 13 are connected, and the cashier medial region 15 (
By supplying power to this area via pads P2 and P4 in Fig. 12, the number of transfer path drive circuits and the number of chip input/output pins can be reduced. Even after the desired information has appeared on the medium line, the cache area must continue to be driven, and the amount of heat generated on the chip increases accordingly compared to the chip shown in FIG.

On the other hand, when writing, there is a medium line M and a cache loop M. operate at the same time, so it is not possible to keep the blank 7 bit position in the replicate gate section as in the chip example shown in Figure 13.
It is necessary to rotate the cache loop a predetermined number of steps before starting writing (after erasing old information). This ensures that when the information written via bubble generator G reaches replicate gate R, M
It is possible to ensure that the empty bit on O reaches exactly the position of gate R (this is called synchronization of the major line and cache loop). However, regarding the latter, the length of the median line M and the cache loop M. By appropriately determining the length of , it is possible to automatically synchronize the loops to solve the problem. The example shown in Figure 15 is
In the first embodiment of the present invention, in order to melt down the phases F2 and F6 and to reduce the time required for initialization during writing, a write-only medium line M2 (sector 17 including this) is set as shown in FIG. Padded Pl3 inside,
(Power supplied via Pl4) and the minor loop ml are directly connected via a swap gate Sw.

With this configuration method, it is possible to simultaneously replace M2 and ml, so there is no need to erase old information before writing. First, regions 14 and 17 are simultaneously driven in parallel by a predetermined number of steps to transfer unnecessary information and desired information (information written by generator G) to the position of swap gate Sw. After the replacement r operation is completed, the storage of new information in the minor loop has been completed, so the current application to the area 14 is immediately stopped, but the current application to the major area 17 is stopped on M2. This continues until all the information released is expelled from the chip.
Although the logical configuration has been explained above limited to the on-chip cache system, other configuration methods are of course possible.

For example, in the first embodiment shown in Figure 12, the phases Fl, F6
If the swap gates Sc and S are operated in a subordinate manner (the bottom row area is not used in this case as well; see FIG. 13 for SO and S), the major-minor configuration shown in FIG. 10 is obtained. It has an equivalent chip configuration, and
In FIGS. 13 to 15, if a plurality of swap gates are operated independently of each other, a chip configuration equivalent to a bubble ladder configuration is obtained. FIG. 16 shows a second embodiment of the present invention.

In this example, there are three phases, Fl, F2, and F6, and pads are P1 to P4, P6, and Pl2 to Pl.
4 of 8 pads (the figure shows only one of the two-layer conductor films; therefore, the actual number of pads is doubled) in order to reduce the chip mounting cost. 13-1
5, the same effect can be obtained by deriving the chip configuration shown in FIG. The scope of application of the present invention is not defined by these embodiments, and since it is sufficient that phases are arranged between row areas, it is assumed that only F2 is a phase and pads P2, P4, P6, and Pl3 are arranged. or by melting F1 in advance (do not place a conductor on F1 and insulating the top row region from others), make the phase only F2, and pads Pl, P2, P3, P4, P6,
and Pl2, or other types may be used.

Finally, a comprehensive explanation of the present invention will be provided for reference when commercializing the present invention.

When the swap gate shown in FIG. 5 and the replicate gate shown in FIG. It should be noted that a current of . This is particularly true when connecting two adjacent conductor film regions that are electrically insulated by complete slots, for example region 1 in FIG.
Replicate gate R connects regions 13 and 13, and swap gate S connects regions 13 and 14. Swap gate S connects regions 14 and 15 in FIG. 14. Regions 14 and 16 in FIG. Swap gate Sw. connecting regions 14 and 17. Swap gate Sw.
Care must be taken when operating such devices. As detailed above, according to the present invention, it is possible to reduce drive current capacity and heat generation on the chip without significantly increasing the number of input/output pins on the chip or impairing the operating speed of the chip. can be achieved at the same time.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view of a main part of a two-layer conductor film magnetic bubble transfer path, and FIGS. 2A and B are explanatory diagrams of the drive current sequence of the transfer path shown in the first diagram and the drive current pulse sequence of the bubble generator, respectively. The figure shows a schematic configuration diagram of an example of a magnetic bubble generator for a two-layer conductor bubble memory, FIG. Schematic configuration diagrams of an expander type swap gate and a magnetic field gradient type swap gate as examples of gate configurations, Figures 6A, B, and C respectively show the driving current sequence of the first illustrated transfer path and No. 5A of the illustrated swap gate. a sequence of gate control pulses, and a sequence of gate control pulses for the 8th A, B replicate gate;
FIGS. 7A and 7B are explanatory diagrams of changes in the shape and position of the bubble during operation of the swap gate shown in FIG. 5A and the positions on the time sequence corresponding to each transition.
Figures A and B are both schematic plan view configuration diagrams as configuration examples of a replicate gate for a two-layer conductor bubble memory, and Figures 9A and B are respectively the shape and position of the bubble during operation of the replicate gate shown in Figure 8A. Explanatory diagram of the transition of and the position on the time sequence corresponding to each transition, No. 10, 1
FIG. 1 is a chip configuration diagram of a conventional two-layer conductor bubble memory, FIG. 12 is a schematic configuration diagram of the first embodiment of the present invention, and FIGS. FIG. 16, an example of a chip configuration derived from the embodiment, is a schematic configuration diagram of a second embodiment of the present invention. In the figure, 1 is a bubble carrier, 2 and 4 are interlayer insulating films, 3 and 5 are first and second layer conductor films, 6 is a detector lead wire, 7 is a hairpin-shaped conductor constituting a bubble generator, 3a ,3a7
, 3b, 3c are openings in the first layer conductor film, 5a, 5a'',
5b and 5c are openings in the second layer conductor, 10-17 are connecting conductor film regions on the chip, 20 is a swap gate control conductor, 21 is a replicate gate control conductor, 30 and 31 are incomplete slots, and G is a Bubble generator, D is detector, M,
Ml, M2 is the medium line, M! Mi. , m} is a minor loop, Mj is a minor loop, m^ is a cache loop, Tf is a transfer gate, S, SI, SO, Sw is a swap gate, R is a replicate gate, F1 to F6 are Phases connecting the conductor film row regions, P1 to P14 are transfer path bonding pads, and 11 to 16 are insulating slots.

Claims (1)

[Claims] 1. Among the two-layer conductor film regions formed on the substrate film that carries magnetic bubbles, vertically adjacent ones are alternately connected via a connecting part at the left end or right end to form a plurality of row regions, and each row region is What is claimed is: 1. A magnetic bubble memory chip in which a magnetic bubble transfer path is formed by an opening pattern provided in a magnetic bubble transfer path, characterized in that at least one of the connecting portions is formed by a phase.