JPS5947326B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller, and particularly to a sequence controller that allows easy changes in control specifications such as expansion or reduction of control scale.

Recently, so-called sequence controllers, which are control devices that use a stored program method, have appeared, and due to the flexibility of their programs, they are beginning to replace conventional relay boards made of hard wires.

It is true that if the stored program method is adopted, modifying or changing the program will be easier and faster than changing the wiring using hard wires. Even so, the program is modified by reading the program written on the tape using a reader, etc., and storing the new program in memory, so the operation is done by a friend or a friend in order to make this modification without error. requires appropriate training, and is not yet sufficiently easy to operate at the field level. Further, prior to developing the present invention, the inventors considered configuring the memory in which programs are stored, so-called main memory, in a building block format.

To briefly describe this method, programs according to various specifications are divided into blocks and stored in one or several LSI memory chips. If control specifications are added, a memory chip storing a program related to the additional specifications is additionally placed on the memory board. However, in general, the central processing unit (hereinafter referred to as CPU) and main memory in a sequence controller are the central parts of the system, and malfunctions in them can have a fatal impact on the system, so it is not recommended to request operation or modification of these parts. It was found that this placed an excessive burden on on-site workers. In addition, for example, when a program is stored on an LSI chip, the mechanical strength of each terminal (pin) of the LS chip is low, and repeated mounting may deform each terminal and reduce the contact function. In some cases, it even broke. In any case, manipulating and processing the memory board in response to specification changes is not appropriate for sequence controllers that require ease of operation at the field level. Therefore, the present invention is designed to store a program corresponding to the additional specifications in a part of the device necessary to realize the additional specifications, which is usually formed of one or several printed circuit boards. Implement the memory that is
On the other hand, a part conventionally called the main memory and placed integrally with the CPU stores a management program that manages program sequences according to the addition of the device, and programs related to the basic specifications, if any are essential. .

The CPU executes both the main memory and the program for the additional specifications installed, and the control scale can be changed depending on the implementation of the device for the additional specifications, thereby simplifying changes to the control specifications. The purpose of the present invention is to provide a sequence controller that is not only easy to use, but also has high operability at the field level. Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an embodiment system.

Reference numeral 1 denotes a basic control device, which controls the controlled device 6 (
control target equipment).

The memory 2 in the basic control device 1 stores the minimum necessary programs to control the controlled device 6, and by executing this program, the basic operation of the controlled device 6 is ensured. The interface circuit (referred to as 1/F) 7 transmits and receives signals between the controlled device 6 and the basic control device 1.
It is done through. Selection control devices 9 and 10 are connected to the bus 8 .

The selection control is a control related to specifications that is added to the basic control, and may or may not be applied depending on the control specifications of the controlled device 6. In the selection control device 9 (or 10),
The control circuit for additional specifications is 1/Fll (or 12
) is built in. A signal to this control circuit is given by the CPU 5 by executing a program stored in the memory 3 (or 4). I/Fll(
Alternatively, the control state of 12) is transmitted to the controlled device 6. Further, the selection control circuit 9 (or 10) not only outputs output, but also performs input control for transmitting the operating status of the controlled device 6 to the CPU 5. In this system, the control scale increases or decreases depending on whether the selection control circuit 9 or 10 is installed, but the program that manages this increase or decrease is.
If the basic control device 1 is present, it is stored in the central memory 2.

The program in the memory 2 will be explained based on the flowchart in FIG. 2 and the block diagram in FIG.

It should be noted here that all programs are executed by the CPU 5, and the parts indicated by 1 to 5 in FIG. 2 do not exist in the basic control device 1. or,
FIG. 4 shows a sketch of the apparatus in which this embodiment is implemented.

The housing 13 includes a power supply 14, a CPU board 15, and a memory board 1.
6. A control board 17 on which various circuits necessary for controlling the basic operations of the controlled device 6 are mounted, and interface (hereinafter referred to as 1/F) boards 18 and 19 with the controlled device 6 are arranged. In another part of the housing 13, a space is provided for arranging a selection control printed circuit board (selection control device) 20 in order to meet additional specifications. This selection control printed circuit board 20 includes various circuit components 21 constituting the control circuit.
In addition, one semiconductor memory SI22 is mounted. There are various types of printed circuit boards 20 for selective control, and by increasing or decreasing the number of printed circuit boards 20 or selecting them, the control contents for the controlled device 6 can be changed. FIG. 3 shows details of the system shown in FIG.

To show the correspondence between this figure and FIG. The devices 9 to 10 are configured. continue,
The progress of control will be explained with reference to FIG.

When control of the CPU 5 is started, a program routine SP1 is first executed. After initial processing such as registration and storage of control conditions is performed in this routine SP1, control of the CPU 5 is transferred to a management program that manages selection control.
Therefore, in routine SP2, a determination is made regarding the necessity of performing selection control, which is the first additional specification. Is this judgment I/F? This is done by determining whether a specific switch of the selection connection switch 23 connected to the switch is set. That is, this specific switch is the selection control device 9,1.
It is provided in one-to-one correspondence with 0. For reference here, the selection setting switch 23 constitutes one input device (or input channel) for the CPU 5. Now, in this routine SP2, if it is found that the specific switch corresponding to the selection control device 9 is "0Nj", the judgment result is "YES", and the control is carried out by the routine S indicated by 1.
Move to RI.

This program routine SRI stores a program related to the first additional specification, and by sequentially executing this program by the CPU 5, the controlled device 6 is controlled according to the additional specification. When the execution of this routine SRI is completed, the control of the CPU 5 is transferred to the routine SP3 in the main memory 2 again. In routine SP3, the selection switch 23 is pressed as in routine SP2.
to determine whether second selection control is required.

Now, if the specific switch in the selection switch 23 related to the second selection control is not set to "ON", the determination result will be "NO", and therefore the second selection control 2 will not be performed. Then, a program is executed to determine whether or not the next selection control is necessary. In this way, the execution of the program that determines whether or not the selection control of routines SP2 to SPn is necessary and the selected routines SRI to S
When the program Rn is executed, control moves to a routine SPm containing a program for controlling the basic operations of the controlled device 6.

When the program execution of this routine SPm is finished,
Control is again transferred to routine SP2. In this way, the CPU 5 sequentially executes the programs in the memory 2 or the selected and installed memories 3 and 4 (3 and 4 are selected by 0N-0FF of the selection switch 23 in this embodiment). The controlled device 6 is monitored and controlled. Next, based on FIG. 3, the hardware aspect of the system of this embodiment will be briefly explained.

The central memory 2, the basic control interface T, and the selection control device 9 including the selection control memory 3 and control I/Fll are all connected to a bus line 8 consisting of an address bus 81, a data bus 82, and a control signal line 83. It is connected to the CPU 5.

It is now assumed that the address bus 81 has a 12-bit configuration and the data bus has an 8-bit configuration.

Therefore, the engineering C memory 24 consisting of the engineering CROM has 8
One word is made up of bits, and one block is made up of 256 words. The first selection control program, ie, the aforementioned routine SRI, is stored in these 256 words. The control signal line 83 outputs a timing signal for synchronizing the CPU and each peripheral device: the memory 2, 3, the I/F 7, 11, or the selection switch 23 as an input device. Note that this timing signal serves as a gate signal when information is handled using an address bus or a data bus, and since this function is well known, a detailed explanation will be omitted. Further, a decoder 25 for controlling the IC memory 24, an address pedestal 26, and a buffer circuit 27 for buffering the output of the IC memory 24 and transmitting it to the data bus 82 are housed in the memory 3.

The lower 8 bits of the address information (12 bits) are input to the address controller 26, thereby controlling the IC memory 24.
Each of the 256 words inside is accessed separately. The upper 4 bits of the address information are input to the decoder 25, and the movement or immobility of the address controller 26 and buffer circuit 27 is controlled according to the bit pattern. Such IC memory 2
4 can be expressed in commonly used profanity: ``The 256 words of the engineering C memory 24 form one page, and the selection of each page is performed by the decoder 25.''
It turns out that. Therefore, 102 is now stored in the IC memory 24.
Assuming that it was assigned from address 4 to address 1279,
When the binary data pattern “0I00” is input to the decoder 25, the address controller 26 is turned on, and the contents (command) of the address specified by the lower 8 bits are transferred to the data bus 82 via the buffer circuit 21. CPU5
and executed. Next, the operation of the controller/Fll will be explained.

Assume that the program is currently running on the CPU 5 and an instruction (input/output instruction) for controlling the control I/F 11 is executed. Along with this input/output command, this I/Fl
Address data specifying 1 (ie, the selected pedestal device 9) is output. This address data is decoded by the I/O control circuit 28 and drives the I/0 gate 29. If the aforementioned instruction is an output instruction, the information provided via the data bus 82 is sent to the output element (usually a flip-flop) 30.
The D/A converter 31 and relay 32 are driven. If it is an input command, the status signal of the controlled device 6 is transmitted to the input element 35 via the photocoupler 34, and the status signal is taken into the CPU 5. Similar input control is performed for the selection switch 23, and its state is taken into the CPU 5.

(Here, the difference between the address data specifying the I/F and the address data indicating the memory address is the control signal 83.
It will be given at ) Next, we will briefly explain how the flowchart shown in FIG. 2 is executed in terms of hardware.

When it is determined that the first selection control is necessary in the routine SPl, the CPU 5 starts the first selection control program, that is, the start address of the routine SRl (for example, "401" in hexadecimal notation).
” is executed. This Jump
When the instruction is executed, “401” (1) is placed on the address bus.
Hexadecimal display. The same applies hereinafter) is transmitted, so the decoder 25 outputs an output due to the upper "4" and the address controller 26 is activated. With this, /C memory 2
The contents of address "01" of No. 4 are transmitted to the CPU 5, and control is executed according to the contents, that is, the command. Then “0”
The instruction at address 2 is executed. In this way, a series of instructions or routine SRl is executed. In this routine SRl, when an instruction to give an output to the D/A converter 33 is executed, the information on the address bus 81 specifies the output element 30, and the information on the data bus 82 specifies the output element 30. 3
Set to 0. The D/A converter 33 generates an analog signal according to the above data and controls the controlled device 6. The description above has mainly been about the selection control device 9, and the same applies to the selection control device 10, but since the description is redundant, it will be omitted.

As described above, in this embodiment system, the part that stores the programs related to additional specifications is installed separately from the central memory device necessary for basic control, and also has a mechanically strong printed circuit board. It is important to ensure that it will not be destroyed even if it is handled a little roughly.

Therefore, whether the CPU adopts the scan method or the interrupt method is a secondary issue. Also, selection (addition)
Providing the selection switch 23 to detect whether or not a device for the specification is mounted is not an essential configuration. That is, it reads a certain address in the IC memory 24, confirms that the content is not a specific pattern (for example, "00" or "11"), and detects that a printed circuit board for additional specifications is mounted. You may.
This means that if the board is not mounted, no output will be given to the data bus 81 even if the above read command is executed, and the "00" pattern (or "11" pattern depending on the configuration) will not be provided. This is obvious if you consider that the following information is input. Furthermore, in the above embodiment system, the selection control program routines SR1 to SRn are used only at one place in the entire program.

That is, the return address of routine SRl is specified as the start address of SP3, or the return address of routine SRn is specified as the start address of SPn. However, when actually creating a program, the routine SRi as shown above
In some cases, it may be necessary or possible to reduce the number of program steps by using the program in multiple locations. Such program blocks that are used several times in a series of programs are usually called subroutines. For subroutine control, return address status information is secured in advance before transferring control to a specific subroutine, and control is transferred by referring to the return address status secured at the last step of the subroutine. . By using this technique, the selection control routines SR1 to SRn can be regarded as if they were subroutines, and the routines SR1 to SRn can be used in multiple locations. In any case, it is easy for on-site managers to increase or decrease the scale of control simply by connecting additional control devices with sufficient mechanical strength using connectors. Although this is preferable and does not require any special training, an example in which the present invention controls a loom will now be described based on FIG.

In FIG. 5, parts such as the CPU that perform the same functions as the systems shown in FIGS. 1 and 3 are given the same reference numerals.

The controlled device includes a loom main body 61 and an input/output control section (I/F) 62 including various setting devices (not shown).

In the loom main body 61, the curled yarn 6 is supplied from the supply roller 63.
A weft thread 65 is inserted into 4 to weave the cloth, and the cloth is wound onto a winding roller 66. Weft thread detector 6? to monitor the weaving movement. , a warp yarn breakage detector 68, etc. are provided. The timing signal T indicating the weft driving operation of the loom 61 is sent to the CPU via the I/F 62.
5, and the number of times is added up. When the integrated value reaches a predetermined value, the loom 61 is stopped. The loom is also stopped if a warp thread breakage is detected or weft threads are frequently pulled out. The basic operations of the loom system 60 are managed and controlled by the CPU 5 executing a program stored in the central memory 2. Suppose now that a specially designed woven fabric with controlled warp tension is required.

In this case, a board 9 on which a control circuit with additional specifications is mounted is placed in the casing. When control is started after placing this board 9, information regarding the tension of the warp threads is transmitted from the loom I/F 62 to the I/Fll. The CPU 5 executes the warp thread tension control program in the memory 3 to control the rotational speed of the motor 69 so that the warp thread tension is maintained within a desired range. Also, assume that it becomes necessary to make a multicolor weave.

The administrator of this loom arranges the control board 10 related to multicolor weaving, and also sets the conditions for multicolor weaving in a setting device in the I/F 62 using a deciswitch. When the multicolor weave control program in the memory 4 is executed by the CPU 5, various solenoids are controlled according to the read setting conditions, and a desired multicolor weave is produced. In this way, the loom administrator can select a control board or device prepared in advance (which, of course, has a built-in program for special control) as needed.

), control specifications can be easily changed. Regarding the point that the selective control board is prepared in advance, this does not mean that additional control boards are prepared for all the looms in the factory. That is, a loom factory is equipped with several hundred looms, and it is highly unlikely that all of these looms will be controlled according to additional specifications. In other words, it would be quite useful to stock up on additional control boards for only a few dozen units and then selectively place them as needed. In addition, control specifications are generally not changed often, and equipment adjustments or maintenance work associated with specification changes is always required, and it may take only a few minutes to relocate a board or device. is not a problem.

The control device for additional specifications may consist of several or more printed circuit boards depending on the control scale, but in such cases, a special mark is attached to each specification to make it easy to identify. It is better to devise ways to do so. Another method for ensuring reliable mounting is to mechanically integrate several boards and separately provide a connector for connection to the CPU, as shown in Figure 4. It is also a good idea to insert it into the housing in a similar way. As described above, according to the present invention, the programs to be decoded and executed by the central processing unit are not concentrated only in the central side, but the memory in which the predetermined control program is stored can be added or By deleting it, the control specifications can be changed, making it extremely easy to change the program.
A highly flexible system can be configured. Moreover, the present invention
Since the memory that stores the control program is integrated with the control circuit, the equipment in which it is installed can have sufficient mechanical strength, and therefore can be handled somewhat roughly, making it difficult to handle at the field level. This is particularly suitable for systems that require changes in specifications.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the embodiment, Fig. 2 is a flowchart, Fig. 3 is a detailed block diagram of the embodiment, Fig. 4 is a sketch of the embodiment device, and Fig. 5 is a block diagram of the loom system. . 1...Basic control device, 2...Central memory, 3, 4...Memory, 5...C
PU) 6... Controlled device, 9, 10...
...Selection control device.

Claims (1)

[Claims] 1. In a sequence controller for controlling a controlled device by executing a program stored in a memory device in a central processing unit, the sequence controller includes a memory storing a control program for performing predetermined control on the controlled device, and A selective control device integrally configured with a control circuit for exchanging signals with the control device; can be additionally connected to a central processing unit, and the central processing unit executes a management program stored in a central memory. and managing the selection and discarding of the control program, and controlling the control circuit by executing the selected control program, and control specifications are changed according to adjustment of the selection control device. controller.