JPS5947327B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller that employs a stored program method.

In recent years, control devices employing a stored program method in computers have been developed as control devices to replace conventional relay boards.

The main reason for this is that in this type of device, the program is stored in the core or semiconductor memory, and changing the program changes the control specifications, which changes the conventional connection between relays. This is because it is extremely quick and easy to change. However, even in this type of sequence controller, a certain amount of training or skill is required to create or change the above-mentioned program.

Therefore, if there is a change in the control specifications, it is not necessary to add a new program according to the change.
This is not desirable because it places an excessive burden on the so-called on-site operators. On the other hand, if we look at loom control in a textile factory as an example where specifications need to be changed from time to time, in addition to essential basic controls such as managing weft thread driving operations, optional controls such as multi-color weaving control or warp tension control are provided. Control is required. However, this option control is not always necessary for all of the hundreds of looms in an entire factory; for example, only a few dozen of them are often operated with option control also performed. Furthermore, it is not determined in advance which looms require option control. Therefore, in such a case, the control specifications required for option control can be achieved by providing only a few dozen control devices necessary for option control, and placing them additionally in the loom control section as necessary. It is reasonable to configure it so that additional changes can be made.

Moreover, since such operations are performed on-site, it is desirable that the operations be easy. The present invention has been made in consideration of the above-mentioned points, and provides a sequence controller that employs a stored program method that allows easy operation for changing control specifications and can be performed reliably even at the field level. The purpose is to

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an embodiment system.

Reference numeral 1 denotes a basic control device, which decodes and executes programs in memories 2, 3, and 4 with a CPU 5, and controls a controlled device 6 (
control target equipment).

The memory 2 of the basic control device 1 stores the minimum necessary programs to control the controlled device 6, and the basic operation of the controlled device 6 is ensured by executing this program. Signals are exchanged between the controlled device 6 and the basic control device 1 via an interface circuit (referred to as 1/F) 7. Selection controllers 9 and 10 are connected to the CPU 5 via a bus 8.

The selection control is a control related to specifications that is added to the basic control, and may or may not be applied depending on the control specifications of the controlled device 6. In the selection control device 9 (or 10),
The control circuit for additional specifications is I/Fll (or 12
) is built in. A signal to this control circuit is given by the CPU 5 by executing a program stored in the memory 3 (or 4). I/Fll(
Alternatively, the control state of 12) is transmitted to the controlled device 6. Further, the selection control circuit 9 (or 10) not only outputs output, but also performs input control for transmitting the operating status of the controlled device 6 to the CPU 5. In this system, the control scale increases or decreases depending on whether the selection control circuit 9 or 10 is installed, but the program that manages this increase or decrease is
It is stored in a so-called central memory 2 of the basic control device 1.

The program in memory 2 will be explained based on the flowchart in FIG. 2 and the block diagram in FIG. do.

It should be noted here that all programs are executed by the CPU 5, and the parts indicated by 1 to 5 in FIG. 2 do not exist in the basic control device 1. or,
FIG. 4 shows a sketch of the apparatus in which this embodiment is implemented.

The housing 13 includes a power supply 14, a CPU board 15, and a memory board 1.
6. A control board 17 on which various circuits necessary for controlling the basic operations of the controlled device 6 are mounted, and interface (hereinafter referred to as 1/F) boards 18 and 19 with the controlled device 6 are arranged. In another part of the housing 13, a space is provided for arranging a selection control printed circuit board (selection control device) 20 in order to meet additional specifications. This selection control printed circuit board 20 includes various circuit components 21 constituting the control circuit.
A semiconductor memory LSI 22 is also mounted thereon. There are various types of this selection control printed circuit board 20.
By increasing/decreasing or selecting the number of printed circuit boards 20, the control content for the controlled device 6 is changed.
FIG. 3 shows details of the system shown in FIG. The correspondence between this figure and Figure 4 is as follows: CPU board 15, memory board 1
6. The control board 17 and the I/F boards 18 and 19 constitute the basic control device 1, and each of the selection control printed circuit boards 20 constitutes the selection control devices 9 to 10. Next, the progress of the control will be explained with reference to FIG.

When control of the CPU 5 is started, a program routine SP1 is first executed. After initial processing such as registration and storage of control conditions is performed in this routine SP1, the control of the CPU 5 is transferred to a management program that manages selection control. Therefore, in routine SP2, a determination is made regarding the necessity of performing selection control 1, which is the first additional specification. How this determination is made will be explained in detail with reference to FIG. This determination is made when the selection control printed circuit board 20 (selection control device 9 or 10 in FIGS. 1 and 3) in which a program related to additional specifications is stored is mounted, and the semiconductor memory 22 in the board 20 is accessed. It is done based on what is done. That is, in the program routine SP2, first, the starting address of the memory 22 on the corresponding selection control printed circuit board 20 is accessed, and
Read the contents of that address. Now, assuming that the program for selection control regarding SP2 is stored in the memory 3 (FIG. 5), the above-mentioned starting address is the "AOO" address.When this "AOOl" address is accessed, the C
The accumulator (not shown) of PU5 has “0101
0101'' pattern is set. On the condition that such a pattern is read, it can be seen that the corresponding selection control device 9 is installed and control of additional specifications is required. To explain this situation in terms of hardware, the routine SP
In step 2, a load instruction to read the contents of address "AOO" is first executed.

Along with this, the address data “AO” is sent to the address bus 81.
"O" is output, and the contents of the first address "AOO" of the memory 3 are transmitted to the CPU 5 via the data bus 82.If the selection control device 9 is not installed, even if the address data is sent out, Since the memory 3 is not accessed, all bits ``1'' are transmitted to the data bus 82 (depending on the circuit specifications, all bits may be ``0''). On the other hand, if device 9 is installed, “01
010101” is transmitted. Therefore, routine SP2
Next, the contents of the 11th accumulator are all bits "1".
” or V1 is executed, and if the selection control device 9 is installed, the judgment result is “Y”.
In the opposite case, the result is "NO", and it is possible to determine whether or not the selection control device 9 is installed, that is, whether or not selection control is necessary.

This determination is. The content of the accumulator is “010101”
It is also possible to improve the determination accuracy by performing determination detection on patterns such as "01" or 1i, which are unlikely to occur by chance. Also, as mentioned above, it is not limited to the first address, but any appropriate address in the program (usually there is a "1"
It is also possible to determine whether or not selection control is necessary by accessing the pattern (the pattern is not stored), thereby reducing the memory capacity, albeit at one address. In any case, it is important to maintain high reliability of the determination by operating the selection control device itself to determine whether or not the device is installed.

Now, in this way, the determination result in routine SP2 is "
If the answer is “YES”, the control goes to the routine SR shown in FIG.
Move to l. This program routine SRl stores a program related to the first additional specification, and by sequentially executing this program by the CPU 5, the controlled device 6 is controlled according to the additional specification. This routine S
When the execution of Pl is completed, the control of the CPU 5 is transferred again to the routine SP3 in the main memory 2.
In step 3, as in routine SP2, it is determined whether the contents of the address "BOO" are not all bits "1", and it is determined whether the second selection control is required. If the determination result is "NO", the program routine SR2 regarding the second selection control is not executed, and a program for determining whether the next selection control is necessary is executed. In this way, from routine SP2 to S
Execution of a program to determine whether or not selection control is necessary up to Pn and selected routines When the programs SRl to SRn are executed, the control is executed by storing a program for controlling the basic operations of the controlled device 6. The routine then moves to SPm.

When the program execution of this routine SPm is finished,
Control is again transferred to routine SP2. The CPU 5 thus monitors and controls the controlled device 6 by sequentially executing programs in the memory 2 or the selected and installed memories 3 or 4. Next, based on FIG. 3, the hardware aspect of the system of this embodiment will be briefly explained.

The central memory 2, the basic control interface 7, and the selection control device 9 including the selection control memory 3 and control 1/Ell are all connected to a bus line 8 consisting of an address bus 81, a data bus 82, and a control signal line 83. It is connected to the CPU 5.

It is now assumed that the address bus 81 has a 12-bit configuration and the data bus has an 8-bit configuration.

Therefore, the IC memory 24 composed of 1CR0M has 8
One word is made up of bits, and one block is made up of 256 words. The first selection control program, that is, the aforementioned routine SRl, is stored in these 256 words. A timing signal for synchronizing the CPU 5 and each peripheral device: memories 2, 3, 1/F7, 11, 12; is output from the control signal line 83. Note that this quimming signal serves as a gate signal when information is handled using an address bus or a data bus, and since its function is well known, a detailed explanation will be omitted. Also, in the memory 3, there is a decoder 25 for controlling the IC memory 24, an address controller 26, and a buffer circuit 2 that buffers the output of the IC memory 24 and transmits it to the data bus 82.
7 is stored. The lower 8 bits of the address information (12 bits) are input to the address controller 26, which allows each of the 256 words in the C memory 24 to be accessed individually. The upper four bits of the address information are input to the decoder 25, and the movement or immobility of the address controller 26 and buffer circuit 27 is controlled depending on the bit pattern. To express such address control of the IC memory 24 in commonly used words, ``256 words of the C memory 24 form one page, and each page is selected by the decoder 25.''
It will be held in ]It turns out that. Therefore, if addresses 2560 to 2815 are currently allocated to the 1C memory 24, the decoder 25 will receive binary data [101
When the pattern η of "0"("A" in hexadecimal notation) is input, the address controller 26 is turned on, and the contents (command) of the address specified by the lower 8 bits are transferred to the data bus via the buffer circuit 27. 82, taken into the CPU 5, and executed. Next, the operation of control 1/Fll will be explained.

Assume that the program is currently progressing on the CPU 5 and an instruction (input/output instruction) for controlling control 7↑11 is executed. Along with this input/output command, the address bus 81 is connected to this I/Fll.
(ie, the selection control device 9) address data is output. This address data is decoded by the I/O control circuit 28 and drives the 1/O gate 29. When the above-mentioned command is an output command, information given via data bus 82 is transmitted to output element (usually a flip-flop) 30, and D/A converter 31 and relay 32 are driven. If it is an input command, the status signal of the controlled device 6 is transmitted to the input element 35 via the photocoupler 34, and the status signal is taken into the CPU 5. (Here I/
The difference between the address data specifying F and the address data indicating the memory address is given by a control signal 83.

) Next, we will briefly explain how the flowchart shown in FIG. 2 is executed in terms of hardware.

When it is determined that the first selection control is necessary in the routine SPl, the CPU 5 selects the first selection control program, that is, the starting address of the routine SRl (for example, "AOl" in hexadecimal notation).
'') executes a Jump instruction to shift control j to . This Ju
When the mp instruction is executed, “AOl” is placed on the address bus.
(Displayed in hexadecimal, the same applies hereafter) is transmitted, so
The upper "A" causes the decoder 25 to output an output and the address controller 26 to be activated. As a result, the contents of the address "01" of the IC memory 24 are transmitted to the CPU 5, and ?Hllllll according to the contents, that is, the command, is executed.Then, the command of the address "02" is executed. A series of instructions, that is, a routine SRl is executed.In this routine SRl, when an instruction to provide an output to the D/A converter 33 is executed, the address bus 81 is
The above information specifies the output element 30, and the information on the data bus 82 is set to the output element 30. D/A converter 3
3 generates an analog signal according to the above data to control the controlled device 6. The description above has mainly been about the selection control device 9, but the same applies to the selection control device 10, but since the description is redundant, it will be omitted.

Furthermore, in the above embodiment system, the selection control program routines SR1 to SRn are used only at one place in the entire program. Moreover, routine SRl
In some cases, it may be more reasonable to use multiple times in a series of programs to compress the entire program. In such a case, it is necessary to treat the routine SRl as a subroutine. In order to facilitate understanding of the above embodiment system, an example in which the present invention is implemented in a loom system will be briefly described in FIG.

In FIG. 6, parts such as the CPU that perform the same functions as the systems shown in FIGS. 1 and 3 are given the same reference numerals.

The controlled device includes a loom main body 61 and an input/output control section (1/F) 62 including various setting devices (not shown).

In the loom main body 61, the warp threads 6 are supplied from the supply rollers 63.
A weft thread 65 is inserted into 4 to weave the cloth, and the cloth is wound onto a winding roller 66. A weft yarn detector 67, a warp yarn breakage detector 68, etc. are provided to monitor the weaving operation. The timing signal T indicating the weft driving operation of the loom 61 is sent to the CPU via the I/F 62.
5, and the number of times is added up. When the integrated value reaches a predetermined value, the loom 61 is stopped. The loom is also stopped if a warp thread breakage is detected or weft threads are frequently pulled out. The basic operations of the loom system 60 are managed and controlled by the CPU 5 executing a program (routine SPm in FIG. 2) stored in the central memory 2. Suppose now that you need a specially designed sacrificial cloth that also controls the tension of the warp threads.

In this case, the selection control device 9 in which a control circuit with additional specifications is mounted is placed in the casing. When control is started after placing this board 9, information regarding the warp tension is transmitted from the loom 1/F62 to the loom 1/Fll. By executing the warp thread tension control program in the memory 3, the CPU 5 controls the rotational speed of the motor 69 so that, for example, a D/A converter is driven and the warp thread tension is maintained within a desired range. . Also, assume that it becomes necessary to make a multicolor weave.

The manager of this loom uses the selection control device 10 for multicolor weaving.
Place. As mentioned above, when the first address of the memory 4 in which the program related to multicolor weave control is stored is read and the necessity of control is detected, the multicolor weave control program in the memory 4 is executed by the CPU 5. Various solenoids are controlled according to the setting conditions to create the desired multicolor weave. In this way, the loom administrator can select a control board or device prepared in advance (which, of course, has a built-in program for special control) as needed.

), control specifications can be easily changed. Regarding the point that the selection control board is prepared in advance, this does not mean that additional control boards are prepared for all the weaving cloths in the factory. That is, a loom factory usually has several hundred looms installed, and it is highly unlikely that all of these looms are controlled according to additional specifications. In other words, it would be quite useful to stock up on additional control boards for only a few dozen units and then selectively place them as needed. In addition, control specifications are generally not changed often, and equipment adjustment or maintenance work is always required due to specification changes, and a few minutes spent relocating a board or device is not a problem. It's not worth it.

The control device for additional specifications may consist of several or more printed circuit boards depending on the control scale, but in such cases, a special mark is attached to each specification to make it easy to identify. It is better to devise ways to do so. Another method for ensuring reliable mounting is to mechanically integrate several boards and separately provide a connector for connection to the CPU, as shown in Figure 4. It is also a good idea to insert it into the housing in a similar way. As described above, according to the present invention, the programs to be decoded and executed by the central processing unit are not concentrated only in the central side, but the memory in which the predetermined selection control program is stored is added as necessary. Alternatively, if it is deleted, the control specifications can be changed, so it is extremely easy to change the program, and a highly flexible system can be configured. Further, in the present invention, since the memory storing the selection control program is integrated with the control circuit, the device in which it is mounted can have sufficient mechanical strength, and therefore, it can be handled less roughly. It is particularly suitable for systems where changes in specifications are required at the field level. Furthermore, what is important in the present invention is that the memory itself, which is integrated with the control device and stores the program, is accessed by the central processing unit that decodes and executes the program, and the memory responds to determine whether or not it has been accessed. Detect the
The point is that the necessity of controlling additional specifications is determined.

That is, according to the present invention, when the memory is accessed, it is almost certain that the related control circuit is also installed, so the reliability of the entire system is increased. In addition, since all that is needed is to connect the control device to the various bus lines using connectors, the operation is extremely simple, and operational errors are less likely to occur, especially when the system configuration requires changes in control specifications at the field level. suitable.

[Brief explanation of drawings]

1 is a block diagram of the embodiment, FIG. 2 is a flowchart, FIG. 3 is a detailed block diagram of the embodiment, FIG. 4 is a sketch of the embodiment device, and FIG. 5 is a diagram showing details of the memory. FIG. 6 is a block diagram of the loom system. 1... Basic control device, 2... Central side memory, 3, 4... Memory, 5... CP
Ul6...Controlled device, 9,10...
Selection control device.

Claims (1)

[Scope of Claims] 1. In a sequence controller that controls a controlled device by executing a program stored in a memory device in a central processing unit, a selection control program for performing predetermined selection control on the controlled device is stored. and a control circuit for transmitting and receiving signals with the controlled device during the selection control, the selection control device can be additionally connected to the central processing unit, and the central processing unit It has a configuration that outputs a signal for accessing a memoria, detects that the memory has responded to the access signal, and determines whether or not the selection control is necessary, thereby transmitting the information to the central processing unit of the selection control device. The control specifications are changed depending on the degree of connection of the memory, and the presence or absence of connection of the selection control device in which the memory is implemented is identified by the response of the memory to the access signal. Sequence controller with special features. 2. The output of the access signal and the determination of whether or not the selection control is necessary are performed by the central processing unit executing a management program stored in a central memory provided centrally together with the central processing unit. A sequence controller according to claim 1. 3. The central processing unit accesses the memory, reads the contents of a specific address in the memory, confirms that the contents are a pattern other than a predetermined pattern, and detects that the selection control device is connected. A sequence controller according to claim 1 or 2. 4. A patent claim in which the central processing unit accesses the memory, reads the contents of a specific address of the memory, confirms that the contents are a predetermined pattern, and detects that the selection control device is connected. Range 1 or 2
Sequence controller described in section. 5. Claims 1, 2, 3, or 4, wherein the selection control device is constituted by one printed circuit board.
Sequence controller described in section.