JPS5947893B2 - Parallel analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter (hereinafter referred to as an A/D converter), and particularly to a parallel type A/D converter that compares input signals simultaneously using a plurality of comparators. .

In recent years, PCM recording and the like have been carried out, and the need for high-speed A/D converters used in the video band is increasing.

There are various types of A/D converters, such as successive approximation type, tracking comparison type, and parallel comparison type, each with its own characteristics.

Here, the parallel comparison type prepares a reference power supply and a comparator in parallel for each quantization level, and compares the analog input signal and the reference voltage of each quantization level at the same time. It is the fastest among all the devices.

In other words, this parallel type requires (2°-1) comparators to achieve n-bit resolution accuracy, but since the input analog signals are compared simultaneously, it is a high-speed A/D for analog input signals in the video band. It can be said that a parallel comparison type is optimal as a converter.

The 8-bit parallel A/D converter will be explained below with reference to the drawings.

In the case of 8 bits, the comparator and reference power supply are 28-1 = 2
There are 55 pieces.

In the figure, R is a resistor for generating the reference voltage, CI, C2
, . . . C255 is a comparator that compares the base voltage and the input analog signal, and each has the same resolution.

AI, A2. ...A255 is an AND circuit, Ll
, L2. ...L8 is a latch circuit.

1 is an analog signal input terminal, 2 is an encoder circuit consisting of a diode matrix, etc., and 3 and 4 are clock pulse generation circuits, CI, C2, . . . C, respectively.
255 and Ll, L2° is connected to L8.

Next, the operation will be explained using FIG. 2 showing waveforms of each part.

It is assumed that an analog input signal a and a reference signal S are applied to a comparator C4 on a metal plate.

Pulses c and d are applied to the comparator C4 by the clock pulse generation circuit 3, and a comparison operation is performed when the pulse C is at a high level, and a latch operation is performed when the pulse d is at a high level.

Therefore, the comparator C4 generates a comparison signal such as e, performs waveform shaping, and outputs an output signal such as f.

Here, at time T1, if the outputs of only the comparators C1 to C4 are at a high level, the output of only the AND circuit A4 is at a high level and is input to the encoder circuit 2.

The output of encoder circuit 2 is latch circuit L1...
It is input to L8 and A/
The D-converted outputs are output to terminals D1...D8.

Now, the parallel type A/D converter mentioned above has 8 bits and 25
Since it is composed of as many as 5 comparators, if a current of 1 mA is supplied to each comparator, a large current of 255 mA will be required, and if a 5 V power supply is used, the comparator alone will require approximately 1 mA current.
．． The power consumption is as much as 3W, and the power consumption of about 2W is required for all I4.

Therefore, if a high-speed, high-precision parallel rod A/D converter is constructed, the power consumption will be extremely large, making it impractical.

The present invention has been made in view of the above drawbacks and provides a parallel type A/D converter that is high speed, highly accurate, and consumes very little power.

That is, the present invention divides a plurality of parallel-arranged comparators having reference voltages corresponding to each quantization level into a plurality of groups, and, prior to the comparator operation, converts the analog signal into a plurality of groups. is compared by an auxiliary comparator, and based on the comparison result, only a predetermined group is subjected to a comparison operation.

The present invention will be explained below along with examples using the drawings.

First, FIG. 3 shows the basic concept of the embodiment of the present invention,
C is a comparator arranged in parallel corresponding to each quantization level,
SC1 to SC3 are each auxiliary comparators.

The basic configuration of the present invention is that the comparator C arranged in parallel with the analog input signal is divided into several blocks as shown in FIG. ), auxiliary comparators SC1 to SC3 having the same determination level as the comparator that detects the voltage at the boundary of the block are provided, and first, these auxiliary comparators SC1 to SC3 are used to determine the input signal voltages of blocks A, B, C, and D in advance. As a result of that judgment, only the comparator group of the predetermined block is operated, and all the comparator groups of other G blocks are operated by cutting off or reducing the operating current. This is intended to reduce the current consumption of all A/D converters.

Table 1 shows the status of the auxiliary comparator and the block. For example, when the analog input voltage is equal to the judgment level (quantization level) of the comparator in block B, the auxiliary comparator SC
1 determines that the analog input voltage is lower than the determination level of the auxiliary comparator S01, and the output becomes PP0jj.

The auxiliary comparators SC2 and SC3 determine that the level is higher than the determination level of the auxiliary comparators SC2 and SC3, and both outputs become 1''.

Therefore, at this time, only the regular comparator in block B operates, all others stop operating, and the comparator in block B accurately determines the analog signal voltage and converts it into a digital signal. be.

Therefore, in this case, if the operating currents of the comparators in blocks A, C, and D are completely set to O, the current consumption of the entire A/D converter will be approximately 10% compared to the conventional method in which all comparators are always working. can be reduced to

Of course, as the number of blocks and the number of auxiliary comparators increases, the current reduction rate also increases.

Conversely, however, if the number of auxiliary comparators is increased beyond a certain point, the current consumption of the auxiliary comparators increases to exceed the amount due to the reduction in the number of regular comparators.

For example, in the case of an 8-bit A/D converter with 255 comparators, the current consumption can be minimized when divided into 16 blocks, and the current consumption at this time is approximately 1/1.
It becomes 8.

FIG. 4 shows an embodiment of the present invention in more detail.

FIG. 4 shows an example of a 6-bit A/D converter.

In FIG. 4, 11 is an analog input terminal, 12 is a matrix encoder circuit, and 13 is a reference voltage input terminal.

C'1 to C'6 are 63 regular comparators, which compare the analog input voltage Vin and a voltage obtained by dividing the reference voltage.

R' is a reference voltage dividing resistor provided corresponding to the comparators C'1 to C'63.

INV2 to INV63 are inverters that invert the output signals of the comparators C'2 to C'63, respectively.

A'1 to A'63 are three-man-operated AND gates provided corresponding to the comparators C'1 to C'63, and the first input directly applies the output of the corresponding comparator, and the second input The input is the output of an adjacent comparator applied through an inverter, and the third input is applied the output of an auxiliary comparator, which will be described later.

L'1 to L'6 are output buffers provided for lowering the output impedance and converting the output level.

Although the conventional parallel comparison type A/D converter has the same configuration as before, the present invention adds a new part to be described below.

First, SC? ~SC3 is an auxiliary comparator and is the regular comparator 01
- C'63 is provided at a position where a reference voltage that divides approximately into four equal parts is input.

In this case, the 16th and 3rd comparators of regular comparators 01 to C'63
The same reference voltage as the 2nd and 48th ones is used as one input.

Therefore, auxiliary comparator SC1 is at the same level as comparator C'16, comparator SC2 is at the same level as comparator C'32, and auxiliary comparator SC3 is at the same level as comparator C'48.

Next, INV'1--Nv'3 are inverters, which invert the outputs of the auxiliary comparators SC1-5SC3, respectively.

Also, A″1 to A″4 are AND gates, A″1 inputs the output of the auxiliary comparator SC1, and A″2 is the inverter INV.
'1 and the output of the auxiliary comparator SC2 are input, A''3 also receives the output of the inverter INV'2 and the output of the auxiliary comparator SC3, and A''4 is the inno expansion. The output of INV'3 is used as input.

Here, the two AND gates A″1 and A″4 are not necessarily required.

In this embodiment, the AND gates A''2 and A''3 are provided in order to make their outputs, amplitudes, impedances, etc. the same.

L″1 to L″4 are buffer drivers and AND gate A
It is provided to turn on and off the current of the comparator for each block with the output of "1 to A"4.

Here, comparators C'1 to C'16 are placed in A block, comparators C'17 to C'32 are placed in B block, and comparators C'33 to C'32 are placed in B block.
C'48 is C block, comparators C'48 to C'63 are D
Block.

Next, the operation of the embodiment shown in FIG. 4 will be explained.

- The analog input signal applied to terminal 1 is first compared with the voltage corresponding to each auxiliary comparator in auxiliary comparators S01 to SC3.

Now, if the reference voltage 1■ is applied to the terminal 13, the comparison judgment level of each of the auxiliary comparators SCI to SC3 is 0.75V.
, 0.5V, 0.25V.

For example, if the analog input signal is 0.6V, the auxiliary comparator SCI determines that it is lower than the comparison level and sets the output to 0''.
Then, the auxiliary comparators SC2 and SC3 determine that the level is higher than the comparison level and output 1''.

Therefore, the output of each inverter is INV'1 is 1'',
2 becomes 'O', INV'3 becomes 0", and the input of each AND gate is A". Only the input of 2 becomes 1", and the other AND gates A"1°A" 3, A ”
The inputs of 4 are 0'' and 1'' or 0'' and 0'', and each output of the AND gate is only A''2. Provided AND gate and A'l~A'6
3 to the third input.

More specifically, A′1 to A′ of block A of A″1
16, the output of A″2 is A′17~ of block B.
To the input of A'32, A'33~ of A'33 output lock C
To the input of A'48, the output of A''4 is A'4 of block D.
It is connected to the inputs of 9 to A'63.

Therefore, the output of A″2 becomes 1″, and A″1.
Since the output of A"3.A"4 is Pro 55, only the gates of block B's A'17 to A'32 are open, and the outputs of the AND gates of other blocks are all open. It is forced to 0''.

This is a circuit for maintaining the input of the matrix encoder 12 in a correct state, no matter what the output state of the non-operating regular comparator is.

Next, the buffer drivers L''1 to L''4 respectively control the operating currents of the comparators C'1 to C'63 for each block.

Now, if the configuration is such that the comparators C'l to C.63 (current flows through and operates the comparators only when the human power of buffer drivers Ln to L"4 is 1"), the AND gate A"2
When the output of is '1', only comparators C'17 to C'32 operate, and all other comparators stop operating.

The subsequent operations are performed in exactly the same manner as before.

At this time, if the operation of the other comparators is stopped by not allowing the comparison current to flow, only the 16 comparators in block B are actually operating, so the current consumption of the entire comparator is approximately It can be reduced to 174.

However, since the three auxiliary comparators must be operated at all times, this will increase the number of comparators, but this will not be a problem as it is small compared to the number of regular comparators.

Up to 22, we have explained the case where only the comparator of block B is operated, but Table 2 shows the output of the auxiliary comparator, the status of the comparator block, and the status of the AND gate block corresponding to each analog input voltage. I'll keep it.

Next, a more specific method for the comparator block will be explained.

Two methods will be described here.

As explained above, the method of providing an auxiliary comparator at the boundary position without overlapping the comparator blocks and selectively operating one block according to the output of the auxiliary comparator is as follows. The comparison level of the auxiliary comparator must be within 172 LSB of the comparison level of the regular comparator.

However, in order to maintain accuracy, the comparators C'l to C'63 and the corresponding reference resistors R' must be formed at the same location in a repeating pattern, and the auxiliary comparators SC1 to SC
3 cannot be formed at the same location as the comparators C'l to C'63, so the comparators C'l to C'63 and the auxiliary comparators SC1 to S
There are differences in characteristics from C3.

Therefore, the following configuration is effective in preventing malfunctions.

The first configuration is as shown in FIG.
The regular comparators (indicated by diagonal lines) located near the boundaries between blocks have operating currents that are not controlled by the auxiliary comparators S01 to SC3, are always in an operating state, and have a reference voltage at the boundary. Auxiliary comparators SC1 to SC2
control the normally inactive regular comparators in blocks A-D, respectively.

In other words, if the input voltage exists at a voltage value near the block boundary, even if the auxiliary comparator malfunctions, the input voltage will be compared by the regular comparator C that exists near the boundary, regardless of its accuracy. Therefore, malfunctions can be prevented.

The second configuration, as shown in the schematic diagram of its arrangement in FIG.
Based on the determination of the auxiliary comparators SC'1 to SC'5, the comparator block that is considered to have the same comparison level as the input voltage and the blocks before and after the comparator block are operated.

For example, as shown in Table 3, the auxiliary comparator s c'
The output of i~SC'3 becomes 0'' and the auxiliary comparator SC'4.
When the output of SC'5 becomes 1'', the input signal voltage should be equal to the comparison level of the comparator in block D, so the blocks C, E and D block before and after it are operated.

This method does not require a constantly operating comparator unlike the first configuration.

However, to increase the effectiveness, it is necessary to increase the number of blocks and reduce the number of operating comparators.

Next, a specific example of controlling the operating currents of the comparators C'l to C'63 will be described.

The circuit diagram shown in FIG. 7 is the first embodiment.

In FIG. 7, Q1 to Q1. , R1-R8 is an ECL differential comparator.

Ql, Q2 have an analog input voltage of 1N on each base.
Q3. is a differential transistor pair to which Q3. Q4 is Ql and Q, respectively.
This is a cascode transistor to eliminate the Miller effect of 2, and each base is fixed with a DC bias voltage.

Q5. Q6 is a pair of transistors that perform a hold (latch) function, 6Q7, which constitutes a so-called latch circuit.
Q8 is an emitter follower transistor for impedance conversion.

Qll, Q12? Ql3. Ql5 is a constant current circuit transistor, and Ql4 is a bias diode.

R1 and R2 are load resistances for the differential transistor and latch circuit.

R3°R4, R5, and R6 are constant current circuit resistors whose current value is determined by the ratio with R9.

Also Q9. Qlo is a switching transistor, and clocks φ and T control the operation of Ql and Q2 and Q5. This is used to switch the operation of Q6 between so-called comparison operation and hold operation.

Next, R9, Rlo. Ql6. Ql□ is a reference current circuit that determines the operating current value of each part.

The reference current in this part is determined by the magnitude of Rlo.

Further, Q18 is provided as a transistor for controlling the operating current of the entire comparator circuit.

If the collector emitter of Q18 is off now, Q18
As mentioned above, the point of the present invention is to use a regular comparator to compare the analog input signal and the quantization level. The purpose of this method is to roughly judge the input level using an auxiliary comparator before comparing it with a reference voltage, and operate only the comparators at the necessary level to reduce the current.

Therefore, the timing of the comparator, which is typically clocked, is also disadvantageous in conventional methods.

That is, it is necessary to newly perform convergence of the auxiliary comparator and switching of the operating current circuit during the conventional one convergence period.

The first method that can be considered is to change the clock frequency to the conventional 2
This method doubles the number and repeats the cycle of auxiliary comparison → switching → regular comparison.

However, this method is not preferable because the time for auxiliary comparison and the time for switching are wasted compared to the original conversion time.

Therefore, in order to increase the speed, the clock frequency is left as is, and the timing of the comparator latch and the on/off of the power line of the comparator block are set within the same time.

This driving method will be explained below.

FIG. 10 shows a circuit including an auxiliary comparator that turns on and off the comparator block current, including auxiliary comparators S01 to SC3 and AND circuits A″1 to A″4 in the circuit diagram shown in FIG.
．． Inverter circuit INV'l~INV3 buffer circuit L
Play circuit D1~ having the same delay time in ``1~L''4
A circuit to which D4 is added is shown.

FIG. 11 shows a waveform diagram of each part of FIG. 10. Next, the operation of this drive system will be explained based on FIG. 11.

In FIG. 11, the analog signal a is input to the terminal 11, the auxiliary comparators S01 to SC3 operate according to the clock d, and the comparison operation is performed during the period of the clock pulse ''.
It is assumed that the latch is applied at the timing of eH11.

At time T1, the human input signal a is higher than the reference voltage S of the auxiliary comparator SC2, so the output of SC2 becomes H''.

Therefore, the output to the AND circuit A"3 becomes the "King", so the output to the AND circuit A"33 becomes the "King".

This signal "K" is delayed by the play circuit D3 and then passes through the buffer circuit L"3, and the current of the comparator of the block C is turned off by the signal g.

In other words, the timing is delayed from the timing of the L''33 output 1, and during this period, the comparator of block C performs a latching operation.

The play circuit D1 used here is one in which several stages of gate circuits are connected in series, and it is sufficient that the output of the comparator of the block C is sent to the subsequent stage before the power of the block C is turned off.

On the other hand, at this timing, the output of AND circuit A″2 is 4gH.
? ? Therefore, this “Htt level signal is output to the play circuit D2.
After , the comparator of block B is turned on by the signal.

Therefore, if the reference voltage is set at the next clock timing T2, then C
The comparator of block B, which is inserted between the two, performs a launch operation.

At timing T3, the human input signal a becomes higher than the reference voltage C, so the auxiliary comparator SC1 becomes "H" like the signal f, and the delay circuit D1. Signal after passing D2.

i turns on the comparator of block A and turns off the comparator of block B.

During this time, the comparator output of block B is transferred to the subsequent stage.

At timing T4, the comparator of block A, which is at or above the reference voltage C, is operated by the signal i, and at timing T5, the comparator of block B, which is between the reference voltages C and C, is operated by the signal i.

At timing T6, since the comparator of block B is turned on again, the comparator of block B is immediately turned off, so a sufficient play time is required for this output to be transferred to the next stage.

By giving the power switch a play function as described above, the clock pulse can be kept as it was before.

Therefore, the speed around the clock can be reduced to 1/2.

However, the outputs of the auxiliary comparators SC1 to SC3 for each block and the outputs of the comparators of blocks AD are delayed by one clock.

In addition, the present invention uses an auxiliary comparator, and as described above, some of the comparators in the block part are stopped depending on the signal. For example, if the input analog signal is a rapidly changing video signal. When power is applied to the comparator in the block, depending on the rise characteristics of the power supply,
Ringing may occur and the voltage may not fall to a predetermined value.

As a first embodiment for solving this problem, the method shown in FIG. 13 is used to solve the problem.

The principle of operation will be explained according to FIG.

Signals a and b in the figure are clock pulses for the auxiliary comparator and the block comparator, respectively, and signal a is the clock signal φ.

It is a pulse that falls in accordance with the fall of the clock signal φ, and the signal A is a pulse that falls in accordance with the falling edge of the clock signal φ.

This is a pulse that operates with a phase difference of half a cycle.

Signal C is an analog input, and d, e, and f will flow.

Next, Vo. When a voltage is applied to , and Q18 is turned on, Q1? The base potential of Q1□ becomes almost equal to GND.
+ Q129 Q13. The collector current of Q15 will almost no longer flow, and the entire comparator will stop operating.

Therefore, if Vcot is connected to the output of the buffer driver L'(˜L''4 in FIG. 4), the operating current of the regular comparator can be turned on or off based on the determination result of the auxiliary comparator.

Note that the number of comparators shown in FIG.
Therefore, the buffer driver L in Figure 4
Paras 1 to L''4 simultaneously control Q18 provided in comparators C'1 to C'63.

The first embodiment of operating current control has been described above. Although this method has the advantage of a simple circuit configuration, it is not possible to switch at a very high speed because the transistor Q18 operates in saturation.

Therefore, there is a second method described below in order to further increase the speed.

FIG. 8 shows a circuit diagram of a specific embodiment of the second operating current control.

In FIG. 8, the main part of the comparator is omitted, and only the part that determines the reference current for the constant current circuit and the switching part are shown.

Q169 Q17S R9 and RIO are the same elements as those in FIG.

Here, the switching circuit is R1. Rx2t
It is composed of R13, R149Q191 Q20.

To explain the operation of this circuit, V when the comparator is operating.

Transistor Q19 can be turned off by keeping ot higher than the base voltage of Q19, and the current flowing through Rlo is equal to the collector current of transistor Q17 and Q16.
becomes the base current and generates a constant base voltage VB,
Since this voltage (8) is the control voltage for the constant current circuit of the entire comparator, an operating current flows through the comparator.

Now V. When the voltage of 0□ is lower than the base voltage of Q19, Q20 is turned off and Q19 is turned on.

At this time, if R14 is made small and the current flowing through Q19 is made large, the current flowing through Rlo is almost Q.
Since the current flows into the collector of the transistor Q19, the voltage at the base potential (2)8 of the transistor Q17 becomes low, and the current in the constant current circuit decreases.

Therefore, when reducing the operating current of the comparator, ■.

■ When setting 0□ to a low level and performing an operation.

All you have to do is raise OL to a high level.

The feature of this method is that the differential switching transistors Q191 and Q20 can be operated in non-saturation.
This enables high-speed switching.

■co□ is the inverted signal of ■oo□ in Figure 7, and the fourth
Inverted outputs of the buffer drivers L''1 to L''4 shown in the figure may be used.

Next, AND gates A'l~ provided between the comparators C'l~C'63 and the matrix encoder 12 in FIG.
A'63 will be specifically explained.

In the conventional example, this AND gate logically ANDs the output of the n-th comparator and the inverted output of the n+1-th comparator, and sets only the output of the comparator corresponding to the input analog voltage to 1''.
' and converts it into a binary signal using a matrix encoder.

In the present invention, the input of this AND gate is forced to 0'' for each block according to the output of the auxiliary comparator by three people.
This is what we are trying to do.

FIG. 9 shows a circuit diagram of a specific embodiment.

In FIG. 9, the parts consisting of Q1 to Q18 and R1 to R9 are the same as the comparator in FIG. 7, and Q21 to Q2
9 and R1 to R20 is an AND gate part.

Here Q14. Unlike the case shown in FIG. 7, the bias circuit formed by Ql, , R6, R7, and R8 also serves as a base bias for the AND gate differential transistor Q2, so that the constant current transistors Q1, . The base is R17, R19°Q27. to fix it. It is connected to a second reference current circuit formed by Q28.

Q2□, Q2□+ Q23. Q24 is R1,, R1
An ECL AND gate is configured with ・ as a load.

Q29°R20 is a constant current circuit.

Q25 is Q26. The emitter follower transistor with R18 as a constant current circuit lowers the output impedance.

Now, the inverted output of the comparator in the previous stage is connected to the base of Q22, the output of the next comparator is applied to the base of Q23, and the auxiliary comparator L″1 to L″4 side is applied to Q24. The outputs (VCOT2) of AND gates A''1 to A''4 are connected.

Therefore■. Only when o1□ is at a low level, the gate opens and the output of the comparator is ANDed with the inverted output Qn+1 of the next comparator.

Here, for convenience of explanation, AND circuits A'l to A' in FIG.
Unlike 63, the explanation is made using a negative logic OR circuit.

When VCOT2 is at a high level, the output OUT is forced to a low level, and even when the comparator is not operating, a correct signal is input to the input of the matrix encoder.

The reference voltages of the auxiliary comparators S01 to SC3 shown in FIG. 4, the signal g, are the output of the auxiliary comparator SC2, and the signal g is the output of the auxiliary comparator SC3.

Here, in the waveform diagram of signals g and h, the solid line portion indicates the comparison operation, and the diagonal line portion indicates the latch operation.

In this embodiment, the comparators of blocks A to D are first powered up and all operate together with the comparison operations of the auxiliary comparators S01 to SC3.

Next, when the comparators SC1 to SC3 of blocks AD are latched, the power is turned on or off depending on the comparison result.

Therefore, the comparators of blocks A and D are turned on and off every half cycle like signal i.

Also, the comparator of block B operates like signal j.

Furthermore, the comparator of block C operates like a signal.

In this way, as is clear from signal k, the comparison of block C is performed at the timing shown in the figure.
The power of the comparator that is turned on at the point ■ in the signal is maintained without being turned off at the point ■, so when the comparator compares, it remains on for a considerable time from the point ■, for example. The power supply rise noise generated in step (3) is also eliminated during the comparison, which is a very effective means especially when the clock speed is 10 MH2 or more in the high-speed comparator according to the present invention, and the damping of the power supply noise cannot be ignored. Become.

For reference, the signal p shows the adverse effects when the power supply is not turned on and off based on the invention.

In other words, in this case, in response to the signal from the auxiliary comparator, the power is turned on rapidly from the detection point ①, and the points 7 and 7 are very close to each other when the comparator compares, resulting in a sudden movement. For a video input signal that does this, the time of comparison and the power-on time are too close together.

Therefore, if power supply ringing or the like occurs, there is a possibility that a convergence error may occur.

Also, regarding the power reduction ratio when the comparator is turned off, video signals generally do not change very quickly, and in most cases only one block or a whole number of In many cases, only one-third of the blocks are used, and the proportion of blocks that must be constantly powered on is small.

Other blocks are on duty at a ratio of 1:1.
Due to the current being turned off, the power is down by 50%.

Therefore, in parallel comparison type A/D converters where the comparator is the main power consumption source, the power down ratio is 30 to 40%.
The effect is extremely large.

In addition, in this system, the power is turned on much earlier than in the comparison, so the system configuration is such that power supply noise can be ignored.

We implemented a method of turning on the power one or two clocks earlier than when comparing the comparators of each block, but this requires a function to temporarily store the video signal in analog memory, so it is slightly We must be prepared for the system complexity to increase.

Next, the video signal is 3.58M in the case of NTSC system.
Hz, even in the PAL method, it is 4.5MH2, and its sampling frequency is four times that, from 14MH2 to 18MHz.
MH2 is used.

However, actual video signals generally do not change so sharply.

For example, if 256 comparators are lined up like an 8-bit A/D converter, the optimum number of auxiliary comparators is about 16, and for every 16 comparators, there should be 1 auxiliary comparator.
The ratio will be 1.

Therefore, even if the analog signal fluctuates considerably, it generally takes a considerable amount of time for the analog signal to pass through the two auxiliary comparators, and it is often virtually pointless to constantly move the auxiliary comparators. .

In addition, in order to send the output detected by the auxiliary comparator to the comparator of each block within one cycle delay, the auxiliary comparator output processing circuit and comparator power control circuit must operate at extremely high speed. This will require the following.

In addition, since the auxiliary comparator itself operates at high speed, sufficient power must be supplied, and the original purpose of power down cannot be achieved.

Therefore, in this embodiment, the speed of the auxiliary comparator is made sufficiently slow,
For example, the output of the auxiliary comparator every 10 clocks is used to control the power supply of the comparator in each block.
Thereby, the power consumption of the auxiliary comparator is low, and the configuration can be relatively simple without requiring high-speed power supply control logic.

One embodiment will be described using the timing chart in FIG. 13 and the relationship between the comparator output and block output in Table 4.

By the way, in explaining the present invention so far, the auxiliary comparators have been provided corresponding to the lowest reference voltage of each comparator block, but in this embodiment, the auxiliary comparators are provided corresponding to the lowest reference voltage of each comparator block A to D. Auxiliary comparator SC'1~ with reference voltage
SC'4 is provided corresponding to comparator blocks AD.

Therefore, for the output results of the auxiliary comparators SC'1 to SC'4.

The operating status of the comparator block is as shown in Table 4.

Now, in FIG. 13, signal a is a clock pulse that drives the comparators constituting blocks A to D, and the frequency is 1.
We are assuming 4-18MH2.

The signal is a clock pulse for the auxiliary comparators SC'1 to SC'4, and a level signal is output every 10 pulses of the basic pulse.

Signal C is an analog input signal, and one comparison voltage d is assumed as the comparison voltage of auxiliary comparator SC'2.

Signal e indicates the output signal of the auxiliary comparator SC'2,
The level is held until the second pulse of the signal comes in.

From the first pulse to the second pulse of this signal, the comparator of the block selected based on the comparison result of this auxiliary comparator compares the analog input signal C 10 times.

f=i indicates the variation in the power supply voltage value from blocks A to D.

Since the analog signal does not change much during these 10 pulses, that is, about 700 nS in the case of a 14 MH2 chlorus pulse, block D is always off and block B is always on.

Since the output of the auxiliary comparator SC'2 changes from 1'' to 0'' at the second pulse of the signal, block C changes from off to on, and power is applied slowly. .

Even in such a slow application state, the auxiliary comparator changes every 10 pulses, so no problem occurs.

As described above in detail with the embodiments, the feature of the present invention is that by using auxiliary comparators, only some of the comparators are operated for a certain period of time, and the operating current of other comparators is reduced to 0. With this method, it is possible to realize an A/D converter with high accuracy and low power consumption without losing the high speed which is an excellent feature of the parallel comparison method.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional parallel A/D converter, Figure 2 is a block diagram of a conventional parallel A/D converter.
The figure is a timing diagram showing the operation of the A/D converter, Fig. 3 is a basic conceptual diagram of the present invention, Fig. 4 is a block diagram showing one embodiment of the present invention, and Fig. 5 is a diagram showing other embodiments of the present invention. FIG. 6 is a conceptual diagram showing still another embodiment of the present invention,
FIG. 7 is a circuit diagram showing a specific embodiment of the comparator of the present invention;
FIG. 8 is a circuit diagram showing a specific embodiment of the comparator operating current control circuit of the present invention, FIG. 9 is a circuit diagram showing a specific embodiment of the comparator and AND gate of the present invention, and FIG. 10 is a circuit diagram of the present invention. A block diagram illustrating an embodiment of the clock method according to the invention,
FIG. 11 is a timing diagram explaining the same clock method, FIG. 12 is a timing diagram explaining another clock method according to the present invention, and FIG. 13 is a timing diagram explaining still another clock method according to the present invention. be. C'l~C'63...Comparator, SC1~SC3
...Auxiliary comparator, A'l~A'63...
・3 person Kaand gate, A″1~A″4・・・・・・2
Person and gate, L'1 to L'6...Exit cover sofa, L''1 to L''4...Buffer driver, INV1 to INV'63. INVI~INV' 3・
...Inverter, R'...Resistor, 11.
... Analog input terminal, 12 ... Matrix encoder, 13 ... Reference voltage source.

Claims (1)

[Claims] 1. A plurality of comparators having reference voltages corresponding to each quantization level and arranged in parallel, and dividing the plurality of comparators into a predetermined number, and each of the divided comparators having a reference voltage corresponding to each quantization level. and an auxiliary comparator provided for each comparator group, and the input signal is compared by the auxiliary comparator. A parallel analog-to-digital converter, wherein each of the comparators in the comparator group operates based on a comparison result of the auxiliary comparator corresponding to the comparator group.