JPS599995B2 - charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device, particularly a two-dimensional array in which a plurality of one-dimensional charge transfer elements are arranged. The present invention provides a semiconductor device that can correct the fluctuation and obtain a proper two-dimensional array output signal under a constant reference level.

Conventionally, charge transfer devices have a structure in which, for example, a thin insulating film is provided on a semiconductor substrate, and a plurality of independent electrode rows are provided on the insulating film, and the charge coupled device is operated by three-phase circuit means ( CCD■ChargeCou-pledDevic
e) Two-phase drive CCD) A packet brigade device (BBD) that has multiple MOS transistors and charge storage capacitors on a semiconductor substrate and is operated by a two-phase clock.
There are many proposals such as e).

In the following description of the present invention, for convenience of explanation, a packet brigade element will be used for the explanation, and then it will be stated that the present invention is applicable to charge transfer elements of other structures as well. FIG. 1 shows the basic circuit of a packet brigade element.

Here, 1 to T represent MOS transistors, 8 to 12 represent capacitors, and 13 represents a resistor. Clock signals φ1 and φ2 having mutually opposite phases are applied to 14 and 15, and a drain voltage VD is supplied to IT.

16 is an input terminal, 18 is an output terminal, and here, the input terminal 16 is of a type in which a charge is read by a capacitor 8;
As an example of a means for extracting the transferred charge, a method is shown in which the potential appearing at both ends of the resistor 13 is detected by a source follower circuit including a transistor T.

Note that the arrow indicates the direction in which charge is transferred. FIG. 2 shows a sectional view of the basic structure for forming the circuit of FIG. 1 on the surface of a semiconductor substrate.

Semiconductor substrate 19 (N-channel MOS transistor, -
First, a diffusion layer 20 of the opposite conductivity type to the substrate (an N-type impurity diffusion layer when forming an N-channel MOS transistor) is used as a source/drain electrode, and a thin ( Two or more gate electrodes 22 are arranged with an insulating film 21 interposed therebetween.

Clock signals φ1 and φ2 having mutually opposite phases are applied to the gate electrode 1 from terminals 23 and 24. In addition,
A charge storage capacitor (bucket capacitor, for example 9 to 12 in FIG. 1) for charge transfer has a gate electrode 22 connected to a drain electrode 2.
It is formed by the MOS capacitance generated in the overlapping portion between the two. Next, the method by which charges are transferred by the circuit shown in FIG. 1 will be briefly explained as follows.

The input electrical signal S applied to the input terminal 16 is read into the capacitor 8 by the transistor 1 by applying the clock signal φ1 to the terminal 15. At this time,
Since φ1 is applied to the terminal 15, the transistors 3 and 6 are also opened, and in the steady state of this circuit. teeth,
Capacitors 9, 11, and 12 are set to a transfer reference voltage VB (reference level). Next, when the clock signal φ2 is applied to the terminal 14, the transistors 2, 4, and 5 open, and if the voltages of the clock signals φ1 and φ2 are equal to Vφ, the potential of the capacitor 9 becomes φ+VR, and the potential S of the capacitor 8 becomes Since the potential of capacitor 8 is VR
and the potential of capacitor 9 vφ+VR-(R-
S)=φ+S. When the clock signal φ2 becomes zero, the potential of the capacitor 9 becomes S, and the charge of the capacitor 8 is transferred to the capacitor 9. Incidentally, at this time, the capacitor 10 is also set to B at the same time. In this way, when φ1 is applied next, the input electrical signal S is transferred to the capacitor 10, and thereafter, by alternately applying φ2 and φ1, the signal is repeated as many times as the number of bits in this circuit. After that, the input electrical signal S applied to the terminal 16 becomes the potential across the resistor 13 of the source follower circuit and is taken out to the output terminal 18 at the timing of the clock signal φ2. Now, FIGS. 3 and 4 show a two-dimensional array in which a plurality of charge transfer elements (bucket bridge elements are used as an example here) as described above are arranged.

The arrows in FIGS. 3 and 4 each indicate the direction in which charge is transferred. In Fig. 3, A1 to A8, Bl, respectively.
~B8, . . . H1 to H8 are charge transfer elements constituting each column of the two-dimensional array.

The input electrical signals applied to the input terminals 25 are respectively A
1 to A8, Bl to B8, . . . H1 to H8, and taken out as parallel outputs to output terminals A, B, . . . H. In FIG. 4, similar to FIG. 3, AV-A8', BV-B8',...HV-H8
' are charge transfer elements constituting each column of the two-dimensional array. The input electrical signal applied to the input terminal 26 is
They are shifted by AV-A8', BV-B8', HV-H8' and output in parallel to A', B', . 2
7, and the output of the two-dimensional array is eventually taken out to the output terminal 28 as a time-series serial output.
In Figures 3 and 4, the input terminals are represented by a single common line 2-5, 26, but if the charge transfer elements in each column have separate input terminals, The same is true.

Furthermore, such two-dimensional arrays are used, for example, in shift registers, optical sensors, etc., but in these cases the input terminals for each bit are omitted, and the third
It is sufficient to consider that FIG. 4 and FIG. 4 show only the transfer stages of those input signals. Now, the charge transfer elements A1 to A8, B1 to B8, H1 to H8 and the fourth
Charge transfer elements AV-A8', BV-B87 in each column in the figure,
The HV-H8' operates in exactly the same way as the circuit shown in Figure 1, but there are various problems such as when operating these circuits at high speed, when leakage current is large, when transfer efficiency is poor, etc. For some reason, the reference level and input signal transfer may not be carried out completely according to theory.

At this time, even if the input signal VI is kept constant, for example, each element Al, A2, A1 to A8, etc.
- The VIN value transferred in A8 differs for each element. In order to observe this situation, a waveform as shown in FIG. 5 was used. In other words, the input signal VIN-circle [fifth
A] is applied to the input terminal 25, and by intermittent clock signals φ1 and φ2 as shown in FIGS.
Charge transfer elements No. 1 to A8 were driven. At this time, the waveform of the output terminal A was observed, and the result was as shown in FIG. 5D. In the figure, 29, 30, . . . 36 are respective elements A of the charge transfer element for the same input signal VIN.
1, A2, . . . corresponds to the VIN value transferred to A8. In other words, the element A1 is activated by a clock signal in which periods in which the clock signal is inactive and periods in which the clock signal is generated alternate, such as the clock signal shown in FIGS. 5B and 5C when an imaging signal is read out by a charge transfer element. ~
In the drive method for driving the A8 charge transfer element,
At the end of the clock signal generation period, each element Al, A2, ..., A8 of the charge transfer element is in a state where the input signal IN is transferred and set at a steady level R (ZVIN). , after the clock signal has stopped, the clock signal is generated again. Therefore, the output signal from element A8 is VTi minus 8 stages of the signal ΔV leaked from each transfer stage to the board during the idle period (V8-8×Δ), as shown in FIG. The signal has a height of 29. Next, the output signal from element A7 passes through element A8, which is set to a certain reference potential VR by the power supply terminal (for example, 17 in Figure 1), so that leakage to the board is reduced by 7 stages (VR7 x Δ), and sequentially the output signal from A6 becomes (R - 6 x Δ), the output signal from A5 becomes (R - 5 x ΔV), ..., the output signal from A1 becomes (VR - ΔV). Therefore, the subsequent output signal approaches the steady value VB (+VIN) of IN transfer. In this way, the apparent charge transfer elements A1 to A8 after a certain rest period have characteristics as shown in FIG. 6. In the two-dimensional array shown in FIG. 3, the charge transfer elements in each column, ie, A1 to A8, Bl to B8, . . . H1 to H8, are arranged as shown in FIG. If it has this characteristic, it will cause great inconvenience. In other words, even if the same input is applied to each element, the signal that is output later (that is, A1
〜Signal at H1) is the signal output earlier (A8〜
The DC level of the output is lower than the signal at H8). Furthermore, even when inputs are read into each element of a two-dimensional array in parallel, the reference levels are different, so the same parallel inputs are read as different levels. These effects are noticeable, for example, in image relationships. For example, if a video signal is transferred using a two-dimensional array with the characteristics described above and then restored to an image,
Only one side of the image will be brighter than the other side of the image, ie there will be shading. These drawbacks become more serious as the transfer stage becomes longer and the image processing frequency, that is, the driving frequency of the charge transfer element becomes higher. Furthermore, in the two-dimensional array of the system shown in FIG. 4, if the charge transfer elements 27 for parallel-to-serial conversion have similar characteristics, the fluctuation in the DC level of the output signal obtained at the output terminal 28 will be It becomes even more intense and the output signal becomes even less correct.

Therefore, an object of the present invention is to provide a two-dimensional array of charge transfer devices in which a plurality of charge transfer devices as described above are arranged.
By correcting the above-mentioned drawbacks, namely, the variation in the reference level when input is read in parallel to each element of the two-dimensional array, and the variation due to the output order of the output signal in the output signal of the two-dimensional array, it is possible to simply maintain a constant level. The object of the present invention is to provide a charge transfer device that can obtain an appropriate two-dimensional array output signal under a standard DC level of .

According to the present invention, a two-dimensional array of charge transfer elements has a capacitor with a capacitance approximately equal to the same number of transfer stages as charge transfer elements in each column of the two-dimensional array, which is attached to the two-dimensional array; The above object is achieved by a charge transfer element made of a semiconductor device having circuit means for comparing and correcting the output of a charge transfer element having a terminal and an output terminal with the output of a two-dimensional array. Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 7 shows the configuration of a two-dimensional array of charge transfer elements as an example for explaining the present invention. FIG. 7 shows a configuration in which the present invention is implemented in the 8-bit x 8-bit two-dimensional array shown in FIG. In Figure 7, Al
2~A82, Bl2~B82...Hl2~H8
Reference numeral 2 denotes charge transfer elements constituting each column of the two-dimensional array.

The output of the two-dimensional array is the output terminal A of the charge transfer element in each column.
2, B2, . . . are taken out as parallel outputs to H2. Xl2 to X82 are charge transfer elements according to the present invention, and charge transfer elements Al in each column of the two-dimensional array
2~A82, Bl2~B82,...Hl2~H
82, each of which has the same number of transfer stages, capacitors of approximately the same capacity, input terminals, and output terminals.
Note that the charge transfer elements Al2 to A8 in each column of the two-dimensional array
2. The input terminals of Bl2 to B82, . be.

The input electrical signal VIN now applied to the input terminal 41 is
In the direction of the arrow in Fig. 7, Al2 to A82, Bl, respectively.
2 to B82,... Hl2 to H82, and if input signals are applied to each element of the two-dimensional array in parallel, the output terminal A
2, B2, . . . appear as parallel outputs on H2.

At this time, the input signal VIN(
For example, V·IN-X=-VR. ) is applied and shifted by the charge transfer elements Xl2 to X82, and the output terminal X2
This detects the different characteristics of the amount of charge transferred to each element of the transfer stage in each column of the two-dimensional array and inputs it to the device 43. In the device 43, the characteristics of the input charge transfer element are inputted in time series, that is, among the outputs A2, B2, . . ., corresponding to Al2, Bl2, . , A22, B22...X22 corresponds to H22,...A82, B82,...
. . . X82 is input to the comparison correction circuit 44 in correspondence with H82. The comparison and correction circuit 44 rereads the outputs of the charge transfer elements in each column of the two-dimensional array using the output DC levels of the charge transfer elements X12 to X82 as reference levels, and outputs a corrected output to the output terminal 45. This situation is shown in FIG. 8 by waveforms at various parts.
When input VIN-A as shown in FIG. 8B is applied to the input terminals of the first column charge transfer elements Al2 to A82 of the two-dimensional array,
The output A2 of the charge transfer device described above is as shown in FIG. 8C as described above. Here, the characteristics of this charge transfer element are determined by the output X2 of the charge transfer elements Xl2 to X82 as shown in FIG.
If it is known that the characteristics are as follows, the comparison correction circuit 44 sets the waveform of FIG.
The output shown in Figure C will be read, and the output obtained at the terminal 45 will be as shown in Figure 8D. The output D obtained at the terminal 45 in this way is initially
It can be reproduced with exactly the same waveform as input B applied to A82. Therefore, according to the present invention, no matter what the characteristics of the charge transfer elements in each column of the two-dimensional array are, the output signal of the two-dimensional array can always be correctly obtained under a constant reference level. It is possible. FIG. 9 shows an embodiment of a circuit for realizing a coupling circuit for comparing and correcting output signals in a two-dimensional array as described above.

In the same figure, Al2 to A82,..., Hl2
~H82, Xl2~X82 are respectively Al2~ in Figure 7
A82,...Hl2~H82, Xl2~X82
These are charge transfer elements that constitute each column of a two-dimensional array corresponding to . Further, 44 is a charge transfer element for parallel-to-serial conversion;
3 and 44 indicate comparison and correction circuits. The operation of the circuit shown in FIG. 9 will be explained.

Parallel outputs A2, B2,...H2 of two-dimensional array
In other words, before the charge transfer element 44 for parallel-to-serial conversion is read, a control pulse is applied to the terminal 80 to
Before opening 82, . Each capacitor 75, 77, 79 of the charge transfer element 44 is opened by opening 64.
Load it into. Therefore, the DC level
2 as a reference level, then apply a control pulse to the terminal 80 to open the gates 81, . . . 83, and change the parallel outputs A2, B2, . The data is read into each capacitor of the transfer element 44. In this way, each capacitor 7 of the parallel-to-serial conversion charge transfer element 44
5, 77, . . . 79, the outputs of the charge transfer elements in each column of the two-dimensional array, which have been compared and corrected using the output DC levels of the charge transfer elements Xl2 to X82 as reference levels, are serially connected. By applying a clock pulse to terminals 66 and 67 as an output, it is obtained at output terminal 45. In the above description, for the sake of simplicity, the above-mentioned characteristics of different DC levels in the parallel-to-serial conversion charge transfer element 44 are not taken into consideration. Furthermore, the present invention can be similarly implemented in a system in which the output of a two-dimensional array is taken out as a serial output as shown in FIG. FIG. 10 shows an example in which the present invention is implemented in a two-dimensional array using the serial output extraction method as described above.

In FIG. 10, charge transfer elements Xl4-X84 are arranged in each column Al4-A84, Bl4-B84, . . . of a two-dimensional array.
...A charge transfer element having the same number of transfer stages as each of H14 to H84 and capacitors with almost the same capacity,
Further, the charge transfer element 56 is a correction charge transfer element having the same number of transfer stages as the charge transfer element 55 for parallel-to-serial conversion and capacitors having approximately the same capacity.

Now, when an input signal having a certain reference level is applied to the input terminal 42, it is shifted by the charge transfer elements Xl4 to X84, and the characteristics of the charge transfer elements Xl4 to X84 appear in X4. Further, when an input signal having a certain reference level is applied to the input terminal 60, it is shifted by the correction charge transfer element 56, and the characteristics of the charge transfer element 56 appear at the output terminal Z4. Therefore, the charge transfer elements Al4 to A84, B14 to B84 in each column of the two-dimensional array...
. . . This means that an output that can equivalently detect both the characteristics of H14 to H84 and the characteristics of the charge transfer element 55 for parallel-to-serial conversion is obtained. In this way, the serial output Y4 of the output signal of the two-dimensional array and the reference level outputs X4 and Z4 described above are applied to the comparison correction circuit 57,
At the output terminal 58, a two-dimensional array output signal is obtained at a constant reference level. As described above, according to the present invention, by varying the DC level of the two-dimensional array,
It has the effect of correcting the drawback that the entire output signal obtained from the two-dimensional array fluctuates, and that it is possible to obtain an appropriate two-dimensional array output that does not include fluctuations corresponding to a certain reference level.
This is particularly effective when processing image signals.

All of the above describes the case where a bucket brigade element is used as the basic structure as a charge transfer element, but as mentioned above, it is clear that the present invention can be similarly applied to charge transfer elements with other structures. It is.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of the packet brigade element.
Figure 2 is a cross-sectional view of the basic structure when the circuit in Figure 1 is formed on the surface of a semiconductor substrate, and Figure 3 is a configuration diagram of a two-dimensional array in which a plurality of charge transfer elements are arranged, and the two-dimensional array output is FIG. 4 is a block diagram of a two-dimensional array in which a plurality of charge transfer elements are arranged, and shows a case where the output of the two-dimensional array is converted into a serial output and taken out. FIG. 5 is a waveform diagram of each part to explain that the amount of charge transferred to each element of the transfer stage of the charge transfer element constituting the two-dimensional array mentioned above is slightly different, where A is the input waveform VINsB, C shows the clock signals φ1 and φ2, D shows the BBD output for these waveforms, and FIG. 6 shows that the amount of charge transferred to each element of the charge transfer element determined from the output of FIG. 5D is slightly different. FIG. 7 is a configuration diagram of a two-dimensional array consisting of charge transfer elements according to an embodiment of the present invention, FIGS. 8A to 8D are waveform diagrams of various parts in FIG. 7 for explaining FIG. 7, and FIG. 9 7 is a specific circuit configuration diagram, and FIG. 10 is a configuration diagram of other embodiments of the present invention in which the output of a two-dimensional array is obtained by serial output. 41, 42, 47, 48, 59, 60...
...Input terminal, 45, 52, 58...
...Output terminal, A1-A8, Bl-B8,...H1-
H8, Al2 ~ A82, ... H12 ~ H82, Al3
~A83,..., Hl3~H83, Al4~A84,
..., H14 to H84... Charge transfer elements forming each column of the two-dimensional array. 44, 49, 55... Charge transfer element for parallel-serial conversion, Xl2 to X82, Xl4 to X84... Charge transfer element equivalent to a charge transfer element constituting a two-dimensional array, 50, 56...Charge transfer element equivalent to the charge transfer element for parallel-to-serial conversion, 44, 51, 57...
・Output comparison τ comparison correction circuit.

Claims (1)

[Claims] 1 A device having a plurality of charge storage capacitors and a plurality of charge transfer devices that operate to transfer charge from one capacitor to another under the control of a series of clock signals with different phases. to configure a two-dimensional array,
A charge transfer element for correcting the DC level of the output of the two-dimensional array having the same number of transfer stages as the charge transfer elements in each column of the two-dimensional array and capacitors having approximately the same capacitance is provided, and the charge transfer element for correcting the DC level of the output of the two-dimensional array is provided. Comparison and correction means for reading out the output of the charge transfer elements in each column of the two-dimensional array using the output DC level of the transfer element as a reference level is provided on the output side of the charge transfer element of the two-dimensional array, and the charge for the DC level correction is By applying an output reference voltage obtained by inputting a predetermined signal to the transfer element to the above means, an output is read out from each charge transfer element of the two-dimensional array with DC level fluctuations corrected due to transfer stage losses. A charge transfer device characterized by: