JPS6024951B2 - Electrochromic analog display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrochromic display (hereinafter referred to as EC).
Say D.

) relates to an analog display device. ECD
Regarding the two types of basic structures, characteristics of ECDs, basic drive circuits of ECDs, etc., the patent application filed by the applicant, including some of the inventors of the present invention, was filed in 1986-1193.
As explained in No. 96 and elsewhere.

Furthermore, the present invention relates to a drive circuit when an ECD is used as a segment-type analog display device, and in particular, detects a change in the amount of analog to be displayed, such as an increase or decrease, and colors or erases it depending on the detected output. It is characterized in that the displayed content of the ECD is changed by selecting the applied voltage polarity for the color.

The present invention will be described in detail below according to a specific example.

FIG. 1 is a diagram vaguely representing the display state of the segment type analog display device according to the present invention, with cross hatching indicating display areas and white areas indicating non-display areas. , b indicates 2.0, and c indicates 1.0.

The segment type analog display device shown in Figure 1 is
FIG. 2 shows a schematic configuration diagram of the ECD when it is realized by a CD.

In Fig. 2, 1 is a counter electrode, 2 is a reference electrode, So~
S4o is a display segment electrode. Note that the reference electrode 2
is unnecessary unless constant potential driving is performed. FIG. 3 shows a block diagram of a driving circuit for an ECD analog display device according to the present invention. In FIG. 3, each element indicated by a number is as follows. 3 is an analog quantity source and its detection/electrical conversion system.

4 is a V-F converter, 5 is a counter, 6 is a register that samples and stores the output of counter 5, and 7 is a register like register 6, but its contents are the same as the previous one stored in register 6. It's about the timing.

8 is a magnitude comparator which receives the outputs of resistors 6 and 7 as inputs.

Reference numeral 9 represents an output circuit, 10 represents an ECD, and 11 represents a segment switch unit for selecting a display segment in which the display mode changes, such as coloring or decoloring.

As already stated, the present invention is characterized in that the polarity of the applied voltage is changed according to changes in the analog quantity to be displayed,
Elements 6, 7, and 8 in FIG. 3 accomplish this. B in Figure 3.

An example of a circuit embodying a block diaphragm is shown in FIG.
Each element in Figure 4 is as follows.

Sig is the output from the V-F converter, the frequency of which is proportional to the analog quantity to be displayed. a is the differential waveform of the rising edge of Sig, and its number per second is the frequency of Sig. Ts is a gate pulse whose rising edge is the falling edge of the display update pulse Clock, and by adjusting its pulse width, a proportionality constant between the Sig frequency and the number of analog display segments is determined. b is the product of the differential waveform a and the gate pulse Ts, and the signal is the input pulse of the multistage binary counter 12 and the clock pulse of the shift register 6. 13 and 14 are registers that store counter outputs, and register 14 stores the output of register 3 one step before. 15 is a magnitude comparator that determines whether the change in the analog quantity is an increase or a decrease.

If the value stored in register 14 one step before is larger than the value stored in register 13, comparator 1
If the output a of 5 becomes Hi, and vice versa, the output y
becomes High.

If the values stored in registers 3 and 14 are equal, both outputs Q and y are mountains w. As already mentioned, 16 is a shift register, the data input D of which is connected to the power supply +V and kept at a high logic level.

The power source -V is a power source corresponding to the peak w level. Therefore, the high level is shifted every time the clock pulse b of the shift register 16 becomes high. Then, after the reset signal Clock of the shift register 16 is input, for example, if the signal b becomes 4 pulses High, outputs Q and Q of the parallel outputs of the register 6 become High.
h'Konaru. Reference numerals 17 and 18 are D-flip-flops, and the flip-flop 18 stores the output Q4 of one step before, and detects changes in the output Q by exclusive OR.

The display state change detection circuit consisting of these two flip-flops 17 and 18 and exclusive OR is provided at all parallel output terminals of the shift register 6.
In FIG. 4, only the output Q4 is depicted for simplicity. This change detection circuit makes use of the memory function that is a feature of the ECD, and allows current to flow through the display segment only when there is a change in the display state of the display segment.
The output e4 of the exclusive OR is the output Q immediately before reset.
The axis becomes Hi axis only when there is a change in the state of . The above-mentioned output Clock is a display update pulse, which takes the output data of the binary counter 12 and shift register 16 into the register 3 and flip-flop 17, and uses those data as data from the previous step stored in the register 14 and flip-flop 18. - comparison is performed using the comparator 15 and exclusive OR. That is, Clo
ck is a clock pulse for the registers 13, 14, 17, and 18, and is also a reset pulse for the binary counter 12 and shift register 16. However, 19.2 is a buffer inserted to shift the timing to prevent data loss. It goes without saying that the number of parallel outputs of the shift register 16 is the same as the number of analog display segments. FIG. 5 is a time chart of various signals in FIG. 4.

Next, the operation of the circuit shown in FIG. 4 will be explained.

The circuit of FIG. 4 has two main purposes; one is to obtain a segment display state control signal for analog display by coloring a number of display segments proportional to the frequency of signal Sig; One of these is to generate a signal that is synchronized with the aforementioned control signal and distinguishes whether the updated display amount is increased or decreased.

A number of pulses proportional to the frequency of the signal Sig appears as the output b within one period of the signal clock.

The output b is divided into two parts; one is used to make the parallel output of the shift register 16 high by the number of pulses of the output b, and the other is used to tell the number of pulses by the ripple counter 12. The parallel outputs of shift register I6 correspond to the coloring and decoloring of analog display segments. Changes in the number of pulses are detected by the comparator 15, and changes in the segment display state appear as the output of the exclusive OR. For example, consider a case where the number of pulses of output b increases from 1 to 6.

In this case, the output Q of the comparator 15 becomes High', producing a segment colored signal. Which of the many segments is to be colored or not can be determined by the output of the exclusive OR corresponding to each display segment becoming High. That is, in this case, output Q4 becomes High when the number of pulses of output b is 4 or more, and therefore output e4
will be High. Further, when the number of pulses of the output b decreases from 4 to 1, the output y goes high, and a signal for segment color erasure is outputted to reduce the number of colored display segments.

In this case, the output e4 becomes High, and the segment corresponding to the output e4 is selected as the decoloring segment. The signals Q, q, and e4 shown in FIG. 5 are led to, for example, a constant potential drive circuit shown in FIG. 6.

In FIG. 6, the analog switches 19 and 2 are controlled by the outputs Q and Q, respectively, and are suitable when the control signal becomes a Hi node. 21 is an OP amplifier.

22 is an analog switch.

A segment selection switch for display segment S4 controlled by output e4. Of course, other display segments would also be provided with such segment selection switches, but they are not depicted for simplicity. FIG. 7 is a timing diagram of each signal in the circuit of FIG.

In Fig. 6, for example, if the signal Q becomes High', a voltage suitable for coloring appears at the terminal f, and at this time the output e4
When the analog value becomes High, the display segment S4 is colored, and it can be visually observed that the analog amount has increased.

Further, when the signal y becomes High, a negative voltage suitable for erasing appears at the terminal f, and the segment for which the control signal of the segment selection switch becomes High at this time is erased.

FIG. 8 shows an example in which constant voltage drive is used in the drive circuit of the present invention. It should be added that the inputs of the flip-flops 17 and 18, which are the same as the number of display segments, can be used as the 15 inputs.

As described above, the present invention provides segment type EC
D Ana.

The present invention provides a digital analog display device that includes a circuit that detects changes in the analog quantity to be displayed, and emits a colored signal when the displayed quantity increases, and a decoloring signal when it decreases. Furthermore, which segment among the large number of segments is to be colored or decolored is made conductive only when there is a change in the display state of a segment selection switch provided in each segment. In addition to the drive circuit of the present invention, the polarity of the applied voltage is automatically switched at certain fixed time intervals, and a segment selection switch connected in series to the segment to be colored or decolored is turned on in synchronization with the polarity. It is also conceivable to color or decolor appropriate display segments.

This method is effective, for example, in the case of a seven-segment type numeric display device shown in FIG. This is because when the display pattern changes from one display state to another display number, in many cases there is a dual process of coloring and erasing, in which newly necessary segments are colored and unnecessary segments are erased. This is because two processes are required. However, when the display pattern of a segment-type analog display device as shown in Figure 1 changes, the display segments are either colored or decolored, and both coloring and decoloring are required at the same time. It will never be.

Therefore, according to the present invention, if the applied voltage is given a polarity to color when the analog amount to be displayed increases, and a polarity to be decolored when it decreases, the display pattern can be changed. It becomes possible to shorten the time required to complete the change, and it is possible to compensate for the long response time of the ECD. i.e., coloring of display segments;
If it takes 0.9 hours to erase each color, then according to the present invention, the time required for changing the display pattern may be 0.9 hours.
A method that automatically switches the applied voltage polarity at fixed time intervals may take one second. The segment type ECD analog display device of the present invention is generally effective and can be used to display the degree of a current value relative to a certain optimum value, which cannot be obtained with a digital numerical display, such as a thermometer, blood pressure monitor, tachometer, weight scale, speedometer, etc. It can be used for display devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic display diagram of a segment type ECD analog display device, FIG. 2 is a schematic diagram of the foundation, FIG. 3 is a block diagram of a drive circuit of an ECD analog display device according to an embodiment of the present invention, and FIG. 4 5 is a drive circuit diagram, FIG. 5 is a time chart of signals of each part of the circuit in FIG. 4, and FIG.
The figure is a circuit diagram of another embodiment of the present invention, which is driven at a constant potential. Figure 7 is a time chart of the circuit shown in Figure 6. Figure 8 is another embodiment of the present invention, which is driven at a constant voltage. The circuit diagram, FIG. 9, is a segment pattern diagram of a 7-segment numeric display device. 3 is an analog quantity source and its detection electric conversion system, 4 is V-F
Converter, 5 is a counter, 6, 7 is a register, 8 is a magnitude comparator, 9 is an output circuit, 10 is an ECD, 12 is a binary force counter, 13, 14 is a register, 15 is a magnitude counter, 16 is a shift register, 17,
18 is a D-flip-flop, and 19 and 20 are analog switches. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. In an electrochromic analog display device in which a plurality of display segment electrodes are arranged in a line and one end of the arrangement is colored or decolored to display an analog quantity of a signal, an increase in the analog quantity to be displayed or means for detecting a change in the decrease; and means for selectively selecting the applied voltage polarity for coloring or decoloring the display segment electrode in which the analog quantity changes, based on the output signal of the detection means. 1. An electrochromic analog display device comprising a drive circuit including: