JPS6032207B2 - Branch control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a branch control circuit built into, for example, a microcomputer.

Conventionally, in order to perform a branch control operation in a branch control circuit built into a microcomputer, it is necessary to insert a branch instruction into a program for each branch operation.

For example, although the basic processing on the program is the same,
If it is necessary to change some data for processing depending on the target operation, a branch instruction is required to send each piece of data to a common routine. In addition, if there are several common routines in a program and the processing content differs depending on the purpose operation among the common routines, it is necessary to program the branch condition codes for these different processes one by one, and the branch condition code It was necessary to insert a branch instruction for each setting. Therefore, the conventional branch control circuit has the disadvantage that the number of program words (number of steps) increases. The present invention has been made to solve the above-mentioned drawbacks, and by sequentially programming predetermined instructions, necessary data or branch condition codes are automatically generated and the processor processes the target processing routine. By also providing a means to transfer the
It is an object of the present invention to provide a branch control circuit that eliminates the branch instruction for each data and branch condition code, and can significantly reduce the number of words (number of steps) of a program.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a branch control circuit of the present invention, 11a,
11b is a command input terminal, and the input state 11a is N, which will be described later.
An NSET command is applied to set data in the register, and a DINC command is applied to the input terminal 11b to increment the data. 12 is a gate control circuit, and this gate control circuit 12 includes an AND circuit 13 for ANDing the NSET command and the second basic synchronization code 2;
Second basic synchronization signal? 2 and the NSET instruction inverted by the inverter 14, and a flip-flop 1 which is set by the output of the AND circuit 13 and set by the output of the AND circuit 15.
6, and when the NSET command is transmitted, the flip-flop 16 is activated at the rising edge of the second basic synchronization signal 2.
A set output is sent from.

17 is a counter control circuit;
Is the PINC command and the first basic synchronization signal? , and an AND circuit 20 that takes an AND between the first basic synchronization signal and the DINC command inverted by the inverter 19. Send count data,
A signal for clearing the counter 21 is sent from the AND circuit 20.

Reference numeral 21 denotes a counter, and the contents of this counter 21 are incremented at the time of the preceding INC command, and cleared at times other than the DINC command.

22 is a selector which selects the output data from the counter 21 at the time of the PINC command and outputs the data from the DI
When the command is not an NC command, data on the data bus 23 is selected.

Also, 24 is a gate circuit for creating a latch pulse,
This gate circuit 24 includes an AND circuit 25 which takes the NSET command, the output of the flip-flop 16, and the first basic synchronization signal ?, and the DINC command and the second basic synchronization signal? It consists of an AND circuit 26 which takes an AND of 2, and an OR circuit 27 which takes an OR of the outputs of both the AND circuits 25 and 26. Furthermore, 28 is an N register, and this register 28 stores output data from the selector 22 in response to a latch pulse from the gate circuit 24.
That is, after executing an instruction other than the NSET instruction, data is latched onto the data bus 23 selected by the selector 22 only at the time of the first NSET instruction, and the contents of the counter 21 selected by the selector 22 are latched at the time of the DINC instruction. Ru. Note that when these NSET commands are executed consecutively, the data latched by the first NSET command is stored in the N register 28.
is stored in Further, 29 is a branch condition determination circuit for determining the branch condition code contained in the N register 28 and instructing a predetermined processing destination. Here, the codes of the NSET instruction and the DINC instruction are each composed of an operation code and an n-bit operand for the NSET instruction, and only an operation code for the DmC instruction.

The relationship between each instruction and the synchronization signal is as shown in FIG. , and the second basic synchronization signal? 2 is generated, and the first basic synchronization signal ◇ precedes the second basic synchronization signal F2 in terms of timing. Next, the special feature of this branch control circuit will be explained along with a specific program.

In Figure 3, the basic processing on the program is the same, but
This figure shows a flowchart of a program when it is necessary to change some data for processing depending on the purpose. In this program, the common routine is automatically entered by sequentially programming several pieces of data, so there is no need to insert a branch instruction to go to the common routine for each piece of data. That is, the value latched in the N register 28 in FIG. 1 is used as data for the above processing. To obtain such data, the NSET command described above is executed in steps S, ,S, etc.
2 and S3 are sequentially programmed, and the target processing is performed in a common routine starting from step S4 based on the data obtained in these steps S, , S2, and S3. Note that a, b, and c in the figure are jump destination indicators for executing processing of a common routine based on target data from other processing routines used for branch instructions of the main program. For example, when the processing of the microcomputer processor moves from another routine of the main program to the jump destination index C, the NSET command is applied to the input terminal 11a in FIG. The first basic synchronization signal by this NSET command? A “1” level signal is output from the AND circuit 25 at the timing of “1”.
” level signal is sent to the N register 28 via the OR circuit 27.
is transmitted as a latch pulse. This latch pulse causes the data ratio on the data bus 23 to change to the selector 22.
is latched into register 28 through. Therefore, this data n3 is transmitted to data bus 23 through bus A. At this time, the processing of the processor has entered step S4, so after reading the data transmitted on the data bus 23, the processing of the common routine is executed. Similarly, when the program processing of the processor moves to the jump destination index a, data n is latched into the N register 28 in step S by the NSET command. Step S2,
The NSET command in step S3 is outputted from the AND circuit 16 at the "0" level, and the flip-flop 16 is not reset (that is, as long as the NSET command is continuously input, the flip-flop 16 is not reset). Since the latch pulse is not output, the N register 28 is first set to NSET at step S.
The data n latched by the instruction is held. Then, when the processing of the processor proceeds to the next step S4,
Here, a common routine is executed based on data n, as described above. When the program processing of the processor moves to the destination index b, the N register 28 holds the data ratio as described above, and the common routine is executed based on this data n2. In the program shown in Fig. 3 above, in the conventional case, a branch instruction was required to unconditionally jump to the common routine between steps S, S2, respectively.
By using this circuit, it is possible to eliminate the branch instruction for every 2 pieces of data, and as the amount of data to be processed increases, the number of words in the program can be significantly reduced compared to the conventional method.

Figure 4 shows that there are several common routines in the program.
This figure shows a flowchart of a program when processing contents differ depending on the purpose among the common routine tools.

This program automatically generates branch condition codes by continuously inputting predetermined instruction codes, eliminating the need to program branch condition codes for different processes one by one. It is no longer necessary to insert a branch instruction for each DmC instruction). That is, the value latched in the N register 28 of FIG. 1 is used as a branch condition code for the different processing. In order to obtain such a branch condition code, for example, when there are three different processes, the above-mentioned DINC instructions are programmed consecutively as steps S, , S2, and S3. Different processes (processes A, B, C, and D) are executed according to the judgment conditions judged by the judgment circuit 29 based on the branch condition codes obtained in S2 and S3. In addition, a, b, c, in the program
d is a jump destination index from the main program as described above. When the processing of the processor shifts to the jump destination index d, the DINC instruction does not arrive at the input terminal 11b in FIG. At the timing of sync signal low 2 “
0” is latched.The value of this N register 28 is “0”.
In this case, the determination circuit 29 instructs the processor to re-execute the process D of the common routine and the other processes. When the processing of the processor moves to the jump destination designation c, a DINC instruction is executed in step S3. That is, since the DINC command is applied to the input terminal 11b in FIG. 1, the first main synchronization signal ? The counter data is output at the timing of ,
The counter 21 counts this and sets the content to "1". The content “1” of this counter 21 is selected by the selector 22 and stored in the N register 28. In step S5, the content of this register 28 is judged by the judgment circuit 29. For example, if it is "1", processing C is designated, so the microprocessor executes processing D of the common routine and then goes to step S8. The process moves to process C. Similarly, when the processing of the processor shifts to the jump destination index b, the content of the counter 21 becomes "2" due to the two DINC instructions in steps S2 and S3, and this counter 21
In response to the content "2", the processor process shifts from process D of the common routine to process B of step S6. Similarly, when the processor processing moves to the jump destination index a, step S
,, S2, S3 three times, the content of the counter 21 becomes "3", and the NO register 28 contains "3".
” is latched, and in response to the content “3”, the processor executes the process A of step S7 from process D of the common routine. Furthermore, after executing these processes A, B, C, and D, the processor Execute the common routine in step S9 and return to the metain program.In the program shown in FIG. In addition, since the present invention eliminates the need for a branch instruction to a common routine, the number of words in a program can be significantly reduced.

As explained above, according to the present invention, there is a means for automatically generating different data necessary for a common routine by sequentially programming a predetermined command, and a means for automatically generating different data necessary for a common routine, and a means for executing different processing between different common routines. By providing a means for automatically generating branch condition codes by sequentially programming predetermined instructions, data or branch conditions that are automatically generated starting from any point in a continuous program can be automatically generated. Since the processor processing can be automatically transferred to a common routine or to a different processing according to the code, there is no need to insert a branch instruction for each data item or each setting of a branch condition code.

It is possible to provide a branch control circuit that can significantly reduce the number of words (number of steps) of a program and improve the efficiency of the processor.

[Brief explanation of the drawing]

FIG. 1 is a branch control circuit diagram according to an embodiment of the present invention, and FIG.
This figure is a time chart showing the relationship between commands and synchronization signals in the circuit of FIG. 1, and FIGS. 3 and 4 are flowcharts of specific programs of this circuit, respectively. 11a, 11b...Input terminal, 12...Gate control circuit, 16...Flip-flop, 1
7... Counter control circuit, 21... Counter, 22... ...Select item, 23...Data bus, 24...Gate circuit, 28...
・N register, 29...Branch control circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a branch control circuit built into a microcomputer that branches program processing to a predetermined processing routine based on a branch instruction, different data necessary for a common routine is programmed in succession with a predetermined first instruction. and means for automatically generating a branch condition code for executing different processes between different common routines by sequentially programming a predetermined second instruction, Starting from an arbitrary instruction location in the continuous program, the processing of the microprocessor is automatically branched to a common routine or a different processing according to the data or branch condition code generated by the generating means, and A branch control circuit characterized in that it is not necessary to insert a branch instruction into a program for each data or each branch condition code setting.