JPS6042628B2 - Input/output protection circuit for MOS integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit for input/output terminals of a MOS integrated circuit.

In a conventional input/output protection circuit for a MOS integrated circuit, a P-type diffused resistor 2 is connected to a terminal 1, as shown in FIG.

Due to the structure of the diffused resistor 2, a Zener diode 21 is inevitably connected to the drain side. Diffusion resistance 2
A Zener diode 3 having one end connected to the drain side and a Zener diode 4 having one end connected to the source side are connected to.

The terminal 5 is connected to an internal gate (not shown) of a FET transistor or the like in the MOS integrated circuit.
When a voltage higher than the drain side is applied to terminal 1 with power connected to the drain side and the source side, two Zener diodes 21 are connected from terminal 1 to the drain side.
Charge flows in the forward direction of Zener diode 4, and if a voltage lower than the source side is applied to terminal 1, charge flows in the forward direction of Zener diode 4 from the source side to terminal 1, so in either case, the FET No charge flows through the gate of the transistor, and the gate is protected.

However, when the drain side or the source side is open, the gate of the FET transistor and the PN junction of the Zener diode 21 are destroyed under the following conditions.

When the drain side is positively charged and a negative voltage is applied to terminal 1, and the source side is open, the two Zener diodes 21 and 30 are in opposite directions,
Charge will flow from the drain side to terminal 1.

At that time, since the breakdown of Zener diodes 21 and 3 is used, the rise of the Zener diodes 21 and 3 is delayed, and there is a risk that charge may flow at the gate of the FET transistor, increasing the possibility of gate breakdown and reducing the amount of charge applied to terminal 1. When it is large, the PN junction of the Zener diode 21 is destroyed.

In addition, if the source side is negatively charged and a positive voltage is applied to terminal 1, and the drain side is open, it will be transferred from terminal 1 to the source side in the opposite direction of Zener diode 4 through diffused resistor 2. This causes a charge to flow,
It is possible that the gate of the FET transistor or the Zener diode 4 may be destroyed. In fact, MOS destruction often occurs between the time it is manufactured, when the drain and source sides are open, and the time it is mounted, and conventional protection circuits cannot completely prevent such destruction.

The object of the present invention is to obtain an input/output protection circuit that prevents damage even in an open state.

The present invention will be explained based on the drawings. In FIG. 2, P-type diffused resistors 7 and 8 are connected in series to the terminal 6. Due to the structure of the diffused resistors 7 and 8, Zener diodes 71 and 81 are inevitably connected to the drain side.

Note that the breakdown voltage of the Zener diode 71 is made high, and the breakdown voltage of the Zener diode 81 is made low.

In addition, as for the diffused resistor 7, it is better to use a Pwell that is used on an N-channel substrate in C-MOS, since abnormal alloying between the electrode and the substrate may occur, causing spikes in the electrode and causing the diffused resistor 7 to be destroyed. It disappears. The diffused resistor 8 includes a Zener diode 9 whose one end is connected to the drain side.
and one end is connected to the source side. Zener diode 1
0 is connected.

The Zener diodes 9 and 10 have a low voltage and a small forward voltage drop. A gate (not shown) of a FET transistor or the like in a MOS integrated circuit is connected to the terminal 11.

Next, we will explain how the gate of the FET transistor and the PN junction of the Zener diode are protected when the drain side or the source side is in an open state. In FIG. 2, it is assumed that when the drain side becomes positively charged and a negative voltage is applied to the terminal 6, the source side becomes open.

The peak voltage applied to the drain side and terminal 6 is divided by the diffusion resistor 7 and applied in the opposite direction to both ends of the Zener diode 71, but since the breakdown voltage is high, almost no current flows in the reverse direction. , the junction is not destroyed.

Further, a diffused resistor 7,
When a voltage divided along with 8 is applied in the opposite direction, a current in the opposite direction flows relatively easily because the breakdown voltage is low.

If too much current flows, the PN junction of the Zener diode 81 will be destroyed, so the diffusion resistor 7 suppresses the current value to a small value.

Similarly, reverse current flows relatively easily in the Zener diode 9, which also has a low breakdown voltage.

Since the current is suppressed by the diffused resistors 7 and 8, it does not destroy the PN junction of the Zener diode 9. Therefore, no charge flows through the gate of the FET transistor connected to the terminal 11, and the gate is protected. Next, when the drain side is negatively charged and a positive voltage is applied to the terminal 6, and the source side is open, the voltage from the terminal 6 to the drain side is mainly due to the forward direction of the Zener diodes 71 and 81. Since charge flows quickly toward the terminal 11, the gate of the FET transistor connected to the terminal 11 is protected.

Furthermore, when the source side is negatively charged and a positive voltage is applied to the terminal 6, and the drain side is open, the positive charge on the terminal 6 passes through the diffusion resistors 7 and 8 and is connected to the Zener diode 10. It flows in the opposite direction and reaches the source side.

The breakdown voltage of the Zener diode 10 is low, and a reverse current flows relatively easily, so that no charge flows through the gate of the FET transistor connected to the terminal 11, and the gate is protected.

The magnitude of this reverse current is suppressed by the diffused resistors 7 and 8 to such an extent that the PN junction of the Zener diode 10 is not destroyed.

Also, since the drain side is open, terminal 6
The positive charges do not flow using the forward direction of the Zener diodes 71, 81, and 9.

It goes without saying that the internal gate is protected against various conditions even when the drain and source sides are connected to the power supply. Furthermore, if this protection circuit is used on the output side, the output side will be protected. Furthermore, even if the diffused resistors 7 and 8 are both N-type, or P-type and N-type, respectively,
A similar operation is performed even in the opposite case.

As explained above, this invention has a simple structure, and MO
Even the most frequent failures that occur before S is implemented can be completely prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of an input/output protection circuit of a conventional MOS integrated circuit, and FIG. 2 is a diagram of an input/output protection circuit of the present invention. 2... Diffused resistance, 21, 3, 4... Zener diode, 7, 8... Diffused resistance, 71
,81,9,10... Zener diode, 1
1...Resistance.

Claims (1)

[Claims] 1 A first diffused resistor and a second diffused resistor are connected in series, and the open terminals of the first and second diffused resistors are connected, respectively.
The signal input/output terminal is used as the gate terminal of the FET in the MOS integrated circuit, and two first and second Zener diodes with low breakdown voltage and small forward voltage drop are connected in the same direction across this gate terminal. A power supply is connected in parallel to the open ends of the first and second Zener diodes, and the breakdown voltage generated by connecting the first and second Zener diodes to the first and second diffused resistors, respectively. This is an input/output protection circuit for a MOS integrated circuit, in which the open ends of a third Zener diode with a high breakdown voltage and a fourth Zener diode with a low breakdown voltage are connected to one end of a power supply.