JPS6048685B2 - Displacement detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a displacement detection circuit that detects displacement as a change in the phase of an electrical signal.

FIG. 1 shows a conventional position displacement detection circuit.

In the figure, an oscillator 1 generates a reference signal having a frequency n times the carrier frequency fc, and the reference signal is applied to a downshifter 3 and a dividing circuit 15. The downgrader 2 sets the frequency of the reference signal and supplies it to the magnetic head 7 of channel 1 via a phase shifter 3 and an amplifier 4, and also supplies the frequency of the reference signal to the magnetic head 8 of channel 2 via an amplifier 5. The magnet is excited by supplying it through the magnet.

A balanced modulation signal obtained by the relative displacement between the magnetic scale 6 and both heads 7 and 8 is added by an adder 11 via preamplifiers 9 and 10 to produce a phase modulation signal having a phase change corresponding to the displacement. After being converted into a signal, it is applied to a dividing circuit 15 via a bandpass filter 12, an amplifier 13, and a waveform shaping circuit 14.

The dividing circuit 15 is a so-called interpolation circuit such as that described in Japanese Patent Publication No. 50-28032, and generates a positive direction movement pulse P+ and a negative direction movement pulse P- whose directions are discriminated according to the displacement position. do. However, according to the conventional method described above, when trying to obtain high resolution accuracy, one wavelength of the phase modulation signal corresponds to the scale recording wavelength (pitch), so it is necessary to divide (interpolate) The frequency of clock pulses must be increased for this purpose. Further, there is a restriction that lowering the frequency of the phase modulation signal causes a decrease in response speed 5. Therefore, conventional systems usually use 10KH2 and 50KH2 phase modulation signals depending on the resolution. Therefore, as the bandpass filter 12 for removing unnecessary components of the output signals of the magnetic heads 7 and 8, filters corresponding to the frequencies of 10 Hz and 50 KHz of the phase modulation signal are required, which inevitably requires the use of coils and capacitors. Therefore, the filter ιj is large and expensive, which is extremely disadvantageous in terms of cost and space. In view of such circumstances, the present invention is characterized in that the input frequency of the bandpass filter is set to -Fc, and the n-filter passing signal and the m-phase clock signal are applied to an m-stage phase comparator. .

The present invention will be described below with reference to embodiments shown in the drawings.
The difference in the embodiment shown in FIG. 2 from that shown in FIG. ) is used, and an adder 11 and a bandpass filter 19
A balanced modulator 18 is inserted between the waveform shaping circuit 14 and the dividing circuit 22, and an m-stage phase comparator 21 is inserted between the waveform shaping circuit 14 and the dividing circuit 22.

That is, the phase modulation signal E,=Esin2π from the adder 11
(2πFct+-x) is the frequency λ-F from the downgrader 16
The m balanced modulated wave signal E is applied to the balanced modulator 18 together with the signal of c.

=ke(COs2π((bud-1)Fct-i)-COS2
It is converted to π((Jin+1)Fct+r)). λ is the pitch of the scale, and X is the displacement position. Next, as the bandpass filter 19, a filter whose passband is the lower side band (--1) Fc or upper side band (-+Mml) Fc of the balanced modulated wave signal is used, and when the balanced modulated 2π harmonic signal is passed, The phase change − is preserved and only the carrier frequency ((−−1
) or (-+1) Mm times the phase modulation signal.

This signal is further applied to an m-stage phase comparator 21 via an amplifier 13 and a waveform shaping circuit 14. This phase comparator 2
1 consists of, for example, m D flip-flops, and the phase modulation signal from the waveform shaping circuit 14 is simultaneously applied to the D terminals D1 to Dm of each flip-flop, and the phase modulation signal from the waveform shaping circuit 14 is applied to each of the clock terminals CKI to CKm, respectively. phase clock generator 20
Clock signals φ, .about.φm are applied. The phase comparator 21 detects one of the sideband waves of the balanced modulated wave, that is, the phase modulated signal 2πn, which is obtained by multiplying only the carrier frequency by (lightning - 1) or (lightning + 1), and m, which have a phase difference of -, respectively.
The phase of the phase -Fc is compared with a clock signal having a frequency of Mm wave number.

As a result, pulsed phase modulation signals S, .about.Sm of frequency Fc are generated as if heat were being generated for each frequency difference Fc. In this case, the phases of the clock 2π lock signals φ, ~φm differ by − M2π, so the phase of the sideband wave and the clock signal match at positions where the phase differs by − m from the heat frequency Fc. Therefore, the phases of the m-phase pulsed 2π phase modulation signals are each shifted by m· in phase.

The phase modulated signals S, ~Sm are respectively given to a dividing circuit 22 together with the respective clock signals, and the circuit generates a positive direction movement pulse P+ and a negative direction movement pulse P- whose directions are discriminated according to the displacement position. . FIG. 3 shows a configuration example of a four-phase clock generator as an example of the m-phase clock generator 20 in the embodiment of FIG. 2, and FIG. 4 is a time chart for explaining its operation.

In the figure, 23 to 26 are D flip-flops, and 27 is a NOR gate. A clock signal with a frequency Nfc from the oscillator 1 is applied to the clock terminal ℃K of each D flip-flop, and a four-phase clock signal φ with a 90° phase shift is applied to the clock terminal ℃K of each D flip-flop.
1 to φ4 are generated. FIGS. 5 and 6 show a dividing circuit (1140 interpolation, resolution 5 μm) constructed particularly suitable for the present invention and its time chart.

This divided circuit consists of four identically configured circuits 2 corresponding to each phase.
8 to 31, and one circuit 28 includes, for example, D flip-flops 32, 33, and a 4-bit shift register 34.
, Noah Gate 35, 36, And Gate 37, 38, 3
9, and the output U from each circuit 28 to 31
,~U. , D, ~D. is given to the or gates 40 and 41. Now, the carrier frequency Fc is 50KHz)φ, ~φ
If the clock frequency of , is 500 KHz, the number of dividing clock pulses φ1 included in one period of the phase modulation signal S, is 10 pulses.

By the way, the D flip-flop 32 and the NOR gate 35 cause the clock pulse φ, . φ, is subtracted by one period. Next D
A load pulse for the shift register 34 is generated by the flip-flop 33 and the NOR gate 36 during one period following the clock pulse φ1, and in synchronization with φ1, the terminals QA--QD of the shift register 34 are loaded with 0) 0, 1, o. pattern is loaded. Thereafter, the shift register 34 starts shifting from the next clock pulse φ1, and the shift register 34 starts shifting from the next clock pulse φ1, and
, when the number of pulses of , is larger than the steady state, the next phase modulation signal S,
In synchronization with the fall of , the AND gate 37 is opened, and the - addition side OR gate 40 generates a positive direction movement pulse P0.

Similarly, when the number of clock pulses φ, is smaller than the steady state,
The AND gate 38 is opened at the next fall of the phase modulation signal S, and the negative direction moving pulse P is opened from the OR gate 41 on the subtraction side.
− is generated. The operation of circuits 29-31 is also exactly the same as described above. In addition, although m = 4 here, the circuit 28
, 30 or 29, 31 in two-phase form, it is also possible to achieve a resolution of, for example, 10 .mu.m, or even 20 .mu.m by using only one circuit. As is clear from the above explanation, according to the present invention, the following excellent effects can be obtained. (1) m by m-stage phase comparator
Since the phase is compared with a clock pulse whose phase is shifted by 2π/m of the phase, the change in phase per pulse when dividing into n is sequentially multiplied by m for each phase and detected. The operating speed of the dividing circuit can be reduced to 1.

Furthermore, the configuration of the dividing circuit can be extremely simplified, and since the operating frequency is low, it can be easily integrated into an LSI. (2) By appropriately selecting the phase number m and carrier frequency Fc, it can be extremely advantageous when selecting a bandpass filter.

As an example, when the resolution is 5 μm, the recording wavelength (pitch) λ of the magnetic scale is 0.2 Tfr, so the number of divisions n is 40. Therefore, if m = 4 and the carrier frequency Fc is 50KHz, the lower sideband of the balanced phase modulation wave is (40KHz).
14-1) Fc=arc, maybe 450KHz. This is equivalent to the intermediate frequency of the AM radio band, and by making the carrier frequency Fc slightly higher (for example, 50.55KH
With z), a commercially available inexpensive and small ceramic filter for radio can be used as it is as the bandpass filter.
(3) When generating a phase modulation signal of carrier frequency Fc, by appropriately selecting the number of phases m for the number of divisions n, it is possible to change the resolution while keeping the frequency of the bandpass filter constant.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional position displacement detection circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a four-phase clock generation circuit used in the embodiment. A block diagram showing an example, FIG. 4 is a time chart for explaining its operation, FIG. 5 is a block diagram showing an example of the configuration of the dividing circuit used in the above embodiment, and FIG. 6 is an explanation of its operation. There is a time chart for 1: Oscillator, 6: Magnetic scale, 7, 8: Magnetic head,
11: adder, 18: balanced modulator, 19: bandpass filter, 20: m-phase clock generator, -21: m-stage phase comparator, 22: dividing circuit.

Claims (1)

[Claims] 1. A circuit that generates a phase modulation signal of frequency f_c having a phase corresponding to the amount of displacement, and balanced modulation to which the phase modulation signal from the circuit and a clock signal of frequency (n/m) f_c are provided. frequency (n/m-1
)f_c or (n/m+1)f_c balanced modulation signal passes through a bandpass filter, an m-stage phase comparator to which the signal passing through the filter and m-phase clock pulses are applied, and a frequency output from the phase comparator. A characteristic displacement amount detection circuit comprising an m-phase phase modulation signal of f_c and a dividing circuit that generates a positive or negative direction movement pulse from the m-phase clock pulse. 2. The dividing circuit includes at least a shift register, a predetermined bit pattern is set in the shift register in advance, and a predetermined pulse is generated by a change in the bit pattern in accordance with a change in the phase of the m-phase phase modulation signal. 2. The displacement detection circuit according to claim 1, wherein the displacement detection circuit is configured to output pulses discriminated between positive and negative directions within an output period.