JPS6133366B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a displacement amount detection circuit for detecting displacement as a change in an electric signal in a magnetic scale device or the like.

FIG. 1 shows a conventional displacement detection circuit. In the figure, an oscillator 1 generates a reference signal having a frequency n times the carrier frequency _c , and this reference signal is applied to a downshifter 2 and a dividing circuit 15. The downshifter 2 sets the frequency of the reference signal to 1/2n and supplies it to the magnetic head 7 of channel 1 via a π/4 phase shifter 3 and an amplifier 4, and the magnetic head 8 of channel 2 is supplied with an amplifier. It is excited by supplying it through 5.

The balanced modulation signal obtained by the relative displacement between the magnetic scale 6 and both heads 7.8 is transmitted to the preamplifiers 9, 1.
0 and is added by an adder 11 and converted into a phase modulation signal having a phase change corresponding to the displacement, and then applied to a dividing circuit 15 via a bandpass filter 12, an amplifier 13, and a waveform shaping circuit 14. It will be done. The dividing circuit 15 is a so-called interpolation circuit as described in Japanese Patent Publication No. 50-28032, for example.
A positive direction movement pulse P+ and a negative direction movement pulse P- are generated whose directions are discriminated according to the displacement amount.

However, according to the conventional method described above, when trying to obtain high resolution accuracy, one wavelength of the phase modulation signal corresponds to the scale recording wavelength (pitch), so it is necessary to use the The frequency of the clock pulse must be increased. Further, there are restrictions such as lowering the frequency of the phase modulation signal, such as lowering the response speed. Therefore, conventional systems typically use phase modulation signals of 10 KHz and 50 KHz, depending on the resolution. Therefore, as a band filter 12 for removing unnecessary components of the output signals of the magnetic heads 7 and 8, the frequency of the phase modulation signal is 10K.
Hz and 50KHz respectively, so it is necessary to use a passive filter using a coil and a capacitor, which is large and expensive, and is extremely disadvantageous in terms of cost and space. It was hot.

Therefore, as proposed in Japanese Patent Application No. 52-95552, for example, the input frequency of the bandpass filter should be set to m/n _c , and the signal passing through the filter and the m-phase clock signal should be applied to an m-stage phase comparator. There is something I did.

FIG. 2 shows a circuit based on the above proposal, which differs from the one in FIG. In addition, a balanced modulator 18 is inserted between the adder 11 and the band filter 19, and an m-stage phase comparator 21 is inserted between the waveform shaping circuit 14 and the dividing circuit 22.

That is, the phase modulation signal e ₁ from the adder 11 = Esin
(2π _c t + 2π/λx) is given to the balanced modulator 18 together with the signal of frequency n/m _c from the down converter 16, and the balanced modulated wave signal e ₂ =E/2{cos2π((n/m-1 ) _c t-x/λ)-cos2π((n/m+1) _c t+x/
λ)}. However, λ represents the pitch of the scale, and x represents the amount of displacement.

Next, as the bandpass filter 19, a filter whose pass band is the lower side band (n/m-1) _c or the upper side band (n/m+1) _c of the balanced modulated wave signal is used, and the balanced modulated wave signal is passed. , the phase change 2π/λx is preserved and only the carrier frequency is (n/m-1)
Alternatively, a phase modulation signal multiplied by (n/m+1) can be obtained. This signal is further applied to an m-stage phase comparator 21 via an amplifier 13 and a waveform shaping circuit 14. This phase comparator 21 is composed of, for example, m D flip-flops, and the phase modulation signal from the waveform shaping circuit 14 is simultaneously applied to the D terminals D ₁ -D _n of each flip-flop, and the phase modulation signal from the waveform shaping circuit 14 is applied simultaneously to each of the D terminals D ₁ -D n of each flip-flop.
Each clock signal φ ₁ to φ _n from an m-phase clock generator 20 is applied to CK _n . The phase comparator 21 is connected to one of the sideband waves of the balanced modulation wave and two
By comparing the phase of the clock signal of the frequency n/ _mc of the m phase with a phase difference of π/m,
Frequency _c of m phase with phase shift of approximately 2π/m
pulsed phase modulation signals S ₁ to _{S n} are generated. The phase modulation signals S ₁ to _{S n} are respectively applied to a dividing circuit 22 together with the respective clock signals, and the circuit generates a positive direction movement pulse P+ and a negative direction movement pulse P- whose directions are discriminated according to the amount of displacement. do.

3 and 4 show an example of a four-phase clock generator and its time chart. In the same figure, 2
3 to 26 are D flip-flops, and 27 is a Noah gate. Clock terminal of each D flip-flop
A clock signal of frequency n _c from oscillator 1 is applied to CK, and four-phase clock signals φ ₁ to φ ₄ having a phase shift of approximately 90° are generated.

Figures 5 and 6 show a dividing circuit (1/40 interpolation, resolution 5
μm) and its time chart. This divided circuit consists of four identically configured circuits 28 corresponding to each phase.
~ 31, one of which 28 is, for example, D
It consists of flip-flops 32, 33, a 4-bit shift register 34, NOR gates 35, 36, and AND gates 37, 38, 39, and the outputs _U1 to _U4 , _D1 to _D4 from each circuit 28 to 31 are OR gates. 40, 41.

Now, the carrier frequency _c is 50KHz, φ ₁ ~ _{φ 4}
If the clock frequency of is 500KHz, the dividing clock pulse φ included in one period of the phase modulation signal _S1 is
The number of _1s is 10 pulses. By the way, the D flip-flop 32 and the NOR gate 35 subtract _φ1 by one period of the clock pulse _φ1 in synchronization with the falling edge of the phase modulation signal _S1 . Next, a load pulse for the shift register 34 is generated by the D flip-flop 33 and the NOR gate 36 during one period following the clock pulse _φ1 , and in synchronization with _φ1 , the terminals Q _A to Q _D of the shift register 34 are loaded with 0, 0,
A pattern of 011,0 is loaded.

Thereafter, the shift register 34 starts shifting from the next clock pulse φ ₁ , and if the number of φ ₁ pulses in that column is greater than the steady state, the AND gate 37 is started in synchronization with the falling edge of the next phase modulation signal S ₁ . Open,
Positive direction movement pulse P+ from addition side OR gate 40
occurs. Similarly, when the number of clock pulses _φ1 is less than a constant, the AND gate 38 is opened at the next fall of the phase modulation signal _S1 , and the OR gate 41 on the subtracting side generates a negative movement pulse P-. The operations of circuits 29 to 31 are also exactly the same as described above. Although m=4 here, the circuits 28, 3
By using a two-phase configuration of only 0 or 29 and 31, the resolution can be increased to, for example, 10 μm, or even 20 μm by using only one circuit.

As mentioned above, the displacement detection circuit shown in Fig. 2 is obtained by generating a balanced modulated wave from signals with frequencies _c and n/m _c (n/m-1) _c or (n/m+1). A sideband wave having a frequency of _c is phase-compared with an m-phase signal having a phase shift of 2π/m at a frequency n/m _c , and a pulse of a frequency _c of an m-phase with a phase shift of approximately 2π/m is obtained. A phase modulated signal can be obtained, and the change per pulse when dividing into n can be sequentially multiplied by m for each phase and detected, and by changing this m, the resolution can be changed. is possible.

However, here, the frequency (n/ _m -1) _c or (n/m+1) _c obtained by generating a balanced modulated wave from signals with frequencies _c and n/m c
When the sideband waves of the magnetic scale fluctuate due to jitter or noise superimposed on the circuit system at the moment when the magnetic scale is stationary or in a stationary state, the lowest digit of the counter display becomes unstable.

The present invention has been made to eliminate such a phenomenon, and the phase of the sideband wave of frequency (n/m-1) _c or (n/m+1) _c is changed depending on the positive or negative direction moving signal. /m-1)n _c or (n/m+1)n _c clock signal, and then the positive or negative movement direction (addition The invention is characterized in that the above-mentioned flickering of the display is prevented by providing hysteresis in the direction (or subtraction direction).In order to reduce the operating speed of the clock signal, the phase of the sideband wave is adjusted to each of the m phases. The frequency (n/m-1)n/m _c or (n/m+1)n/m depending on the positive or negative moving signal of each phase in
After being changed by the clock signal _c , the phase of the sideband may be returned to its original phase by a positive or negative moving signal from all phases.

To further explain the present invention with reference to the embodiments shown in the drawings, FIG. 7 shows an embodiment in which a display flicker prevention circuit (feedback circuit) according to the present invention is provided in each phase of the divided circuit shown in FIG. show. In the figure, 42 and 48 are D flip-flops;
Numerals 3, 44 and 45 are NAND circuits, and 46 and 47 are NAND circuits forming a flip-flop.
Furthermore, the D flip-flop 42 has a frequency (n/m
-1) A clock signal CK of n/m _c or (n/m+1)n/m _c is supplied. Furthermore, NAND circuit 46
The positive direction movement pulse +P is applied to the NAND circuit 47, and the output _D1 from the circuit 28 of each phase is applied to the NAND circuit 47, so that the NAND circuits 43 and 44 are opened and closed by the respective outputs.

Now, when the phase modulated signal S ₁ (sideband) enters the D flip-flop 42, its phase is shifted in the D flip-flop 42 by the clock signal CK ₁ . At this time, the output _D1 causes the NAND circuit 43 to
is closed, the NAND circuit 44 is opened, and the phase-shifted signal _S1 is applied to the D flip-flop 48, where the phase is compared with the clock signal φ1 having the frequency n/ _mc as described above, and the phase is compared with the clock signal _φ1 having the frequency n/ _mc . A phase modulated signal is obtained.

Next, by the positive direction movement pulse +P, the NAND circuit 4
4 is closed and the NAND circuit 43 is opened, the original signal S ₁ , that is, the signal S ₁ whose phase has been restored to its original state, is provided to the D flip-flop 48 .

In this way, hysteresis can be provided in the positive and negative movement directions.

Figure 8 is a timing chart showing the above-mentioned operation, in which +H represents hysteresis in the positive direction (addition direction), -H represents hysteresis in the negative direction (subtraction direction), and the maximum value is the minimum resolution.
Equivalent to 1/2 the amount of displacement.

As is clear from the above explanation, according to the present invention, when generating a phase modulation signal with a carrier frequency _c , in a system where the resolution can be changed by appropriately selecting m for the number of divisions n, it is possible to change the resolution by appropriately selecting m for the number of divisions n. There is no need to change constants to determine the amount of hysteresis in the addition/subtraction direction in accordance with the resolution.

Furthermore, in the past, an analog method was used in which the pulse width of the phase modulation signal was changed by changing the DC level of the Schmitt circuit, but in the present invention, the sideband wave obtained by balanced modulation wave generation is The interpolation circuit, including a feedback circuit for varying the phase with clock pulses corresponding to the minimum resolution and providing hysteresis in the positive and negative movement directions, can be processed using digital signals, and can also be used even at a lower operating frequency, making the circuit It is also advantageous for converting to LSI.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional displacement detection circuit, Fig. 2 is a block diagram showing a displacement detection circuit to which the present invention is applied, and Fig. 3 is a four-phase clock generator used in the circuit. A block diagram showing an example of the circuit, FIG. 4 is a time chart for explaining its operation,
5 is a block diagram showing an example of the configuration of a dividing circuit used in the circuit of FIG. 2, FIG. 6 is a time chart for explaining its operation, and FIG. 7 is a block diagram showing an embodiment of the present invention. FIG. 8 is a time chart for explaining its operation. 1: Oscillator, 6: Magnetic scale, 7, 8: Magnetic head, 43-47: NAND circuit, 42, 48:
D flipflop.

Claims (1)

[Claims] 1. A circuit that generates a phase modulation signal of frequency _c having a phase corresponding to the amount of displacement, and a balanced modulator to which the phase modulation signal from the circuit and a clock signal of frequency n/m _c are applied. , a bandpass filter that passes a balanced modulation signal of frequency (n/m-1) _c or (n/m+1) _c from the balanced modulator, and m stages to which the signal passed through the filter and m-phase clock pulses are applied. a phase comparator, a dividing circuit that generates a positive or negative moving pulse from the m-phase phase modulation signal of frequency _c from the phase comparator and the m-phase clock pulse; (n-m-n) according to the negative direction movement pulse
1. A displacement detection circuit comprising: a circuit that changes the phase using a clock signal having a frequency of n _c or (n/m+1) n _c and then returns the phase to its original state using a positive or negative direction moving pulse. 2. A circuit that generates a phase modulation signal of frequency _c having a phase corresponding to the amount of displacement, a balanced modulator to which the phase modulation signal from the circuit and a clock signal of frequency n/m _c are supplied, and a circuit from the balanced modulator. a bandpass filter that passes a balanced modulation signal with a frequency of (n/m-1) _c or (n/m+1) _c ; an m-stage phase comparator to which the signal passed through the filter and an m-phase clock pulse are applied; a dividing circuit that generates a positive or negative moving pulse from the phase modulation signal of the frequency _c m phase from the phase comparator and the clock pulse of the m phase; The phase of the balanced modulation signal is set as (n/m-1)n/m _c or (n/m+1)n/
1. A displacement detection circuit comprising: a circuit that changes the phase using a clock signal having a frequency m _c and then returns the phase to its original state using a positive or negative moving pulse from all phases.