JPS607426B2 - answering machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention converts audio signals into continuous signals such as dial tones,
Concerning a signal discrimination circuit that can distinguish between intermittent signals such as a busy tone or no signal, if the operating point is set so that it can be reliably switched by a voice signal, continuous signals,
Depending on the amplitude and constant of the intermittent signal, it has the advantage that it is not affected by the time during which the input intermittent signal is transmitted or the time during which it is interrupted.

Such a signal discrimination circuit can be used, for example, in the device described below.

In other words, while the answering machine is intermittently operating while the caller's voice is being input without interruption for a predetermined period of time (for example, 1 hour), all of the customer's voice is recorded on a recording tape. After recording, when the caller finishes using the device and hangs up the handset, the station sends an intermittent signal like a busy tone or a continuous signal like a dial tone to the device, depending on the region. However, if this state continues for a predetermined period of time (for example, about 1 peak), it is used for purposes such as restoring the device to a standby state. Conventionally, a filter circuit, for example, has been known to be used for the above-mentioned purpose. However, this method has the drawback of causing malfunctions due to frequency shifts in mid-word sounds and dial tones, and harmonics. The present invention has been made in order to improve the above-mentioned drawbacks, and has the following objectives: 1) It is not affected by the busy tone or dial tone frequency; (This is easy because the input is the output of an amplifier with an automatic level control circuit.) It is not affected by the amplitude of dial tone or busy tone, and is not easily affected by the repetition frequency of intermittent signals such as glue or busy tone. It has many features.

Next, Fig. 1 is a circuit diagram showing one embodiment, and Fig. 2 is a circuit diagram of each part when an audio signal is input. Figure 3 shows the voltage waveform of each part when a lecture tone is input, and Figure 4 shows an example of an intermittent signal used in some foreign stations. .

First, in FIG. 1, 1 surrounded by a dotted line is a well-known rectifying and smoothing circuit.

2 is a switching circuit, and transistors QI and Q2 form a Schmitt circuit. Since a bias is applied to the base side of QI via resistor R2, Q is low when there is no input.
I is ON, therefore Q2 is OFF, and transistor Q3 connected to Q2 is ON.

3 is an integrating capacitor, which constitutes a charging/discharging circuit for the capacitor C3 via the above-mentioned Q3.

4 is a memory circuit which is a feature of the present invention and is a basic circuit, and transistors Q4 and Q5 are switching ICs.
I and IC4 are NAND gates, IC2 is a flip-flop circuit configured with NAND gates or a dedicated integrated circuit, and IC3 and IC5 are inverter ICs.

5 is a timer circuit including a relay Y, and when the transistor Q6 is turned on by the output of the IC5, the transistor Q7 is turned on by the pulse current of the capacitor C4, and the timer capacitor C5 is rapidly brought to a potential of nearly 112V via the diode D3. Charge it and repeat this while the audio signal is being input.

After the output of IC5 disappears, the electric charge of C5 keeps transistors Q8 and Q9 of about 1 ON', and the load relay Y can be held during that time. In addition, the input terminal I skin is normally ALC (automatic level control circuit)
A built-in amplifier is connected, and the voice signal, busy tone, and dial tone are amplified to an appropriate level by this amplifier and then input. If the operating point is set so that the second switching circuit is switched by the audio signal (which is easy since it has ALC), it will not be affected by the amplitude of the busy tone or dial tone, as will be described later. In addition, when the circuit shown in Fig. 1 is used for an answering machine, although not shown, while relay Y is held by voice, a DC loop of the telephone line is formed through the contacts of this relay, and When the caller finishes using the device and returns the handset, the device returns to the standby state when a busy tone or dial tone is input, or when relay Y is restored after about 1 hour of no signal. It is configured as follows.

"When an audio signal is input" In the circuit configured as described above, the operation when the audio signal shown in diagram A in FIG. 2 is input to the input terminal m will be explained.

That is, this audio signal is rectified into a negative voltage doubler by the diodes D1 and D2, and smoothed by the capacitor C2. C
2 is set to the minimum necessary capacity, this audio signal is enveloped in the negative direction as shown in diagram B. - in diagram B
VLI is the operating point of Schmitt circuits Q1 and Q2, and a negative voltage greater than 1 VLI cancels out the positive bias applied to the base side of QI via resistor R2, turning QI OFF and turning Q2 ON. do. Therefore, the collector voltage of Q2 becomes as shown in diagram C. On the other hand, since the output of Q2 is connected to the base side of the transistor Q3 via the resistor R6, when Q2 turns ON' as mentioned above, Q3
becomes OFF and starts charging the integrating capacitor C3 via the semi-fixed resistor R8. Diagram D shows this charging characteristic,
Charging starts at time axis tl, and the charging curve is C3 and R
It rises gradually according to a time constant of 8. and time axis t
3, when the input level of QI becomes below the operating point -VLI and returns to the state of QI being ON, Q2 being OFF, and Q3 being ON, the charge of capacitor C3 is transferred through the collector emitter of Q3 which is now ON. Discharge rapidly. Therefore, when the random audio signal shown in Figure A is added, the terminal voltage of capacitor C3 has an irregular waveform as shown in Figure D.
On the other hand, the collector side of transistor Q2 and the transistor Q
Since the base side of Q5 is connected to the base side of Q5 via the resistor RII, a waveform E diagram whose polarity is opposite to that of diagram C appears on the collector side of Q5, and a resistor R9 is connected between the collector side of Q3 and the base side of the transistor Q4. When the charging voltage of C3 becomes equal to or higher than VL2 in Figure D, transistor Q4 turns on.

Furthermore, the gate inputs 1 and 2 of the ICI of the NAND gate
is connected to the collector sides of Q4 and Q5, and when gate inputs 1 and 2 are both at H level, the gate output switches from H level to L level. As is clear from diagrams E and F, this period is the time axis tl~t2, t4~t5, t
6-t7, t8-t9, tll-t12, t13-t1
4 (this relationship is not shown). In the flip-flop circuit of IC2, the Q output terminal is preset to the H level when the preset terminal P falls to the L level, and when the reset terminal R falls to the L level (at this time, the P terminal must be at the H level). ) The Q output terminal has the property of being reset to L level. Therefore, as shown in diagram G, IC2 is reset at time axis tl, and Q4 at t2 is turned on.
It is reset at this point, and further preset at t4. However, between t5 and t6 and t7 and t8 in Figure E, even if the preset terminal P of IC2 returns to the H level, the reset terminal R does not go to the L level, so the Q output terminal that stores the preset state is at the H level. held at the level. (The R-S type flip-flop circuit has such a property). On the other hand, the collector side of Q5 is connected to the gate input 4 of 3 for the inverter, and its gate output is as shown in diagram H, and furthermore, its gate output is NAND
4 to gate input 6 to another gate input 7
is connected to the output terminal of IC2.

Therefore, when these two gate inputs are both at H level, the gate output 8 is at L level, so the inverter IC
The gate output 10 of No. 5 switches from L level to H level. The timing is as shown in the time axes t5 to t6 and t7 to t8 (hereinafter omitted) shown in FIG. 1 while both diagrams H and G are at the H level. As mentioned above, when the gate output of IC5 goes from L level to H level, the bias applied through resistor R13 turns transistor Q6 from OFF to ON, and therefore, the pulse current of capacitor C4 generated at this time momentarily turns transistor Q7 ON. However, Q at this time
Since the internal resistance between the emitter and collector of 7 is extremely small, the timer capacitor C5 is connected via diode ○3.
can be charged instantaneously to a voltage close to the electric current, and after the pulse current from C4 disappears and Q7 returns to OFF, the charge from C5 turns on transistors Q8 and Q9.
'Keep this, and in the example, Q7 is divided once within 1 sand.
If C5 is turned on and C5 can be charged, the load relay Y can be maintained continuously.

In the example, Q7 could be rubbed 2 to 4 times per second. The K diagram is the charging voltage of C5, and if VL3
(approximately 3 V in the embodiment) or lower, the IJ Ray Y is restored and the process is completed. "When a busy tone is input" Figure 3 shows the voltage waveforms of various parts when a busy tone is input.

For busy tone, the signal is sent for 0.5 seconds and then cut off for 0.5 seconds. Therefore, t15 to t17 and t17 to
t18 (the same applies hereinafter) is 0.9 sand. As aforementioned,
When this signal is rectified and smoothed, it becomes as shown in diagram B, and therefore the collector voltage of Q2 also becomes as shown in diagram C. As is clear from the above, since the capacitor C3 is charged from time axis t15 and this charge is discharged at t17,
The charging characteristics become regular as shown in the diagram. In the example, the above-mentioned VL2 is reached at time t16 after 0.29 sand (determined by the time constant of R8 and C3) has elapsed from t15.
At this time, transistor Q4 is turned on. This 0.2 scale is within a certain range (for example, 0.1
~0.4 seconds). The range within this range will be described later. Now, as described above, when Q4 is turned ON, the reset terminal R of the flip-flop IC2 becomes L level, and the Q output, which was preset to H level at t15, is reset to L level as shown in Figure G. Therefore G
If you compare the figure with the H figure, it is clear that there is no time when both of the two gate inputs of IC4 are at H level, and as is clear from the above, the Q output of IC2, which is preset to H level, is the gate of IC5. cannot appear in the output. Therefore, as mentioned above, the timer capacitor C
C5 could not be charged, and at time t27, about 1 hour after the busy tone input started, the C5
When the charging voltage is discharged to VL3, Q8 and Q9 turn OFF.
F, and relay Y can be restored.
"When Dial Tone is Input" The explanation of the operation in this case is the same as the explanation for the period t15 to t17 during which the busy tone is transmitted, so illustration of the voltage waveforms of each part is omitted.

Therefore, for example, when a dial tone is input from time axis t15, the charging voltage of capacitor C3 reaches VL2 at t16, which is 0.29 seconds later in the embodiment, and from this point on, the voltage of transistor Q4 becomes N as described above. Therefore, the reset terminal R of flip-flop IC2 becomes L level, and at the same time, the gate output terminal 3 of NAND gate ICI becomes H level, so IC2 is reliably reset, its Q output terminal becomes L level, and the dial tone is a continuous signal. Therefore, the above state continues, and the gate output 8 of IC4
is at H level and the gate output 10 of IC5 continues to be at L level, so as is clear from the above, timer capacitor C5 cannot be charged, and relay Y can be restored after about 1 hour. ``In the case of no signal'' The case where the calling party returns the handset and the input terminal IN is in a no-signal state is easy to explain.

To explain briefly, when there is no signal, t17 to t1 in Fig. 3
As shown in diagrams E and F between 8 and 8, the NAND gate ICI
Gate input 1 is at H level, gate input 2 is at L level, and its gate output is at H level. Therefore, the preset terminal P and the set terminal R of flip-flop IC2
Both are at H level. In this way, both R and P terminals are high.
If the level is high, does the Q output terminal become high level?
It is uncertain whether it will go to L level, but as long as the no-signal state continues, it will continue to be at a constant state of H level or L level, and as is clear from the above, transistor Q6 will be in the ON or OFF state. Capacitor C4 does not generate more than one pulse, so transistor Q7
The timer capacitor C5 cannot be repeatedly charged because it is not turned on more than once. Therefore, as is clear from the foregoing, the relay Y can be restored after about 1 hour after the discharge of the charge of C5 is completed. Above, the circuit diagram of FIG. 1 showing one embodiment of the present invention has been described specifically and in detail.

As mentioned above, when a signal such as voice, busy tone, dial tone, etc. is input and the switching circuit 2 is activated, the Q output terminal of the flip-flop circuit 2 is preset to the H level, and the above signal is transferred to the resistor R8 and the capacitor C3. In the creation explanation, 0.2 within a predetermined time determined by the time constant
When the above signal (9 stages) is disconnected, the output of the preset Q output terminal can be outputted through the NAND gate IC4, and after the above signal continues for more than 0.29 steps, it is disconnected. In other words, if it continues for 0.25 sand or more, the preset Q output of IC2 cannot be outputted via IC4.

Therefore, the maximum peak portion of the signal that can be outputted via IC4 appears from time to time, and the maximum peak portion appears between the pigs.
．． There are times when it is less than 29 sand (of course it is 0.0 at the maximum peak part).
(It can last more than 25 seconds in some cases) This means that it is only an audio signal. Therefore, the transistor Q6 is
The timer capacitor is recharged via the transistor Q7, which is instantaneously turned on by the pulse current generated by the capacitor C4 when power is repeatedly turned on and off, but it can be repeatedly charged only by an audio signal. It is. Moreover, since the internal resistance of Q7 and the forward internal resistance of diode D3 during this charging are extremely small,
Even if the voice from the caller is interrupted for a few seconds and then the voice is input again, it is possible to instantly charge the capacitor C5 to the maximum charging voltage value, which makes it possible to charge the capacitor C5 all at once to the maximum charging voltage value. Depending on the customer's way of speaking (such as when the customer pauses or pauses), it may work (of course, you should not interrupt more than one word, but you can change this 1 hour period as you like). It also has the advantage that it does not have the disadvantage of being canceled. In addition to the above-mentioned features, the present invention is also effective for the intermittent signal shown in FIG. 4 in which the amplitude levels are alternately different and the period during which the signal is transmitted is shorter than the busy tone.

That is, the time constant of the semi-fixed resistor R8 and the capacitor C3 may be set to be smaller than the time during which the signal shown in FIG. 4 is sent. Moreover, the switching circuit 2 may be conductive or non-conductive in a portion where the amplitude is 4·, such as from t30 to t31. Therefore, the signal discrimination circuit of the present invention can be used in any country in the world. It should be noted that the present invention is not limited to the embodiments illustrated and described above, but can be implemented with various modifications without changing the gist of the present invention.

For example, contrary to the circuit example of FIG. 1 described above, even if the switching circuit 2 becomes non-conductive due to the signal,
This 0.29
changing the output of the flip-flop IC2 so that it can be outputted via the NAND gate IC4 only when the switching circuit 2 becomes conductive within seconds (such action is possible only by voice as described above); A capacitor is used in place of IC2 to memorize the H level corresponding to the Q output, and as mentioned above, when the signal continues for more than 0.2 seconds and IC2 is reset, this capacitor has the same effect as when IC2 is reset. This is done by rapidly discharging the charge, and it is also possible to change the capacitor so that the charge cannot be output if the signal continues for 0.25 seconds or more, such as a busy tone.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the present invention showing one embodiment, in which 1 is a rectifying and smoothing circuit, 2 is a switching circuit, 3 is an integrating capacitor, 4 is a memory circuit, and 5 is a timer circuit. Diagrams A to K in FIG. 2 are voltage waveforms at each section of A to K in FIG. 1 when an audio signal is input. FIG. 3 shows the radio waveforms of each part when the busy tone is input as well. FIG. 4 shows the waveform of an intermittent signal used in some foreign stations. Spear Zuji Z Acid O 3 Zu Rikito Zu

Claims (1)

[Claims] 1. A rectifying and smoothing circuit that receives as input signals an intermittent signal such as a voice signal, a busy tone, a continuous signal such as a dial tone, or an intermittent signal with alternating amplitudes such as a bark tone (see Figure 4). and a switching circuit which inputs the DC output of the rectifying and smoothing circuit, and when the switching circuit becomes conductive (or non-conductive) due to the input signal, it is gradually charged and reaches a predetermined charging voltage after a predetermined time, and this input an integrating capacitor connected to rapidly discharge the charged voltage when the signal is disconnected from input (or input from disconnection), and preset when the switching circuit becomes conductive (or non-conductive) due to the input signal; If the switching circuit becomes non-conductive (or conductive) before the integrating capacitor reaches the predetermined charge voltage, the preset output is output, and the switching circuit becomes conductive (or non-conductive) for more than the predetermined time. ) Then, the integrating capacitor is provided with a memory circuit configured so that it cannot output the preset output, and a timer circuit that is charged (or discharged) by the output of this memory circuit, and when the integrating capacitor reaches the predetermined charging voltage. An answering machine characterized in that by setting the predetermined time until the intermittent signal reaches a period smaller than the time during which the intermittent signal is interrupted, a recovery action is performed for all input signals other than voice signals.