JPS6118771B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an input method for a data processing device.

Conventionally, in a device that inputs and processes data from an external input device in response to a program input command, data input becomes possible after the input command is issued, and data generated when the input command is not issued is ignored.

Therefore, with input devices such as keyboards that generate data asynchronously with the execution of a program, if the issuance of input commands is delayed due to internal processing, data that has been correctly pressed may be used, making it difficult for the operator to input data. Operability was poor because it was necessary to press the keys while confirming whether the input was possible, and it was necessary to add a lamp and buzzer circuit to the device to indicate that input was possible.

In order to eliminate this drawback, in a dedicated device that creates data by inputting from a keyboard, etc., a FIFO (first-in, first-out) buffer is installed as a method to ensure that the input data is always valid, and the generated data is temporarily stored in the FIFO buffer. , a method is used to retrieve data from the FIFO buffer when an input command is executed.

However, when FIFO buffer control is incorporated into a device that primarily processes data, data mismatched by the operator when the device is printing out data or performing internal calculations for a long time when no input commands have been issued will also enter the buffer. The drawback is that when an input command is issued, unexpected data is often captured by the program and causes malfunctions.

In either case, the processing when no input command is issued is fixed to the system, and it is difficult to implement a data processing program that follows the flow of input items.

According to the present invention, data generated by an external input device is always stored in a buffer, and data generated when an input command has not been issued as instructed by a program command is set to be valid or invalid.
Both of the above drawbacks can be solved by controlling whether the data already stored in the buffer is passed to the program as is when the program input command is issued, or whether it is ignored and only new input data is passed to the program, and the continuity of input items is improved. It is an object of the present invention to provide a device that can freely realize a data input method that takes account of the above factors by programming the program.

According to the present invention, there is a buffer that can store multiple data, a circuit for controlling the write address to the buffer (hereinafter referred to as W/P register), a circuit for controlling the read address (hereinafter referred to as R/P register), and a buffer inside the buffer. The data input device that stores the number of unprocessed data (hereinafter referred to as DNB counter) passes all the data generated by the external input device to the program as valid data, regardless of the timing of issuing the program input command. A circuit that stores the mode according to an instruction, and a W/P register that uses a signal that is output when an input instruction is issued.
By using a circuit that sets the R/P register and DNB counter to their initial values, it is possible to specify by a program command that the data that was in the buffer when the input command is issued is specified, and the data that matches the continuity of the input items can be specified. A data processing device that can easily implement an input control program from an external input device is obtained.

Next, embodiments of the present invention will be described with reference to the drawings. In FIG. 1, an external input device 1 includes a keyboard 11 and a register 12 of one character length for storing keystroke data from the keyboard. The FIFO buffer circuit 2 includes a buffer 21 for storing data for four characters, a read register 22 for reading data from the buffer 21, a main memory 23 for storing the data, and a buffer 21 for controlling the buffer 21. A counter 26 consisting of bits,
27 and 28. The FIFO control circuit 3 is a control circuit instructed by a program, and includes a one shot 31, a flip-flop 32, and a NAND gate 33 for controlling the FIFO buffer circuit 2. Next, in FIGS. 1 and 2, writing of data to the FIFO buffer 21 is performed as follows.

When a key is pressed on the keyboard 11, an output code is set in the DO register 12 and a signal STB11 is output.
1 is output.

In response to the signal STB, the contents of the DO register are written to address F0 of the buffer indicated by the WP register 26, and the contents of the DNB counter 28 are increased by 1 to indicate that the unprocessed data is in the FIFO buffer.
Furthermore, the contents of the WP register are incremented by 1 in preparation for the next data keystroke.

After that, as data is input, the contents of the W/P register will be 1 → 2 → 3 → 0 → 1... and the data will be F.
It is stored in the positions 1→F2→F3→F0→F1...

Data read from the FIFO buffer 21 operates differently when an input command is issued, depending on the state of the mode flip-flop 32 controlled by program commands.

When an instruction to invalidate the data generated when no input command is issued is executed, the mode flip-flop forced set signal MSET is generated and the signal MODE (311) becomes "1", and when an instruction to make it valid is executed, the forced reset signal is generated. MREST occurs and the signal MODE becomes "0". When the input command (INP) is issued, if the MODE signal is "1" (Fig. 2), the signal CLR becomes "0" due to the output signal of the one-shot circuit 31 driven by the INP signal and the NAND gate 33, and the WP register, R. The P register and DNB counter are each reset (initialized, so the data A, B, and C stored in the FIFO buffer 21 are ignored, and when the data D pressed after that is input)
The content of the DNB counter becomes 1 and AND gate 2
4 and 25 are satisfied, the data is taken into the main storage device through the DI register 22. At the same time, the DNB counter is -1 and the R and P registers are +1 to prepare for the next data input.

When the character count data specified by the program is loaded into the main memory, the input command ends and the INP signal becomes "0", so the subsequent keystroke data is stored in the FIFO.
It is held in buffer 21.

If MODE is switched to “0” before issuing the next input command, when the input command execution starts
The CLR signal remains “1” and the WP register
The contents of the RP register and DNB counter do not change (Figure 2). Therefore, the data GHI stored in the FIFO buffer 21 is treated as valid data and is sent to the DO along with the data J that was subsequently pressed.
Loaded into main memory through registers.

In this way, in a program, all you have to do is put an instruction to control the mode into a series of processing programs.
Data inputted when an input command has not been issued can be made valid or invalidated, and a data input processing program that takes into account the continuity of input items can be realized in a large capacity.

As explained above, by making it possible to control whether data generated when data has not been issued is made valid or invalid by a program, data that matches the processing flow of input items and can prevent malfunctions due to erroneous operations can be created. A processing device can be realized.

[Brief explanation of the drawing]

FIG. 1 shows a circuit showing one embodiment of the present invention, and FIG.
This figure is a diagram showing a time chart in the circuit of FIG. 1. 1...External input device, 11...Keyboard, 12...
Register, 2... FIFO buffer circuit, 21... Buffer, 22... Read register, 23... Main storage device, 24, 25... AND gate, 26, 27, 2
8... Counter, 3... FIFO control circuit, 31... One shot, 32... Flip-flop, 33...
NAND gate.

Claims (1)

[Claims] 1 In a device that inputs and processes data from an external input device via a buffer according to a program command, is the data that entered the buffer when the input command has not been issued treated as valid data when the input command is subsequently executed? , a data processing device comprising means for specifying whether to ignore data as invalid data by a program command.