JPS6240885B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a variable frequency divider circuit that can set an arbitrary number of frequency division numbers according to a numerical value given from the outside, and particularly relates to a variable frequency divider circuit that can effectively provide a frequency division number offset in a swallow counter frequency division method. . A variable frequency divider circuit using a swallow counter frequency divider basically has two circuits, P and P+1, as shown in Figure 1.
A controlled prescaler 1 that performs value frequency division, an auxiliary variable frequency divider circuit 2 that divides the output of this prescaler 1 by M using external data M (OM<P) that specifies a frequency division value, and a control type prescaler 1 that performs value frequency division; N by external data N (P-1N) that specifies the frequency division value.
A main variable frequency divider circuit 3 that divides the frequency, and a flip-flop 4 that is set and reset by the outputs of these frequency dividers 2 and 3 to switch the frequency division value of the prescaler 1 and set the operating cycle of the auxiliary variable frequency divider circuit 2. configured. In this circuit, as is clear from the timing diagram of FIG. 2, the frequency division number for external data M and N is (P+1)M+P×(N-M)=M+PN. For example, when P=10, it becomes M+10N, which corresponds to M giving the first digit of the frequency division number and N giving the second and higher digits. This method can reduce the operating speed of the auxiliary variable frequency divider circuit 2 and the main variable frequency divider circuit 3 to approximately 1/P compared to the controlled prescaler 1, so if the controlled prescaler 1 can be made faster, the overall frequency will be higher. This has the advantage of realizing a variable frequency divider circuit. By the way, in the swirl counter frequency division method, it is relatively difficult to provide a so-called frequency division number offset, which is an operation of dividing external data specifying a frequency division number by a value shifted by a fixed number. In the variable frequency divider circuit of the down-counting method, which is most commonly used in the past, offset can be easily achieved by detecting the final state of counting as 0 or a non-zero value, but the swallow counter frequency divider circuit In this case, no such fixed method has been found. Conventionally, the most common method is to introduce a new adder, create data by adding an offset number to external data, and use this as the dividing value setting data for the swirl counter frequency division method. However, this has the disadvantage that the configuration is complicated by the adder. Furthermore, the method previously proposed by the present inventor in Japanese Patent Laid-Open No. 53-121559 is still inconvenient in that it does not require an adder but requires a counting circuit for offset. In view of the above-mentioned points, the present invention provides a variable frequency dividing circuit using a swirl counter frequency division method, which makes it possible to provide an effective frequency division offset with a very simple circuit configuration. The gist of this invention is to calculate the offset number by ΔM+P×
Divide into ΔM and ΔN where ΔN (ΔM<P), ΔM
For , an addition operation is performed with external data M and the dividing value setting data M + ΔM is provided to the auxiliary variable frequency divider circuit, while for ΔN, the final state of counting in the main variable frequency divider circuit is expressed as a value of −ΔN. The point is that an offset is taken depending on the detection method. Here, the method of using the main variable frequency divider circuit as a down-count method and taking a frequency division number offset of .DELTA.N has been established as a commonly used and extremely simple method. On the other hand, an addition operation is required to obtain M+ΔM for ΔM, but since the numerical values of ΔM and M are smaller than P, the number of bits is small, and it can be realized with a simple gate configuration without the need for an ordinary adder. .
Therefore, according to the present invention, it is possible to obtain an effective frequency division offset with an extremely simple circuit configuration, without requiring addition of multiple bits or multiple digits as in the prior art, and without providing a new counting circuit for offset. You can take it. The present invention will be explained in detail below with reference to Examples.
One of the suitable application fields for the variable frequency divider circuit using the swirl counter frequency division method is PLL of FM/AM receiver.
(Phase Locked Loop) frequency synthesizer. In this case, the variable frequency dividing circuit divides the local oscillation frequency of the receiver by a value corresponding to the selected channel frequency. For example, the frequency division numbers when applied to Japanese and American FM receivers are shown in the table below.

[Table] Taking the Japan FM band as an example, if the external data specifying the frequency division value is 654, 76.1MHz will be received,
793, 90.0MHz will be received. Therefore, it is basically sufficient to give 654 to 793 as external data, but usually direct external data is given as 0 to 793.
139, and 654 is added internally to this and given as data. That is, 654 is the offset value of the frequency division number. The main reason for setting the external data as the starting point at 0 and giving the division value by using the deviation from this as the offset value is to perform data processing such as band scan operations and operations that prohibit data from entering outside the band. This is for the convenience of the above. An embodiment of the present invention applied to a PLL frequency synthesizer for an FM receiver as described above will be described with reference to FIG. Here, P=10 is assumed as the most frequently used example. That is, the controlled prescaler 1
1 performs a frequency dividing operation of P=10 to P+1=11. From the formula ΔM+10×ΔN, the offset number is ΔM=4 and ΔN=65 for the Japanese FM band, and for the US FM band
In the band, ΔM=8 and ΔN=98. The main variable frequency divider circuit 13 is constructed using the usual down-counting method, and the final state of counting is -65 for the Japanese FM band and -65 for the US FM band.
For obi, set it to -98. Therefore, the main variable frequency divider circuit 13, for the input external data N,
The frequency division operation will be N+65 (Japan FM band) and N+98 (US FM band). The adder 15 adds ΔM to the external data M and supplies this to the auxiliary variable frequency divider circuit 12. Auxiliary variable frequency divider circuit 1
2, the external data M changes from 0 to 9 (=P-1), so 9 + ΔM, that is, 13 in the Japanese FM band and 13 in the US
It is configured to allow frequency division up to 17 in the FM band.
As will be described later, in order to simplify the adder 15, the auxiliary variable frequency divider circuit 12 is of a down-count type with binary operation. The flip-flop 14 sends a preset signal to the auxiliary variable frequency divider circuit 12 so that the auxiliary variable frequency divider circuit 12 performs M+ΔM frequency division once during one cycle of operation of the main variable frequency divider circuit 13, and Frequency dividing circuit 12
A switching control signal is sent to the controlled prescaler 11 so that the controlled prescaler 11 divides the frequency by P+1=11 only during the period when the frequency is divided by M+ΔM. Now, regarding the configuration of the adder 15, in the present example, M is 0 to 9, and ΔM is 4 or 8 in some cases. M is the BCD code “A ₀ (LSB), B ₀ , C ₀ ,
D ₀ '', the adder 15 that obtains M+ΔM may be constructed as shown in FIG. 4 a or b. A is a circuit that obtains M+4, and b is a circuit that obtains M+8. So, external data M
To obtain M+4 from , you only need one inverter and one OR gate, and to obtain M+8, you only need one inverter. With this configuration, 1 as external data
When the digit is given as M and the second and above digits are given as N, that is, M+10N, the frequency divided by P+1=11 by the control type prescaler 11 in one cycle of operation of the main variable frequency divider circuit 13 is given as M+ΔM times, P Since the frequency divided by =10 is counted N+ΔN-(M+ΔM) times, the frequency division number is (M+ΔM)×11+{N+ΔN-(M+ΔM)}×10=M+10N+ΔM+ΔN×10. That is, for the Japanese FM band, the frequency division operation is M+10N+4+65×10=M+10N+654, and for the American FM band, the frequency division operation is M+10N+8+98×10=M+10N+988, and the desired offset frequency division can be achieved. As already mentioned, the main variable frequency divider circuit 13 sets the final state of counting, that is, the preset signal detection point, to −ΔN.
This method does not complicate the circuit configuration in any way, and the adder 15 can also be substantially composed of several gates. According to this embodiment, for example, the offset number for M+10N can be set as the conventional method.
Compared to the method of adding data such as 654, 988, etc., it is possible to effectively provide a frequency division number offset with a very simple circuit configuration. In addition, in the example, Δ is applied to an FM receiver.
Although we have explained the case where M = 4, 8, M+ can be applied even if ΔM = 1, 2, 3, 5, 7, 9 in other applications.
The adder for obtaining ΔM can be easily constructed by a combination of gates.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a variable frequency divider circuit using a swirl counter frequency division method, FIG. 2 is an operation timing diagram thereof, and FIG. 4a and 4b are diagrams showing an example of the configuration of the adder in FIG. 3. 11...Controlled prescaler, 12...Auxiliary variable frequency divider circuit, 13...Main variable frequency divider circuit, 14...
Flip-flop, 15...adder.

Claims (1)

[Claims] 1 Set a constant value Δ to external data M that specifies the frequency division value.
A circuit that adds M and this circuit output data M+Δ
An auxiliary variable frequency divider circuit that receives M as an input and divides the frequency by M+ΔM, and a main variable divider that receives external data N that specifies a frequency division value and is configured so that the preset signal detection point is set at -ΔN and divides the frequency by N+ΔN. frequency circuit, and a controlled prescaler that performs P frequency division and P+1 frequency division by being switched by control signals from these variable frequency dividing circuits, inputs the input to be divided into the controlled prescaler, and outputs the output from the controlled prescaler. A variable frequency divider circuit, characterized in that an input signal is input to the auxiliary variable frequency divider circuit and the main variable frequency divider circuit to obtain an M+PN+ΔM+P×ΔN frequency divided output from the main variable frequency divider circuit.