JPS6242307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a page control method in a data processing system having a main memory accessed using a page address method.

In a data processing system having a large-capacity main memory, it is common to access the main memory using a page address method. For example, as shown in Figure 1, in a data processing system in which a main memory device MM and a channel device CH are connected to a central processing unit CC via a bus BS, the main memory device MM is accessed using a page address method. For this purpose, page registers PR and CPR are provided in the central processing unit CC and channel unit CH, respectively.

The page register PR of the central processing unit CC consists of a register JPR indicating the jump destination page, a register PPR for operand fetch, and a register LPR for instruction fetch.
As shown in the figure, when a jump instruction jp is given, the jump destination page set in the register JPR is transferred to the main memory via gate circuits G3 and G6.
Sent to MM. Similarly, the page address set in register PPR by operand fetch instruction pf is sent to main memory device MM via gate circuits G4 and G6, and the page address set in register LPR by instruction fetch instruction if is sent to main memory MM. It is sent to the main memory device MM via gate circuits G5 and G6.

When transmitting channel data, e.g.
When transferring data between CH1 and the main memory device MM, a page address is set in the page register CPR of the channel device CH1, and the data is transferred to the main memory device via the gate circuits G1 and G6 by the transfer command ch1.
The page address is sent to the MM and the channel device
When transferring data between CH2 and the main memory device MM, a page address is set in the page register CPR of the channel device CH2, and the data is transferred to the main memory device via gate circuits G2 and G6 by the transfer command ch2.
The page address is sent to MM.

Note that the operation of the central processing unit is roughly performed as follows.

To execute a macro instruction, the microprogram in the macro instruction processing section performs an instruction fetch, and then the microprogram routines corresponding to various macro instructions are activated to carry out operations such as Oheland fetch, calculation, and storage of calculation results. will be held. When execution of one macroinstruction is completed, the operation is repeated from the instruction fetch for the next macroinstruction. During this time, JPR,
Necessary page specification information is set in each of the LPR and PPR registers. The contents of this register remain at the previously set value unless intentionally changed by a macro instruction.

On the other hand, a channel operation is activated by a channel command, which is a type of macro command, but data transfer itself between an input/output device and a main memory device is not performed until a data transfer request is received from the input/output device. That is, the channel instruction ends with only the initial setting of the channel operation, and the central processing unit moves on to execution of the next macro instruction. If a data transfer request is received from an input/output device while a macro instruction is being executed, the execution of the microprogram is interrupted, a channel operation microprogram is started, and after the data has been transferred, the process returns to the macro instruction processing microprogram.

As described above, each channel device must be provided with a page register CPR for data transfer between the channel device and the main storage device, which has the drawback of increasing the cost of the entire system.

Therefore, the page register CPR of each channel device
omit register PPR for operand fetch
It is being considered that the register can also be used as a page register of a channel device. In this case, when transferring data between the channel device and main memory, register PPR
Save the page address for the operand fetch, write the page address for channel data transfer to this register PPR, send this page address to the main memory, and save it after the data transfer between the channel device and the main memory is completed. The page address for the operand fetch that was previously deleted is restored and the next instruction is executed, which complicates the software processing for saving and restoring the contents of the register PPR.
There was a risk that errors would occur as a result of the return.

In other words, in order to transfer channel data, it is naturally necessary to set a page in the main memory, but if register PPR is used as described above, the contents of the register will be updated each time channel operation and macro instruction completion are switched. It is necessary to evacuate and return. This saving and restoring processing is performed by a microprogram, but as the frequency of switching increases, the proportion of time spent on this processing increases, and the processing capacity of the central processing unit substantially decreases.

The present invention improves the conventional drawbacks as described above, and aims to provide an economical configuration and simplify software processing, and to avoid switching between channel operation and macro instruction execution. , another page register is provided within the central processing unit to perform data transfer. Examples will be described in detail below.

FIG. 3 is a block diagram of an embodiment of the present invention, in which a page address is temporarily set in the page register PR of the central processing unit CC for data transfer between the channel device CH and the main memory device MM. A register UPR is provided so that even if a macro instruction is interrupted due to a channel data transfer or the like, there is no need to rewrite the contents of the macro instruction page register, that is, to save and restore the contents. Each channel device CH is not provided with a page register, and data is transferred to and from the main memory device MM via the bus BS.

Figure 4 shows the page register PR of the central processing unit CC.
It is a main part block diagram for explaining the operation of G11.
~G18 is an and gate, G19 is an or gate,
PA1~PA4 are page addresses, w1~
w4 is a write signal, ch is a channel data transfer instruction, jp is a jump instruction, pf is an operand fetch instruction, and if is an instruction fetch instruction. jump instruction jp, operand fetch instruction pf
The same operation as before is performed for the instruction fetch instruction if, and in the channel transfer instruction ch, the page address for channel data transfer is set according to the channel data transfer request.
PA1 is written to the register UPR by the write signal w1, and the page address is sent to the main memory device MM via the AND gate G15 and OR gate G19 by the channel transfer command ch, and the channel device makes a channel data transfer request. Data transfer is performed between CH and main memory MM.

In this channel data transfer, it is also possible to adopt a method in which data from the channel device CH is once buffered in the central processing unit CC and then transferred to the main memory device MM. That is, the page address set in register UPR and the channel device CH
It is also possible to send data from the central processing unit CC to the main memory unit MM via the bus BS.

In addition, the register UPR is used not only to set the page address during data transfer between the channel device CH and the main memory device MM, but also to access the main memory device MM during system control within the central processing unit CC. It is possible to set the page address in case of

As explained above, the present invention provides a channel device
It is possible to transfer data between the channel device CH and the main memory device MM without providing a page register in the CH, and there is no need to save the contents of the register for executing macro instructions, so software processing is significantly reduced. This has the advantage of being simple and requiring no page register in the channel device CH, resulting in an economical configuration.

In addition, in order to further realize parallel operation of channel devices in such a device, a save area corresponding to the number of channel devices connected as a system should be secured on the main memory, and a save area corresponding to the number of channel devices connected as a system should be secured. Even if switching and channel operations are continuous, it is necessary to perform evacuation and return processing when switching between different channel devices. Although this processing is also performed by microprogram processing, it is much more complicated than when there is only a single channel device, and therefore the processing capacity is further reduced. Therefore, in order to simplify software processing, it is desirable not to operate the channel devices in parallel.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional data processing system, Fig. 2 is a main part block diagram for explaining the operation of a conventional page register, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram of an embodiment of the present invention. FIG. 2 is a main part block diagram for explaining the operation of a page register according to an embodiment of the present invention. CC is the central processing unit, MM is the main memory, CH is the channel device, PR, CPR are the page registers,
UPR, JPR, PPR, and LPR are registers, and BS is a bus.

Claims (1)

[Claims] 1. In a data processing system consisting of a main memory device accessed by a central processing unit using a page address method and a channel device connected to the central processing unit, an instruction is read from the main memory device when a macro instruction is executed, and data is stored in the data processing system. A plurality of registers for setting page addresses for reading, etc., and accessing the main memory during data transfer between the channel device and the main memory or system control within the central processing unit. A page register consisting of only one register UPR in the entire system is provided in the central processing unit, and when the macro instruction is interrupted and the main memory is accessed, the one register is used to obtain the page address. A page control method characterized in that a page address is set, and the main storage device is accessed using the page address to perform data transfer.