JPS6258019B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data comparison device for comparing the magnitude of numerical values in a data processing device. 2. Description of the Related Art Conventionally, when determining the magnitude of numerical data in a data processing apparatus, a method of subtracting between numerical values to be compared is generally used to determine the magnitude of numerical data. In a data processing device that handles data with a relatively large number of numerical digits, especially in a data processing device that handles variable-length data that can specify up to a relatively large number of digits, when the number of digits for subtraction increases, it becomes too large to operate on all digits at the same time. It requires a large arithmetic unit, which is uneconomical, and if the calculation is divided into a specific number of digits, the calculation time increases. In addition, in data processing devices that allow you to specify a unique exponent for each numerical value, it is necessary to align the digits of each numerical value before subtraction, and the content of the actual numerical values being compared must be adjusted. It is extremely inefficient. This invention was made in view of the above circumstances, and for example, depending on the number of digits of numerical values such as "5" and "10",
For example, when the magnitude of a numerical value can be determined by comparing only the most significant digits, such as "19" and "20", the magnitude of the numerical value can be determined without performing subtraction processing between the comparands. It is an object of the present invention to provide a data comparison device that realizes efficient comparison processing. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the relationship between a processing device and data. In the figure, 1 is a data processing device, 2 is a main storage device, and the data processing device 1 compares data a and b in the main storage device by executing a comparison instruction. Similar to a normal information processing system, the data processing device 1 sequentially imports data a and b of a specified length into the data processing device 1 from the address in the main storage device 2 specified by the instruction, starting from the most significant digits. shall be included. Data transfer between the data processing device 1 and the main memory device 2 is carried out 16 bits at a time through the data bus 3, and the data handled is 4 bits representing one decimal digit.
Assume BCD code decimal number. Further, in the data processing device 1, after the execution of an instruction is started, the length of each data, exponent, etc. are appropriately prepared as information necessary for execution. That is, the length register 4 in the data processing device 1 shown in FIG.
The length of data a is stored in length register 5, the length of data b is stored in exponent register 6, and the exponent of data a is stored in exponent register 6.
It is assumed that the index of data b is prepared for each. The sign of each data is determined by a ready-made method, for example, a code reader 8, and if it is plus (+), "0" is set, and if it is minus (-), "1" is set in flip-flops 9 and 10. It is assumed that the code of data a is set in flip-flop 9 and the code of data b is set in flip-flop 10. FIG. 2 is a functional configuration diagram showing an embodiment of the present invention. In the figure, 4 to 7 are registers that hold the length and exponent of data as described above, 8 is a code reader that reads data codes, and 9 and 10 are flip-flops that hold respective codes. Data a and b from the main storage device 2 are input via the bus 3 and are read by a code reader 8, and the reading results are set in flip-flops 9 or 10 in accordance with the respective data. Further, data for use in calculations is written to the data register 100. 11 is a leading cell counter that accumulates the number of high-order zero digits until a non-zero value appears in the data from the bus 3. Furthermore, this leading zero counter 11
The details will be explained in FIG. When the first non-zero value appears, the leading zero counter 11 sends a selection signal indicating the digit position to the data selector 20 and a write signal to the register 21 or 22. Then, the most significant 4 non-zero bits of data a are stored in the register 21, and similarly data b is stored in register 21.
The most significant 4 non-zero bits of 0 are stored in register 22. 12, 13, and 16 are well-known two's complement type adders/subtractors, and 26 is a data comparator that determines the magnitude of 4-bit data. 1", and if both are equal, output 24
only “1”, the contents of register 22 are register 2
If it is larger than the content of 1, only the output 25 is set to "1". The number of consecutive zero digits from the most significant digit accumulated by the leading zero counter 11 is subtracted from the specified data length by the subtracter 12, and the output of the subtracter 12 shows the actual digits of the data. The number will be output. Furthermore, the corresponding exponent is added to this output by adder 13, and then the adder 1
From 3, the effective number of digits of the data is output. data a
The effective number of digits of data b is stored in register 14, and the effective number of digits of data b is stored in register 15. Note that each of the above registers 4, 5, 6, 7, 14, 15, 21, 2
2 shows numerical values corresponding to data a and b illustrated in Table-1.

[Table] The subtracter 16 subtracts the contents of the register 15 from the contents of the register 14, and the inverse subtracter 16 outputs the sign 19 of the result of the subtraction. Further, the decoder 17 checks whether the output data of the subtracter 16 is zero. For example, subtractor 1
When the result of subtraction by 6 is a positive number or zero, the signal line 19 is set to "0", and when it is negative, the signal line 19 is set to "0".
Set to “1”. Further, when the subtraction result is zero (that is, when the contents of the registers 14 and 15 are equal), the output 18 of the decoder 17 becomes "1", and otherwise becomes "0". The zero detector 27 detects that the contents of the registers 14 and 15 are both zero. For example, when the contents of the registers 14 and 15 are both zero, it outputs "1" to its output 28; In this case, the output 28 becomes "0". Next, the operation of the circuit shown in FIG. 2 will be explained below using data a and b shown in Table 1 as an example.
First, data a transferred from data path 3
The data “0” indicating the sign “+” is the code reader 8.
As a result, the flip-flop 9 is set. Further, the number of zeros in the upper digits of the numerical value "00012345678" of data a is counted by the leading zero counter 11, and the count number "3""0011" is output to one side of the subtractor 12. Further, when the leading zero counter 11 detects the first non-zero value "1" of the data a, a selection signal is given to the selector 20 and a write signal is given to the register 21. As a result, the BCD data “0001” of the numerical value “1” is set to selector 2.
0 to register 21. On the other hand, in the subtracter 12, the significant digit of data a is "11".
The leading zero count value “3” “0011” is subtracted from “001011” and the subtracted value “001000”
is output to one side of the adder 13. The adder 13 outputs the subtracted value "001000" and the data a index "6".
“000110” is added and the addition result is “001110”
is set in register 14. A similar operation is performed for data b. In the operation of data b, the flip-flop 10 is similarly set, and the first non-zero value "5""0101" is set in the register 22. Also, the subtractor 12
Then, the significant digits of data b are “8” “001000” – “0001”
(Reading zero count value of data b) is subtracted and the subtracted value "000111" is sent to the adder 13.
Output to. Further, the adder 13 performs addition processing of the exponents "11", "001011" and "000111" of the data b, and as a result "010010" is set in the register 15. According to the embodiment shown in Table 1 above, only the output 25 of the data comparator 26 becomes "1",
Outputs 23 and 24 are "0". Also, the subtractor 16
The output signal line 19 becomes "1" (meaning that the subtraction result is negative). Further, the outputs 28 and 18 become "0", and the outputs 9' and 10' of the flip-flops 9 and 10 become "1". FIG. 3 shows a specific example of the portion for determining the magnitude of numerical values in the embodiment of FIG. 2. In FIG. 3, the input signal from the left side is the signal from FIG. 2, and is given the same reference numeral as in FIG. 2, and the explanation thereof will be omitted. In the figure, 29-38 are inverters, 39-43 are 2-input NAND gates, 44-49 are 3-input NAND gates, and 50 and 51 are 4-input NAND gates. When the signal line 28 becomes "1", the inverter 33 causes the signal line 52 to become "0", which means that both data are zero and equal. 9′,
10' is a code signal of data a and b from the flip-flops 9 and 10, and when the signs of data a and b are equal, "1" is obtained from the output of the NAND gate 41. Further, when the signs of data a and b are both positive, "1" is obtained from the output of the inverter 31. Furthermore, when the signs of data a and b are both negative, "1" is obtained from the output of the inverter 32. The NAND gate 50 has an effective digit in which at least one of both data is not zero (that is, the input 28 is "0" and the inverter 33 is "1") and the signs are equal (the output of the NAND gate 41 is "1"). The output is "0" only when the numbers are equal (ie, when input 18 is "1") and the first non-zero digit is also equal (ie, when input 24 is "1"). Therefore, when "0" is output from the NAND gate 50, it means that data a and b are equal. When the signal line 52 is "0", it means that the magnitude of the numerical value cannot be determined within the scope of this embodiment and must be determined by subtracting both data. The NAND gate 42 operates when the respective data have different signs (i.e., when the output of the NAND gate 41 is "0" and becomes "1" by the inverter 36) and when the sign of the data a is positive (i.e., the input 9 ' is "1"), its output becomes "0". Therefore, when "0" is output from this NAND gate 42, it means that data a is large. NAND gates 44 to 47 are gates for determining the magnitude when the sign is positive, and all gates output "0" when data a is large.
If both data a and b are positive, the inverter 31
output is “1” and the effective number of digits is not equal (i.e.,
When input 18 is “0”, it becomes “1” by inverter 35.
) When data a has a longer effective number of digits (that is, when input 19 is "0" and becomes "1" by inverter 34), the output of gate 44 is "0"
becomes. Also, the effective number of digits is equal (i.e., when input 18 is "1"), but the first non-zero digit value is data a
is larger (that is, when the input 23 is "1"), the output of the gate 45 becomes "0". Both data are
If both are negative, the output of the inverter 32 is “1”
The effective number of digits is not equal (i.e., when input 18 is "0" and becomes "1" by inverter 35)
The number of execution digits is longer for data b (i.e. input 19
is "1"), the output of the gate 46 becomes "0". Furthermore, the signs of both data are the same (i.e. input 1
8) is "1"), but if the first non-zero digit value is larger in data b (that is, when input 25 is "1"), the output of gate 47 becomes "0" and data a is large. In this way, when data a is large, gates 42, 44, 45, 4
The output of either 6 or 47 becomes "0". Therefore, when the data a is large, the output of the gate 43 is set to "1"; otherwise, the output of the gate 43 is set to "0". Further, if both data are equal, the signal line 52 is "1", and if both data are not zero, the signal line 53 is "1". Therefore, if the data a is large, the signal line 54, which is the output of the gate 48, becomes "0". When the data b is large, the output of the gate 43 is "0", the inverter 39 changes it to "1", and the signal line 55 of the gate 49 becomes "0". The operation of the embodiment shown in Table 1 above will be explained with reference to FIG. 3.Inputs 9' and 10' in FIG. 0", input 19 is "1", input 23 is "0", and input 25 is "1". Therefore, gate 50,
"0" is never output from any one of 42, 44, 45, 46, and 47. Therefore,
Since the output "0" from the gate 43 is changed to "1" by the inverter 38 and is input to the gate 49, and the signal lines 52 and 53 are also "1", the output "0" from the gate 49 is input to the signal line 55. is output to. Therefore, in Table 1, data b is data a
is determined to be larger than . FIG. 4 shows a specific example of the area around the leading zero counter 11. In the figure, the same parts as in FIG. 2 are designated by the same reference numerals. In the figure, I is an inverter, 6
4-66 are 2-input NAND gates, 62 and 63 are 3-input NAND gates.
Input NAND gates 56 to 61 are 4-input NAND gates. 67 is a well-known binary adder;
9 is a register which receives the output 70 of the adder 67 as an input. 68 is a 1-bit register written simultaneously with register 69. 56 to 59 are zero detectors. Data input from main memory 2 via data bus 3 is input to NAND gates 56-59 via inverter I, and the contents of the data are examined. If the upper 4 bits are all “0”
If so, the output of the NAND gate 56 becomes "0". Similarly, the NAND gate 57 is the second 4
The NAND gate 58 checks the 4th bit for zero, and the NAND gate 59 checks the 4th bit for zero, and when the corresponding 4 bits are zero,
The output is set to "0". This nand gate 56
The output signal of ~59 is used to decode the number of leading zeros on bus 3 using gates 60-66. With this decoding circuit, if the first digit is zero, it will be "000", if the last digit is zero and the second digit is zero, it will be "001", if the first two digits are zero and the third digit is zero, it will be "001". If the upper three digits are zero and the fourth digit is not zero, then "011" is output, and if all the digits are zero, "100" are output to the signal lines 74 to 76. Registers 68 and 69 are initialized to zero prior to each data read. register 6
8 and 69 are controlled so that writing is performed by a data capture signal when the output signal 72 of 68 is "0". As a result, the contents of the register 69 are accumulated by the number of leading zeros by the adder 67, and when a non-zero number appears, the output of the NAND gate 60 becomes "1", and "1" is written in the register 68. Signal line 72 is “1”
As a result, the register 69 is not rewritten and holds the cumulative value of leading zero. Signal lines 75 and 76 are used as selection signals for data selector 20. When the value is "00", the segment 77 of the data selector 20 is selected and the first 4 bits are output, and when the value is "01", the segment 78 is selected and the second 4 bits are output, and the same is true. When it is "10", the segment 78 is selected and the third four bits are output, and when it is "11", the fourth four bits are selected and output to the signal line 82. The one-digit (4-bit) data selected by the data selector 20 is data a.
While data is being fetched, data b is also stored in the register 21.
is written to the register 22 while the data is being fetched. For both registers 21 and 22, when the output 72 of the register 68 becomes "1" when each data is taken in, writing of data to the corresponding register is prohibited, so that the highest non-zero value of the respective data is stored in the registers 21 and 22. The digit is memorized. Therefore,
At the end of reading each data from the main memory device 2, the number of leading zeros is created in the register 69, and a value is created in the register 21 or 22 for the most significant non-zero digit. As described in detail above, according to the present invention, it is possible to provide a data comparison device that can efficiently compare the magnitude of numerical values without performing subtraction processing, except when the value of the comparand is specific.

[Brief explanation of the drawing]

The figures show one embodiment of the present invention, in which Fig. 1 is a block diagram showing the relationship between a data processing device and data, Fig. 2 is a block diagram showing the circuit configuration of the main part, and Fig. 3 is a block diagram showing the relationship between the data processing device and data. FIG. 4 is a block diagram illustrating a circuit configuration for performing the above-described circuit configuration. 1...Data processing device, 2...Main storage device, 3
...Bus, 4, 5, 6, 7, 14, 15, 21,
22...Register, 8...Reader, 9,10...
Flip-flop, 11... Leading zero counter, 12, 16... Subtractor, 13... Adder, 17... Decoder, 20... Data selector, 26... Data comparator.

Claims (1)

[Claims] 1. For each of the two numerical data to be compared, an invalid digit number calculation means for calculating the number of invalid zero digits as a numerical value consecutively included from the most significant digit, and for each of the two numerical data,
an actual number of digits calculation means for calculating the actual number of digits of data excluding the number of invalid digits calculated by the number of invalid digits calculation means; and an actual number of digits of the two numerical data calculated by the actual number of digits calculation means. A first determining means for determining the magnitude of the two numerical data by comparing the two numerical data excluding the number of invalid digits calculated by the number of invalid digits calculating means starting from the higher digits. a second determining means for determining the magnitude of the two numerical data;
and third determining means for obtaining magnitude determination result information of the two numerical data from the data of the determination results by the first and second determining means.