JPS6318776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data buffer device provided on a data transfer path, and more particularly to a data buffer device with improved malfunction detection function of buffer control logic.

When transferring data between two devices that use different transfer methods and have different transfer speeds,
Data buffer devices are commonly used. A data buffer device generally includes a storage element that temporarily stores transferred data, and a first address and a memory element that designates the storage location of received data.
It is provided with a pointer, a second address pointer that specifies the read position of the transmitted data, a data counter that indicates the amount of data stored in the buffer, and the like. Furthermore, a malfunction detection circuit for guaranteeing the validity of transferred data is also an important component.

Although it is widely known that a parity check is a conventional method for detecting malfunctions, when we focus on the address pointers and data counters mentioned above, malfunctions other than incorrect parity, such as address pointer and data counter trigger signal malfunction, address
It has the disadvantage that it is difficult to detect malfunctions due to abnormalities in control logic, such as malfunctions of pointer selection signals, and it is necessary to take considerations other than parity checks for each address pointer and data counter. It is.

SUMMARY OF THE INVENTION An object of the present invention has been made to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide a data buffer device in which the malfunction detection function of the buffer control logic is greatly improved.

In the case of a data buffer device as described above, which is equipped with a storage address pointer, a read address pointer, and a data counter, these three
There is a latent mutual relationship between them. That is, there is a correlation in that the difference between the storage address pointer and the read address pointer is equal to the content of the data counter representing the amount of stored data.

This correlation is used to detect malfunctions in the buffer control logic, and predetermined calculations and
The above-mentioned object of the present invention can be achieved by equipping the data buffer device with an arithmetic unit having a collation function.

A channel data buffer device which is an embodiment of the present invention will be described below.

A channel data buffer device is provided between a main storage device and an input/output device, and serves to absorb differences in transfer methods and transfer speeds between the two devices. For convenience of explanation,
Data is transferred between the channel data buffer device and the main storage device in units of 32 bytes (called 1 block).
It is assumed that data is transferred between the buffer device and the input/output device in units of 1 byte.

Furthermore, there are the following three types of data transfer for input/output operations.

(1) WRITE Transfers data to the input/output device in ascending order from the specified address location in the main memory.

(2) READ Stores the data received from the input/output device in the main memory in ascending order from the specified address position.

(3) READ/BACK (reverse reading) Stores the data received from the input/output device in the main memory in descending order from the specified address position.

FIG. 1 schematically shows the process of updating the contents of the address pointer and data counter in the data buffer device during a WRITE operation.

Data buffer (CBS) 10 is a storage unit having a maximum storage capacity of 256 bytes and is made up of eight consecutive addressed blocks. The block address register (BLAR) 20 receives one from main memory.
When storing block data in CBS10, it is used as a pointer to specify the block position.
When the storage operation for CBS10 is completed, it is incremented by 1. Byte address register (BAR) 2
2 sends 1 byte of data to the input/output device.
When reading from the CBS 10, it is used as a pointer to specify the byte position, and is incremented by 1 when the reading operation from the CBS 10 is completed. The data block counter (DBC) 24 is a counter that represents the amount of data stored in the CBS 10 in block numbers, and is incremented by 1 when the BLAR 20 is updated.
When the lower 5 bits after updating of 22 become all "0", that is, when the read operation of the final data in one block is completed, it is decremented by 1.

To explain the update status of the contents of the above two registers and counters using the data transfer shown in the shaded area as an example, at the start of input/output operation, DBC2
4. All bits of BLAR20 and upper 3 bits of BAR22 (corresponding to block address)
is set to “0”, and the lower 5 of BAR22
The bits are initialized by the lower five bits of the data transfer start address. Next, the data of the first block is received from the main memory, and the CBS10
When storage is completed, DBC24 and BLAR20
is incremented by +1 to enter state A, and data transfer with the input/output device is started. DBC2
4 and BLAR20 remain in state A, data transfer between them and the input/output device continues, and BAR
22 crosses the block boundary, that is, the read operation of the final data of the first block is completed.
When BAR22 becomes “00100000”, DBC2
4 is incremented by -1 and transitions to state B. In state B, when the second block of data is received from the main memory, the contents of DBC24 and BLAR20 are updated, and the state changes to state C. When the data transfer with the input/output device progresses, state Transition to D,
Continue until the end of data transfer.

On the other hand, in state A, if a second block of data is received from the main memory until the transfer of one block of data to the input/output device is completed,
The contents of DBC 24 and BLAR 20 are again incremented by +1, and a transition is made to state E. Then, when the data transfer with the input/output device progresses and the BAR 22 crosses a block boundary, the contents of the DBC 24 are updated and the state changes to state F and then to state D.

In this example, the amount of data transferred is reduced for convenience of explanation, but the following correlation is recognized to hold true in any case.

(1) BAR22 (upper 3 bits) + DBC24 = BLAR20 FIG. 2 shows an outline of the READ operation.

During READ operation, BLAR20 transfers one block of data to the main memory to CBS10.
It is used as a pointer to specify the block position when reading from the main memory, and is incremented by 1 when the transfer operation with the main memory is completed. The BAR 22 is used as a pointer to specify the byte position when storing 1 byte of data received from the input/output device in the CBS 10, and is incremented by 1 when the storage operation for the CBS 10 is completed. The DBC24 is a counter that represents the amount of data to be transferred from the CBS10 to the main storage device in blocks, and is decremented by 1 when the content of the BLAR20 is updated, and the lower 5 bits of the BAR22 are all set to "0" after the content is updated (1 When the storage of the last data in the block is completed) or when the last data is received from the input/output device and the storage operation for the CBS 10 is completed, it is incremented by 1.

To explain these update situations using the data transfer shown in the shaded area as an example, at the start of an input/output operation, initial settings similar to those for a WRITE operation are made. Subsequently, data transfer with the input/output device is started. When the data transfer with the input/output device progresses and the data is stored in the final data position of the first block, the BAR22 becomes “00100000”.
When the block boundary is crossed, the contents of the DBC 24 are incremented by 1 and the state changes to state A. At this point, data transfer of the first block with the main storage device is started, and when this data transfer is completed, the contents of BLAR20 are incremented by +1, the contents of DBC24 are incremented by -1, and a transition is made to state B. continue,
As the data transfer between the input and output device progresses, the state changes to state C, and when the last data is stored in the final data position of the second block and the content of BAR22 becomes "01000000", the content of DBC24 is updated. and transitions to state D. The data transfer of the second block to and from the main memory is now started again, and when this data transfer is finished, the BLAR
The contents of 20 and DBC24 are updated and state E
The READ operation ends.

On the other hand, at the time of state A, data transfer with the input/output device is progressing until the data transfer with the main storage device is completed, and the final data is stored in the final data position of the second block. , BAR2
When the contents of DBC 24 become "01000000", the contents of DBC 24 are updated and the state changes to state F. here,
When the data transfer of the first block to and from the main storage device is completed, the contents of BLAR20 and DBC24 are updated to state D, and then when the data transfer of the second block is completed, state E is entered. The READ operation ends.

What has been described so far is a case where data transfer between the input and output devices is completed by storing the data at the final data position within one block.

Next, consider the case where data transfer with the input/output device is terminated in the middle of one block. When the last data is received from the input/output device in the middle of one block, it is necessary to transfer the data stored in the CBS 10 up to the middle to the main memory, and the contents of the DBC 24 are incremented by +1. However, the updated BAR 22 does not cross the block boundary and the top three bits do not change. Therefore, compared to the case where data transfer with the input/output device ends at the last byte position of one block, the difference is that the upper three bits of BAR 22 are reduced by 1.

In this example, the amount of data transferred is set to be small for the convenience of explanation, but from what was explained earlier, it is recognized that the following two interrelationships are established in the READ operation. Then, at the end of data transfer with the input/output device,
It is also recognized that identification can be made by referring to the contents of BAR22. More specifically,
Is data transfer with the input/output device complete?
Alternatively, if the contents of BAR22 indicate a block boundary (lower 5 bits are all "0"), (1) BAR22 (upper 3 bits) - BCD24 = BLAR20 is also used for data transfer with the input/output device. has finished and BAR22 does not indicate a block boundary, (2) BAR22 (upper 3 bits) - DBC24 = BLA20 -
1 is established.

FIG. 3 shows an outline of the READ/BACK operation.

The difference in buffer control between READ operation and READ/BACK operation is that when data received from an input/output device is stored in CBS10, in the former case, the block address increases sequentially from 000, and in the latter case, the block address increases sequentially from 000. The first is that the block addresses are stored in descending order from 111. Therefore,
All bits of BLAR20 and the upper 3 bits of BAR22 are initially set to “1”;
It is the same as the READ operation, except that the contents of BLAR20 and BAR22 are updated by -1, and when BAR22 crosses a block boundary, all of the lower 5 bits become "1". .

Taking the data transfer shown in the shaded area as an example, the update status of the contents of each register and counter will be explained as follows.
At the start of input/output operation, all bits of BLAR20 and the upper 3 bits of BAR22 are set to “1”.
The lower 5 bits of BAR22 are initialized to the lower 5 bits of the data transfer start address, and all bits of DBC24 are initialized to "0". Subsequently, data transfer with the input/output device is started. As the data transfer with the input/output device progresses, the data is stored in the final data position of the first block (block address 111), the contents of BAR22 becomes "11011111", and when the block boundary is crossed,
The contents of DBC24 are incremented by 1 and the state changes to state A. At this point, the first
Data transfer of the block starts, and when this data transfer is completed, the contents of BLAR 20 and DBC 24 are incremented by 1, and a transition is made to state B. Then, when data transfer between the input and output devices progresses, state C is reached.
Then, the final data is stored in the final data position of the second block, and a transition is made to state D.
Here, the data transfer of the second block with the main storage device is started again, and when this data transfer is finished, the contents of BLAR20 and DBC24 are updated to state E, and the READ/BACK operation ends. .

On the other hand, at the time of state A, the data transfer with the input/output device is progressing until the data transfer with the main memory is completed, and the last data is stored in the final data position of the second block. and BAR
When the content of 22 becomes “10111111”, DBC24
The contents of are updated and the state transitions to state F. When the data transfer of the first block to and from the main storage device is completed, the contents of BLAR20 and DBC24 are updated to state D, and then when the data transfer of the second block is completed, state E is entered. Then, the READ/BACK operation ends.

What has been described so far is the case where the data transfer between the input and output devices ends after storing the data at the final data position within one block.

Next, as in the case of READ operation, if we consider the case where the data transfer with the input/output device ends in the middle of one block, the data transfer with the input/output device ends at the final data position of one block. The difference is that the content of the upper 3 bits of BAR 22 is increased by 1 compared to when the process is completed.

In this example, the amount of data transferred is reduced for convenience of explanation, but from the above, in READ/BACK operations,
It is recognized that the following two mutual relationships are established. It is also recognized that identification can be made by referring to the contents of the BAR 22 at the end of data transfer with the input/output device. More specifically, if the data transfer with the input/output device has not been completed or if the BAR22 indicates a block boundary (lower 5 bits are all "1"), (1) BAR22 (upper 3 bits) + DBC24 = BLAR20, and if the data transfer with the input/output device has finished and BAR22 does not indicate a block boundary, (2) BAR22 (upper 3 bits) )+DBC24=BLAR20+
1 is established.

The above is a complete overview of the interrelationships that exist between each address register and data counter in a channel data buffer device.

Figure 4 shows BLAR20, BAR22 and
A block diagram of a matching circuit for examining the correlation between the contents of DBC 24 is shown.

The operations of BLAR 20, BAR 22 and DBC 24 are as described above. The arithmetic unit 26 is connected to the line 4
1 from BAR 22 and DBC 24 via line 43.
It receives the data block count from the buffer controller 32 and performs addition and subtraction on both by referring to the input/output operation identification signal supported via the line 53. More specifically, in the WRITE operation and READ/BACK operation, BAR22 (upper 3 bits) + DBC24 is calculated, and in the READ operation, BAR22 (higher 3 bits) - DBC24 is calculated. The result of the calculation is provided to the comparator 30 via line 45.

Further, the computing unit 28 connects BLAR via a line 47.
20, the buffer controller 32 receives the block address by referring to the input/output operation identification signal supported via the line 53 and the data transfer status indication signal supported via the line 55. +1/+0/-1 calculations are performed for . More specifically, in a READ operation, if the data transfer between the input and output devices ends in the middle of one block, BLAR20-1, and also in READ/BACK operations, If the data transfer between the two blocks ends in the middle of one block, BLAR20+1 is calculated, and in other cases, BLAR20+0 is calculated. The result of the calculation is provided to the comparator 30 via line 49.

The comparator 30 includes the arithmetic unit 26 and the arithmetic unit 2.
8 and sends the comparison result to the buffer control section 32 via a line 51. By referring to the matching results, the buffer control unit 32
Malfunction of any one of BLAR 20, BAR 20 and DBC 24 can be detected.

As is clear from the foregoing description, the data buffer device constructed according to the present invention performs , it becomes possible to detect failures in each address pointer and data counter themselves, or failures in the control logic surrounding these, which has a significant effect on improving the reliability of transferred data.

[Brief explanation of the drawing]

Figure 1 shows BLAR2 in WRITE operation.
0, BAR22 and DBC24 state transition diagram, Figure 2 shows BLAR20 and BAR2 in READ operation.
2 and DBC24 state transition diagram, Figure 3 is
BLAR20, BAR in READ/BACK operation
22 and DBC24 transition diagram, Figure 4 is BLAR
20, a block diagram of a correlation checking circuit between three parties, BAR 22 and DBC 24. 10: Data buffer (CBS), 20: Block address register (BLAR), 22: Buffer address register (BAR), 24: Data block counter (DBC), 26,2
8: Arithmetic unit, 30: Comparator, 32: Buffer control unit.

Claims (1)

[Claims] 1. In a data buffer device installed in the middle of a data transfer path connecting two devices, a first pointer designating the storage location of data received from one device and a pointer for sending data to the other device. A second pointer that specifies the data read position, a counter that indicates the amount of stored data, and the number of data determined from the contents of the first and second pointers matches the number of data held by the counter. 1. A data buffer device comprising means for checking whether or not the numbers match, and outputting a signal indicating the occurrence of a malfunction when they do not match.