JPS6221278B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an insulated gate field effect transistor.

InP field-effect transistors (hereinafter abbreviated as FETs) take advantage of InP's characteristics of high electron mobility and high electron saturation drift speed, and GaAs
It can be expected to be faster than the FET. There are various types of FETs, but among them, insulated gate FETs are superior in terms of fabrication and use, such as their simple structure and large logic amplitude. Furthermore, in this structure, there is no strong Fermi-level sticking phenomenon at the InP-insulating film interface, as there is at the GaAs-insulating film interface.
This structure can be said to be optimal for InP. However, conventionally, InP insulated gate type, which operates stably,
FET had not been realized. The main reason for this is that a technology for forming an insulating film with excellent electrical properties at the interface with InP has not been established. The insulating films conventionally used are mainly CVD
(Chemical _{Vapor Deposition} ) _method . In forming these films, temperatures of 300° C. or higher are required in order to form films that do not contain chemically unstable unreacted substances. Therefore, during the formation of these films, the thermally unstable InP crystal is exposed to high temperatures of 300°C or more, and as a result, the surface of the InP crystal has
Defects such as P (phosphorus) vacancies are introduced. These defects lead to a decrease in the electrical properties of the interface, such as an increase in the density of interface states, which causes instability in FET operation. On the other hand, anodic oxidation is the only method that can form an insulating film at room temperature. Anodic oxidation of InP has been studied for a long time, but basic issues such as the correlation between oxidation conditions and electrical properties of the interface have not been clarified.
A high-quality oxide film that can be used as a gate insulating film has not been obtained.

The present invention was realized as a result of establishing the manufacturing conditions for high-quality oxide films through detailed research on the correlation between the manufacturing conditions for InP anodic oxide films and the interfacial electrical properties.The present invention aims to achieve high speed and stable operation. Our objective is to provide an InP insulated gate FET with excellent performance.

A detailed study of the correlation between the fabrication conditions of the InP anodic oxide film and the electrical properties of the interface revealed the following.

(i) The following three types of electrolytes for anodizing InP are known.

(A) Aqueous solutions of acids and bases, (B) a strong oxidizing agent dissolved in a non-aqueous solution; (C) A mixture of an aqueous solution and a non-aqueous solution of an acid or base.

Among these, (C) is the most excellent in terms of oxide film stability, film growth stability, and reproducibility.

(ii) When the electrolyte (C) is used, the composition of the oxide film differs depending on the pH of the electrolyte. That is, the oxide film is composed of In ₂ O ₃ and P ₂ O ₅ , and as the pH increases, the amount of In ₂ O ₃ increases and the amount of P ₂ O ₅ decreases. At 5〓PH〓7, an oxide film containing almost equal amounts of In ₂ O ₃ and P ₂ O ₅ grows. below PH5
In an oxide film containing excess P ₂ O ₅ , the electrical characteristics of the oxide film itself become unstable due to the hygroscopicity of P ₂ O ₅ . On the other hand, in an excessive In ₂ O ₃ oxide film exceeding pH 7,
A reaction between In ₂ O ₃ and InP is likely to occur during heat treatment, which causes deterioration of the electrical properties at the interface between the oxide film and the InP crystal. As a result, at PH=5-7
An oxide film containing approximately equal amounts of In ₂ O ₃ and P ₂ O ₅ is the best.

(iii) Heat treatment is essential to remove moisture in the oxide film, and the heat treatment temperature for this is 150~150℃.
250℃ is optimal. Heat treatment at 300℃ or higher is (ii)
It significantly promotes the reaction between In ₂ O and InP mentioned in .

As a result, an anodic oxide film formed using a mixture of an acid aqueous solution or base aqueous solution adjusted to a pH of 5 to 7 and a non-aqueous solution was heated at 150 to 250°C for 5 to 20 minutes.
It has become clear that the best interfacial electrical properties can be achieved when heat-treated for a minute. Suitable acids include organic acids such as tartaric acid and oxalic acid, inorganic acids such as phosphoric acid and boric acid, bases include sodium hydroxide and potassium hydroxide, and non-aqueous solutions include ethylene glycol and propylene glycol, which are water-soakable and have an appropriate viscosity. It is.

Based on the above research results, the results of manufacturing an InP insulated gate FET will be explained using examples.

FIG. 1 is a cross-sectional view of a p-channel inverted FET fabricated using n-type InP crystal. 1 is n type
InP crystal, 2 is source region, 3 is drain region, 4
is an InP anodic oxide film which is a gate insulating film, 5 is an ohmic source electrode, 6 is an ohmic drain electrode,
7 is a gate electrode, and 8 is an ohmic electrode of the n-type InP crystal 1. To manufacture such an insulated gate FET, an n-type InP crystal having a carrier concentration of about 10 ¹⁶ cm ^-3 is used, which is manufactured by a known liquid capsule pulling method. On the surface of the mirror-polished n-type InP crystal 1,
P-type source and drain regions 2 and 3 are formed by selective thermal diffusion of zinc. Next, Au-Zn was applied to part of the surfaces of the source and drain regions 2 and 3, and n-type InP
Au-Sn is vacuum-deposited on a portion of the back surface of the crystal 1, and ohmic electrodes 5, 6, and 8 are formed by heat treatment at 400° C. for 1 minute in nitrogen gas. Next, InP excluding the area of ohmic electrodes 5 and 6
The surface of crystal 1 was anodized in a 1:3 mixture of 3% tartaric acid aqueous solution and propylene glycol adjusted to pH = 6, and a current density of 1 mA/m was applied using platinum as a counter electrode.
Anodic oxidation is performed at cm ² for 3 minutes to form an anodic oxide film 4 with a thickness of about 2500 Å. Subsequently, in nitrogen gas, 200
Heat treatment at 10°C for 10 minutes. Finally, the gate electrode 7 is formed by vacuum evaporation of Au, and the fabrication of the FET is completed. Insulated gate FET fabricated in this way
, n determined from the capacitance-voltage characteristics of the M (metal)-I (insulating film)-S (semiconductor) diode formed between the gate electrode 7 and the n-type InP crystal 1.
FIG. 2 shows the surface state density distribution of InP crystal 1. Here, a is for the present invention, b is for the conventional anodic oxide film, c is for the SiO ₂ film made by the conventional CVD method, and d is the surface level for the Al ₂ O ₃ film made by the conventional CVD method. This is the position density distribution. This result shows that in the case of the present invention, the surface state density is the lowest and an extremely clean interface is formed. next,
When the drain electrode 6 is negatively biased with respect to the source electrode 5 and the gate electrode 7 is further negatively biased with respect to the source electrode 5, the current between the source and drain increases as the gate bias increases. So-called inverted FET operation was confirmed. Conventionally, p-channel inverted FET in InP
was thought to be extremely difficult to achieve. In the case of the present invention, the p-channel inverted FET was realized because, as shown in FIG. 2, a high-quality insulating film with extremely low surface state density could be formed.

Next, we will discuss the results of fabricating an n-channel inverted FET using p-type InP crystal. Third
The figure is a cross-sectional view of an n-channel inverted FET.
9 is a p-type InP crystal, 10 is a source region, 11 is a drain region, 12 is a gate insulating film, 13 is an ohmic source electrode, 14 is an ohmic drain electrode, 1
5 is a gate electrode. The manufacturing process for such an FET is as follows. N-type source and drain regions 1 are formed on the surface of a mirror-polished P-type InP crystal 9 with a carrier concentration of approximately 10 ¹⁶ cm ^-3 by selective thermal diffusion of sulfur.
0,11 are formed. source, drain region 10,
Au--Sn is vacuum-deposited on a part of the surface of 11, and heat-treated at 400° C. for 1 minute in nitrogen gas to form ohmic electrodes 13 and 14. Next, a gate insulating film 12 and a gate electrode 15 are formed in the same manner as in the case of the P-channel FET shown in FIG. 1, thereby completing the fabrication of the FET. In the device manufactured in this manner, the drain electrode 14 is positively biased with respect to the source electrode 13, and the source electrode 14 is biased positively with respect to the source electrode 13.
By positively biasing the gate electrode 15 with respect to 3, an inversion type FET operation was confirmed.
In this case, the conventional n-channel inverted FET
The source-drain current drift phenomenon observed in the previous model was not observed at all, and extremely stable operation was achieved. In addition, as for the mutual conductance, which is an important figure of merit for FET, the gate length is 5 μm.
In the case of , 180mS/mm was obtained. This value is the traditional
This is more than twice the value for FET.

The above results are for an inverted insulated gate FET, but an n-type FET on a semi-insulating InP substrate crystal
It is clear that even in the case of a depletion type insulated gate FET that uses an InP crystal film as a channel, excellent characteristics can be obtained by using an anodic oxide film with excellent interface characteristics.

As explained above, the InP insulated gate FET of the present invention uses an anodic oxide film with excellent interfacial properties as the gate insulating film, so it has extremely stable operation and excellent high speed. There is an advantage.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a p-channel inverted FET.
FIG. 2 is a diagram showing the measurement results of the surface state density distribution at the interface between n-type InP and an insulating film, and FIG. 3 is a cross-sectional view of an n-channel inversion type FET. DESCRIPTION OF SYMBOLS 1...n-type InP crystal, 2...source region, 3...drain region, 4...gate insulating film, 5...source electrode, 6
... Drain electrode, 7... Gate electrode, 8... Ohmic electrode of n-type InP crystal 1, 9... P-type InP crystal, 10...
Source region, 11... Drain region, 12... Gate insulating film, 13... Source electrode, 14... Drain electrode, 1
5...Gate electrode.

Claims (1)

[Claims] 1. An anodic oxide film of InP formed in a mixture of an acid aqueous solution or base aqueous solution whose pH is adjusted to a range of 5 to 7 and a non-aqueous solution is heated at 150 to 250°C in hydrogen or an inert gas for 50 minutes. It is characterized by being heat treated for ~20 minutes and used as a gate insulating film.
A method for manufacturing InP insulated gate field effect transistors.