JPS6336537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that employs a virtual storage method.

In conventional information processing devices that employ virtual memory, the main memory (hereinafter referred to as main memory)
An update bit is provided in the memory and other storage devices (hereinafter referred to as memory), and when data is stored in these memories, the update bit is set to "1" to indicate that rewriting has been performed. In this case, if the update bit is in main memory, performance will decrease due to increased access to main memory when updating the update bit, and if the update bit is in another memory, the update of the update bit will It has the disadvantage that it requires the use of expensive memory because it needs to be performed at high speed.

Another method to compensate for the above disadvantages is to store a copy of the updated bits in an address translation buffer (hereinafter referred to as TLB), but each time an index error occurs in the TLB, the main memory or another memory is accessed. Since it is necessary to take out the updated bits, there is a drawback that performance degradation due to increased access to the memory remains.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that eliminates the above-mentioned drawbacks by unconditionally registering update bits as unupdated display without memory access when a read access index error occurs in an address translation buffer.

The apparatus of the present invention has a storage area of the main storage means divided into a plurality of pages, and has update bit holding means for holding true update bits corresponding to each page to display the update status of the stored contents. In an information processing device in which a copy of a true update bit is held in an address translation buffer that performs translation between a logical address and a physical address, when an index error occurs in the address translation buffer when accessing the main storage means; physical address registration means for registering a new physical address in an address translation buffer; and a copy of the true update bit corresponding to the new physical address at the time of registration by the physical address registration means in response to a read access. unupdated display registration means that registers the unupdated display in the address translation buffer regardless of the value of the update bit holding means that holds the updated bit; a change registration means for changing and registering a copy of the true update bit of the address translation buffer entry as an update display when an entry whose update bit copy indicates not updated is indexed; and change registration by the change registration means; and updated setting means for setting the true update bit to updated.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, access request source interface 1
When a memory access type flag and a memory access address are sent from the memory access type flag, if the memory access type flag indicates read (reading), read flag flip-flop 2 (hereinafter abbreviated as R flag) is set and store is performed. If it indicates (storage), store flag flip-flop 3 (hereinafter abbreviated as S flag) is set. At the same time, the memory access address is set in register 4 to complete the TLB index preparation. Next, the TLB is indexed, and the TLB structure and indexing method are known (Japanese Patent Publication No. 57-23952 and Japanese Patent Publication No. 57-23952).
25920, etc.), the details are omitted and only the parts related to the present invention will be explained.

The TLB is determined by the lower part (LEA) of the logical page address part of the logical address set in register 4.
5 and TLB6 at the same time, and the upper part (LPA0 and LPA1) of the logical page address part of the entry read from TLB5 and TLB6,
Comparators 7 and 8 compare the upper part (LPA) of the logical page address section of the register 4, respectively, and report the comparison results to the address conversion control section 9 via signal lines 100 and 101. When the address conversion control unit 9 detects a mismatch in the comparison result, that is, a TLB index error, the address conversion control unit 9 converts the data into the main memory (not shown) based on the logical page address part (LPA and LEA) of the register 4 given via signal lines 102 and 103. The main memory access control unit 10 is accessed via the signal line 104 to read the address conversion table in
At the same time as setting in TLB registration register 11,
If the R flag 2 is "1" (read instruction), "0" is set in the update bit copy registration register 12 via the signal line 106. At this time, if the S flag 3 is "1" (write instruction), the update bit copy registration register 12 is set to "1", and its contents are transferred to the replacement algorithm (information processing, Vol・21, No.4,
1980, pp. 334-335)), the contents set in the TLB registration register 11 and the update bit copy registration register 12 are registered in accordance with instructions from the address converter 9.
At this time, when the S flag 3 is "1",
A signal line 1 sends a request signal to the main memory access control unit 10 to set the update bit in the main memory to "1".
04 to ensure a match with the copies of the updated bits in TLBs 5 and 6 (C0 or C1).

Next, the case of store access when there is a hit in the TLB index will be explained.

A memory store access flag and a memory access address are set in the S flag 3 and register 4 from the access request source interface 1, and TLBs 5 and 6 are simultaneously indexed by the lower part (LEA) of the logical page address part of the register 4,
Comparing the upper part (LPA0 and LPA1) of the logical page address part of the entry read by the TLBs 5 and 6 with the upper part (LPA) of the logical page address part of the register 4 using comparators 7 and 8; This comparison result is reported to the address translation control section 9. When the comparison result matches, that is, a TLB index hit is detected, the address conversion control unit 9 converts the
Select circuit 13 for copying real page address information and update bits read from TLBs 5 and 6.
The actual page address information is selected from the TLB side that matches with the TLB side, and the real page address information is sent to the main memory access control unit 10 via the signal line 107, and the copy of the update bit given via the signal line 108 is “0”. ”, a request signal for setting the update bit to “1” is sent to the main memory access control unit 10 via the signal line 104, and at the same time, the
Copies of the update bits of TLB5 and 6 are set to “0”
In order to update the update bit, update data is set in the update bit copy registration register 12 from the address translation control unit 9 via the signal line 106, and then the copy of the update bit in TLB 5 or 6 is set in accordance with the instruction from the address translation control unit 9. is changed from "0" to "1" to guarantee matching.

That is, the update bits stored in the true update bit holding means (table in 10, not shown) provided in the main memory access control unit 10 are transferred to the main memory (not shown). In order to avoid adding processing to set the true updated bit to updated (“1”) every time a write process is performed, TLBs 5 and 6 have copies of the true updated bit and the true updated bit is Configure to reduce processing. In such a configuration, when a new page is registered in TLBs 5 and 6, the true update bit of the corresponding page is stored in the true update bit holding means (1).
0) and register it in TLBs 5 and 6 as a copy of the true update bit. However, in order to reduce the read processing of the true update bit of the corresponding page, when a page is registered in response to read access to TLBs 5 and 6, the corresponding true update bit is unconditionally regarded as "0" and registered. If the true updated bit was originally "0" due to this operation, the true updated bit is unconditionally considered to be "0", that is, the "0" prediction was successful, and the true updated bit is always "0". The read processing can be reduced compared to the case where the true update bits are read from the true update bit holding means (table in 10) and a copy is registered in the TLB.

Also, since the true update bit is unconditionally regarded as "0" and a copy is registered in the TLB, when the true update bit is "1", the value "0" of the copy of the update bit in TLB5 and 6 is different. However, at this time, since the copy update bit is "0" compared to the true update bit "1", a request is made to the true update bit holding means to update it to "1", but it was originally "1".
This is a request to update the value of ``1'' to ``1'', and no conflict occurs.

As explained above, the present invention can reduce update bit accesses by unconditionally registering a copy of updated bits with an unupdated display without memory access when a TLB umbrella error occurs during read access.
This has the effect of improving the performance of the information processing system.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the present invention, in which 1...access request source interface, 2...read access flag, 3...store access flag, 4...logical address register, 5, 6...TLB,
7, 8...Comparator, 9...Address comparison control unit, 10
...Main memory access control unit, 11, 12...TLB
Registration register, 13... selection circuit.

Claims (1)

[Scope of Claims] 1. The storage area of the main storage means is divided into a plurality of pages, and the main storage means has update bit holding means for holding true update bits corresponding to each page to display the update state of the stored contents, In an information processing device in which a copy of the true update bit is held in an address translation buffer that performs translation between a logical address and a physical address, when an index error occurs in the address translation buffer when accessing the main storage means; physical address registration means for registering a new physical address in the address conversion buffer; and a copy of the true update bit corresponding to the new physical address at the time of registration by the physical address registration means in response to the read address. unupdated display registration means for registering an unupdated display in the address conversion buffer regardless of the value of the update bit holding means that holds bits; change registration means for changing and registering a copy of the true update bit of the address translation buffer entry as an updated display when an entry in which a copy of the update bit of the address translation buffer entry indicates that it has not been updated; An information processing apparatus characterized by comprising an updated setting means for setting the true updated bit to updated in addition to registration.