JPS6360531B2 - - Google Patents
Info
- Publication number
- JPS6360531B2 JPS6360531B2 JP56075892A JP7589281A JPS6360531B2 JP S6360531 B2 JPS6360531 B2 JP S6360531B2 JP 56075892 A JP56075892 A JP 56075892A JP 7589281 A JP7589281 A JP 7589281A JP S6360531 B2 JPS6360531 B2 JP S6360531B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- semiconductor device
- grooves
- mesa
- element substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
この発明は、電気泳動法によりガラスパツシベ
ーシヨンを行う半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which glass packaging is performed by electrophoresis.
一般にメサ形半導体装置は半導体基板を切断し
て個々の装置に分解した時にPN接合面が露出す
る。この露出したPN接合面が外部から汚染され
ると半導体装置の電気的特性が損なわれて、製品
としての価値を失うために、PN接合面の露出部
を例えばシリコーン樹脂あるいはガラスなどで覆
つて保護するいわゆるパツシベーシヨンが行なわ
れている。 Generally, in a mesa-type semiconductor device, the PN junction surface is exposed when the semiconductor substrate is cut and disassembled into individual devices. If this exposed PN junction surface is contaminated from the outside, the electrical characteristics of the semiconductor device will be impaired and the value as a product will be lost. Therefore, the exposed part of the PN junction surface is protected by covering it with silicone resin or glass, for example. The so-called passivation is being carried out.
PN接合面を保護する保護材として、一般にシ
リコーン樹脂あるいはガラスが用いられている
が、同一品種の半導体装置で、シリコーン樹脂で
パツシベーシヨンしたものと、ガラスでパツシベ
ーシヨンしたものと電気的特性を比較するとガラ
スパツシベーシヨン半導体装置が優れていて、特
に高温バイアス試験では非常に高い信頼度が有
る。半導体装置の露出するPN接合面にガラスを
被着する方法としては、例えば、真空蒸着法・ド
クターブレード法・印刷法および電気泳動法等が
あるが、ガラス層は厚過ぎず薄過ぎず適当な厚さ
に、均一に被着することが必要である。特に電気
泳動法を用いる場合には、その工程上の都合から
被着するガラス層の均一性が強く要求される。即
ちメサ型半導体装置に電気泳動法によつてガラス
粉末を被着しパツシベーシヨンを行う工程につい
て説明すると、例えばトランジスタの場合、N型
シリコン基板にP型ベース層、N型エミツタ層を
順次拡散形成した後、この半導体素子基板表面に
シリコン酸化膜を1μm以上熱酸化等で形成する。
次にガラスパツシベーシヨンを行うべき部分のメ
サ溝を、ブレードマシン等を用いて、格子模様状
に形成し破砕層をエツチングで除去する。この状
態を第1図a,bに示す。半導体素子基板1に
は、単位素子であるトランジスタa11,a12……が
多数配列され、メサ溝は各トランジスタの周囲を
取り囲むように、縦溝2と横溝3により格子模様
をなしている。次に半導体基板裏面上の熱酸化膜
に電着電極取出し用穴あけを、写真蝕刻法等を用
いて行う。 Silicone resin or glass is generally used as a protective material to protect the PN bonding surface, but when comparing the electrical characteristics of semiconductor devices of the same type that are bonded with silicone resin and those that are bonded with glass, glass The passivation semiconductor device is excellent and has extremely high reliability especially in high temperature bias tests. Examples of methods for depositing glass on the exposed PN junction surface of a semiconductor device include vacuum evaporation, doctor blade method, printing, and electrophoresis. It is necessary that the coating be applied to a uniform thickness. Particularly when electrophoresis is used, uniformity of the glass layer to be deposited is strongly required due to process considerations. That is, to explain the process of applying glass powder to a mesa-type semiconductor device by electrophoresis and passivation, for example, in the case of a transistor, a P-type base layer and an N-type emitter layer are sequentially diffused and formed on an N-type silicon substrate. Thereafter, a silicon oxide film of 1 μm or more is formed on the surface of this semiconductor element substrate by thermal oxidation or the like.
Next, a blade machine or the like is used to form mesa grooves in the area where glass paving is to be performed in a lattice pattern, and the crushed layer is removed by etching. This state is shown in FIGS. 1a and 1b. A large number of unit elements transistors a 11 , a 12 . Next, holes are made in the thermal oxide film on the back surface of the semiconductor substrate for taking out electrodeposited electrodes using photolithography or the like.
こうして半導体素子基板1上にガラス粉末を被
着する準備が出来たら、この半導体素子基板1を
希フツ酸等で軽く処理し、裏面を真空チヤツクで
固定し、第2図で示すように、ガラス電着液槽4
中に、陽極5と半導体素子1の表面が対向するよ
うに所定の位置に配置する。このようにして陽極
5に直流の正の電圧、半導体素子基板1に負の電
圧を印加すると、半導体素子基板上のシリコンが
露出しているメサ溝にガラス層が被着する。メサ
溝に被着したガラスは粉末を固化した状態で機械
的強度が弱く、パツシベーシヨン膜としての電気
的特性も満足しないので、これを約700℃で10分
程度熔解して焼成する。したがつて、Al電極の
形成工程等はこのガラス焼成工程以後に行なわな
いと、Alがシリコン中に拡散していつて、半導
体装置の特性を劣化させることが予想される。 When the glass powder is ready to be deposited on the semiconductor element substrate 1, the semiconductor element substrate 1 is lightly treated with dilute hydrofluoric acid, the back side is fixed with a vacuum chuck, and the glass powder is coated on the semiconductor element substrate 1 as shown in FIG. Electrodeposition liquid tank 4
Inside, the anode 5 and the semiconductor element 1 are placed at a predetermined position so that their surfaces face each other. When a positive DC voltage is applied to the anode 5 and a negative voltage is applied to the semiconductor element substrate 1 in this manner, a glass layer is deposited on the mesa groove where silicon on the semiconductor element substrate is exposed. The glass adhered to the mesa groove is a solidified powder that has weak mechanical strength and does not satisfy the electrical properties of a passivation film, so it is melted and fired at about 700°C for about 10 minutes. Therefore, if steps such as forming an Al electrode are not performed after this glass firing step, it is expected that Al will diffuse into the silicon and deteriorate the characteristics of the semiconductor device.
以上のような理由で、ガラス焼成後にAl電極
形成の写真蝕刻法の工程等を行なわなければなら
ないから、ガラス層が半導体素子基板表面より盛
り上がつていて、その盛り上がつた高さがバラバ
ラであると、Al電極形成時に、マスクでAl上の
感光性樹脂にパターンを露光した場合、マスクと
感光性樹脂ととの隙間にバラツキが出来てしま
い、Al電極パターンがくずれて、Al電極の断線
や短絡事故が発生する。 For the reasons mentioned above, a process such as photolithography for forming Al electrodes must be performed after glass firing, so the glass layer rises above the surface of the semiconductor element substrate, and the height of the rise increases. If they are uneven, when a pattern is exposed on the photosensitive resin on the Al using a mask when forming the Al electrode, there will be variations in the gap between the mask and the photosensitive resin, the Al electrode pattern will collapse, and the Al electrode disconnection or short-circuit accidents occur.
したがつて、焼成後のガラス層の盛り上がり高
さは均一であることが望まれ、そのためには、電
着後のガラス層の高さを均一にしておくことが重
要である。焼成工程でガラスを熔解し、流動性と
表面張力でガラスの厚さが均一になる温度まで焼
成温度を上げることも考えられるが、これは半導
体装置の電気的特性が損なわれてしまうため、実
用できない。 Therefore, it is desired that the raised height of the glass layer after firing is uniform, and for this purpose, it is important to make the height of the glass layer after electrodeposition uniform. It is possible to melt the glass in the firing process and raise the firing temperature to a temperature where the thickness of the glass is uniform due to fluidity and surface tension, but this would impair the electrical characteristics of the semiconductor device and is not practical. Can not.
本発明は上記の点に鑑み、電気泳動法でメサ溝
にガラス層を電着する場合に、被着されるガラス
層の厚みを半導体素子基板内で均一にし、その後
に形成される電極配線の断線や短絡事故を確実に
防止するようにした半導体装置の製造方法を提供
するものである。 In view of the above points, the present invention makes the thickness of the deposited glass layer uniform within the semiconductor element substrate when electrodepositing the glass layer in the mesa groove by electrophoresis, and improves the thickness of the electrode wiring formed thereafter. The present invention provides a method for manufacturing a semiconductor device that reliably prevents wire breakage and short circuit accidents.
本発明者らは、ガラスを均一に被着させるた
め、電着液槽内の液を撹拌したり槽の外側から超
音波振動を与えたり種々の工夫を試みた。そして
被着したガラス層の高さを数多く測定した結果、
バラツキに規則性があることを見い出した。即ち
格子状模様のメサ溝の横溝3と縦溝2が電着時に
液中で第3図に示すように水平と垂直になるよう
に固定されたときには、第1に水平の溝と垂直の
溝でガラスの被着量がはつきりと違つており、水
平溝よりも垂直溝に被着したガラス層の高さの方
が小さい。第2の隣接した単位素子の近接した2
本の水平溝についてみると、上側の溝に比べて下
側の溝の方が、ガラス層が高い。これらの規則性
は、電着液中のガラス粉末の沈澱効果によるもの
と考えられる。 In order to uniformly deposit the glass, the inventors tried various methods such as stirring the liquid in the electrodeposition liquid tank and applying ultrasonic vibration from outside the tank. As a result of numerous measurements of the height of the deposited glass layer,
It was discovered that there is a regularity in the variation. In other words, when the horizontal grooves 3 and vertical grooves 2 of the mesa grooves in the lattice pattern are fixed in the liquid during electrodeposition so as to be horizontal and vertical as shown in FIG. The amount of glass deposited on the vertical grooves is significantly different, and the height of the glass layer deposited on the vertical grooves is smaller than that on the horizontal grooves. adjacent two of the second adjacent unit elements
Looking at the horizontal grooves of a book, the glass layer is higher in the bottom groove than in the upper groove. These regularities are considered to be due to the precipitation effect of glass powder in the electrodeposition solution.
そこで本発明は半導体素子基板を、その表面を
鉛直面内に保つて電着液中で陽極に対向させ、か
つ表面のメサ溝の縦溝と横溝の鉛直線に対する傾
斜が対称的になるように配置してガラス層の電着
を行なうことにより、上述のごときガラス層の高
さのばらつきをなくすようにしたことを特徴とし
ている。 Therefore, the present invention aims at keeping the surface of a semiconductor element substrate within a vertical plane and facing the anode in the electrodeposition solution, and also so that the vertical and horizontal grooves of the mesa grooves on the surface are symmetrically inclined with respect to the vertical line. It is characterized in that the above-mentioned variations in the height of the glass layer are eliminated by electrodepositing the glass layer.
第4図は、本発明の一実施例における、半導体
素子基板1のガラス電着液中での鉛直線(矢印)
に対する傾斜の様子を示している。第3図と異な
り、基板1に格子模様状に形成されたメサ溝の縦
溝2と横溝3を、共に鉛直線に対して45度傾けた
状態に保つている。このような状態に保つてガラ
ス電着を行つた結果、基板1表面内のガラス層の
高さのばらつきは5%以内に納まつた。そしてこ
の実施例によれば、ガラス層が均一性よく被着さ
れる結果、その後に形成するAl電極のパターニ
ングが精度よく行われ、Al電極の断線や短絡事
故が確実に防止される。 FIG. 4 shows vertical lines (arrows) on the semiconductor element substrate 1 in the glass electrodeposition solution in one embodiment of the present invention.
The figure shows the inclination relative to the Unlike FIG. 3, both the vertical grooves 2 and the horizontal grooves 3 of the mesa grooves formed in a lattice pattern on the substrate 1 are maintained at an angle of 45 degrees with respect to the vertical line. As a result of performing glass electrodeposition while maintaining such a state, the variation in the height of the glass layer within the surface of the substrate 1 was kept within 5%. According to this embodiment, as a result of the glass layer being deposited with good uniformity, the patterning of the Al electrode to be formed thereafter is carried out with high accuracy, and breakage and short-circuit accidents of the Al electrode are reliably prevented.
なお、上記実施例では、半導体素子基板を電着
液中で静止状態に保つたが、基板をその表面を鉛
直面内に保つて鉛直面内で回転させながら電着し
てもよい。これによつても電着時間と回転速度の
関係を適当に設定すれば、メサ溝の横溝と縦溝の
鉛直線に対する傾きを実質的に対称的とすること
ができ、上記実施例と同様の効果が期待できる。
この場合、基板の回転は、一方向に連続的な回転
でもよいし、所定の角度範囲での往復回転でもよ
い。 In the above embodiments, the semiconductor element substrate was kept stationary in the electrodeposition solution, but the substrate may be electrodeposited while keeping its surface within the vertical plane and rotating within the vertical plane. Even in this case, if the relationship between the electrodeposition time and the rotational speed is appropriately set, the inclinations of the horizontal grooves and vertical grooves of the mesa groove with respect to the vertical line can be made substantially symmetrical, and the same as in the above embodiment can be achieved. You can expect good results.
In this case, the substrate may be rotated continuously in one direction or reciprocated within a predetermined angular range.
以上のように本発明によれば、メサ型半導体装
置の電気泳動法によるガラスパツシベーシヨンを
均一性よく行うことができ、従つてパツシベーシ
ヨン後の電極配線の形成工程も信頼性の高いもの
となり、メサ型半導体装置の歩留り向上、特性向
上を図ることができる。 As described above, according to the present invention, glass passivation of a mesa-type semiconductor device by electrophoresis can be performed with good uniformity, and therefore, the process of forming electrode wiring after passivation can also be made highly reliable. , it is possible to improve the yield and characteristics of mesa-type semiconductor devices.
第1図a,bはメサ型半導体素子基板のガラス
パツシベーシヨンの平面図とそのA−A′断面図、
第2図は電気泳動法によるガラス層電着工程を模
式的に示す図、第3図は従来法でのガラス電着液
槽中の半導体素子基板の状態を示す図、第4図は
本発明の一実施例における、ガラス電着液槽中の
半導体素子基板の状態を示す図である。
1……半導体素子基板、2……縦溝、3……横
溝、4……ガラス電着液槽、5……陽極。
Figures 1a and 1b are a plan view of the glass packaging of the mesa-type semiconductor element substrate and its A-A' cross-sectional view;
Fig. 2 is a diagram schematically showing the glass layer electrodeposition process using the electrophoresis method, Fig. 3 is a diagram showing the state of a semiconductor element substrate in a glass electrodeposition liquid bath according to the conventional method, and Fig. 4 is a diagram showing the state of the semiconductor element substrate in the glass electrodeposition liquid bath according to the conventional method. FIG. 2 is a diagram showing the state of a semiconductor element substrate in a glass electrodeposition liquid bath in one example. DESCRIPTION OF SYMBOLS 1...Semiconductor element substrate, 2...Vertical groove, 3...Horizontal groove, 4...Glass electrodeposition liquid tank, 5...Anode.
Claims (1)
に格子模様状に形成してなる半導体素子基板を、
ガラス電着液中にその表面を陽極に対向させて配
置して前記メサ溝にガラス層を電着する工程を有
する半導体装置の製造方法において、前記半導体
素子基板を、その表面に形成された前記メサ溝の
縦溝と横溝の鉛直線に対する傾斜が対称的になる
ように前記電着液中に配置してガラス層の電着を
行うことを特徴とする半導体装置の製造方法。 2 前記ガラス電着液中の半導体素子基板を、そ
の表面のメサ溝の縦溝と横溝が鉛直線に対して45
度傾斜した状態に保持するようにした特許請求の
範囲第1項記載の半導体装置の製造方法。 3 前記ガラス電着液中の半導体素子基板を、そ
の表面を鉛直面内に保つて鉛直面内で回転させる
ことにより、その表面のメサ溝の縦溝と横溝の鉛
直線に対する傾斜を実質的に対称的になるように
した特許請求の範囲第1項記載の半導体装置の製
造方法。[Claims] 1. A semiconductor device substrate having a mesa groove formed in a lattice pattern on the surface in which a PN junction of a unit device is exposed,
A method for manufacturing a semiconductor device comprising the step of electrodepositing a glass layer in the mesa groove in a glass electrodeposition solution with its surface facing the anode, A method for manufacturing a semiconductor device, characterized in that the glass layer is electrodeposited by arranging the longitudinal grooves and the lateral grooves of the mesa groove in the electrodeposition liquid so that their inclinations with respect to the vertical line are symmetrical. 2. The semiconductor element substrate in the glass electrodeposition liquid is placed so that the vertical and horizontal grooves of the mesa grooves on the surface thereof are 45 mm with respect to the vertical line.
A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is held in a tilted state. 3. By rotating the semiconductor element substrate in the glass electrodeposition liquid within the vertical plane while keeping its surface within the vertical plane, the inclinations of the longitudinal grooves and the lateral grooves of the mesa grooves on the surface with respect to the vertical line are substantially reduced. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is symmetrical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56075892A JPS57190324A (en) | 1981-05-20 | 1981-05-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56075892A JPS57190324A (en) | 1981-05-20 | 1981-05-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57190324A JPS57190324A (en) | 1982-11-22 |
| JPS6360531B2 true JPS6360531B2 (en) | 1988-11-24 |
Family
ID=13589416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56075892A Granted JPS57190324A (en) | 1981-05-20 | 1981-05-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57190324A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282439U (en) * | 1988-08-10 | 1990-06-26 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008151407A (en) * | 2006-12-18 | 2008-07-03 | Matsushita Electric Ind Co Ltd | Ventilation equipment |
-
1981
- 1981-05-20 JP JP56075892A patent/JPS57190324A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282439U (en) * | 1988-08-10 | 1990-06-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57190324A (en) | 1982-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4622574A (en) | Semiconductor chip with recessed bond pads | |
| US3493820A (en) | Airgap isolated semiconductor device | |
| US3964157A (en) | Method of mounting semiconductor chips | |
| US3609470A (en) | Semiconductor devices with lines and electrodes which contain 2 to 3 percent silicon with the remainder aluminum | |
| JPH063837B2 (en) | Method for manufacturing three-dimensional semiconductor integrated circuit | |
| US3387360A (en) | Method of making a semiconductor device | |
| JPS6360531B2 (en) | ||
| TWI657512B (en) | Method for manufacturing semiconductor device | |
| US3642597A (en) | Semiconductor passivating process | |
| CN107533972B (en) | Manufacturing method of semiconductor device | |
| US3279963A (en) | Fabrication of semiconductor devices | |
| GB1246414A (en) | Diffusion barrier for semiconductor contacts | |
| JPS5951533A (en) | Manufacture of semiconductor device | |
| JPH03204953A (en) | Semiconductor device | |
| JP2643001B2 (en) | Method for manufacturing semiconductor device | |
| JPH0376586B2 (en) | ||
| JP2025090162A (en) | Semiconductor device and its manufacturing method | |
| JPH06283815A (en) | Solid state laser device | |
| JPH0526770Y2 (en) | ||
| JPS5984431A (en) | Manufacture of semiconductor device | |
| JPS63141370A (en) | Manufacture of thyristor | |
| JPH0262944B2 (en) | ||
| JPH0824187B2 (en) | Preventing electrostatic damage to semiconductor devices | |
| JPS5836495B2 (en) | Manufacturing method of semiconductor device | |
| JPH0194640A (en) | Semiconductor device and manufacture thereof |