JPS636958B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention performs a time axis compression or expansion operation.
This article relates to a method for driving a CCD variable delay line.

A CCD (electronic transfer device) is an analog memory that can delay analog signals, and can compress or expand the time axis by controlling the transfer clock frequency.

Conventionally, as a driving method for performing such an operation, the pulse supplied to the transfer gate for transferring charge from the input section to the transfer channel is common to the charge transfer pulse, and its width changes with the clock frequency. Such a mode was common. Therefore, as the clock frequency changes, the amplitude of the analog signal at the output section changes, resulting in fluctuations in the gain of the signal transmission system. This phenomenon will be explained below. 1st
The figure shows a cross-sectional view of the structure of the CCD input section and its vicinity, and the potential distribution under each electrode. CCD
are formed on the p-type semiconductor substrate 11, and φt, φ ₁ ,
It has a structure including a transfer electrode of φ ₂ , an input gate of G ₁ to which a sampling pulse is supplied, a DC bias gate of G ₂ , and an input diode 12 to which an analog signal is applied. This configuration is shown as an example for explanation. Below the transfer electrode is an n ^- impurity layer 1.
3. It is a buried channel consisting of a p ^- impurity layer 14, and the charge left behind in the potential well (transfer loss) is extremely small even during high-speed operation. The input section is configured so that an analog signal applied to the input diode together with a DC bias is converted into a charge form and sampled under the _G2 gate using the so-called diode cut-off method. That is, when the sampling pulse φs applied to the _G1 gate is set to a high level, charge is charged from the input diode ID to the bottom of the _G2 gate, and the interface potential under the _G2 gate reaches a potential equal to the potential level of the input diode. reaches. After that, when φs becomes a low level potential, ID and G ₂
Since the area under the gate is electrically isolated, charge 20 is temporarily accumulated under the _G2 gate.
(Figure a) Since this charge is proportional to the potential change of ID, it corresponds to the input analog signal. This charge does not depend on the discharge time tβ until the transfer gate φt opens to transfer the charge to the transfer channel section after φs transitions to a low level. When the next transfer operation starts, the transfer gate φt closest to the G ₂ gate is set to a high level, and this charge 20 is transferred below the φt gate. In this case, G ₁ ,
The part under the _G2 gate and the part under the φt gate is the Si substrate 11
Since it has a surface channel structure in which a charge transfer path is formed at the interface between the gate electrode and the oxide film, a portion 20a of the charge 20 remains under the _G2 gate during high-speed transfer operation equivalent to 10 MHz. (Figure b) Next, when the potential under the φt gate becomes low and the transfer section and the input section that temporarily holds the sampled charges are electrically separated, only the charge of 20b is adjacent to the φt gate. Transferred below the _φ2 gate. The amount of charge 20b transferred to this transfer stage is
It is determined by the effective on time (effective high level period) of the transfer pulse applied to the φt gate. In particular, in high-speed transfer operation of about 10MHz, the minute difference in the on-time when the φt gate is open is 20b
Largely changes the amount of charge. The conventional CCD driving method uses a pulse group (φs, φ ₁ =φt, φ ₂ ) as shown in FIG. 2 for ease of circuit configuration. The sampling pulse φs is applied to the _G1 gate, and the transfer pulse φt is shared with the transfer drive pulse _φ1 and is also applied to the φt gate. The other transfer drive pulse φ ₂ is a complementary pulse to φ ₁ ,
Duty is almost constant regardless of fs.

The width of the sampling pulse φs is also kept constant regardless of fs. Here, for convenience, two-phase drive is assumed. Figures a and b are drive waveforms during high-speed and low-speed sampling operations, respectively, and the on-times tr, tr ₁ of the φt gate to which the pulse φ ₁ for driving the transfer electrode is commonly supplied as the sampling frequency fs changes. It is a pulse of changing mode.

Changes in the on-times tr and _tr1 of the φt gate appear as a difference in the amount of charge 20b transferred to the transfer stage. That is, the higher the driving frequency of the CCD output voltage becomes, the smaller it becomes. This situation is shown in FIG. 3, which shows the change in CCD output voltage with respect to the sampling frequency. A broken line 22 in the figure shows the fs dependence of the CCD output voltage V ₀ when operating with the drive waveform shown in FIG. Since the charging time tα is constant, there is almost no offset change in V ₀ during low-frequency sampling, but when high-speed sampling operations of several MHz or higher occur, deterioration of V ₀ is observed. This deterioration occurs due to a change in the on-time tr of φt. Since the output signal of a CCD is an amplitude modulated waveform that is periodically reset to a constant level, it is used in the field of signal processing by attenuating out-of-band components and removing aliasing distortion using a low-pass filter. Therefore, if the effective hold width of the amplitude-modulated output signal changes due to the offset change, the amplitude of the analog signal after passing through the low-pass filter will change.

Generally, when the signal charge decreases, the hold width is expanded and the output signal amplitude increases. like this
When gain fluctuation occurs due to fs change, the signal processing circuit becomes more complicated when used in a system.

In order to eliminate the above drawbacks, it is an object of the present invention to provide a CCD driving method in which the width of the sampling pulse, the transfer gate pulse, and the duty of the transfer drive pulse are held constant and no gain fluctuation occurs.

According to the present invention, in a method for driving a CCD in which the input section is composed of a surface channel and the transfer section adjacent to the input section is composed of a buried channel, by a diode cut-off method, a signal applied to a first input gate is provided. the width of the sampling pulse for sampling,
The effective on-time of the transfer pulse for opening and closing the transfer gate provided closest to the second gate that temporarily stores the signal charge in the input section, as well as the duty ratio of the pulse for driving the transfer section, are independent of sampling frequency changes. A CCD driving method is obtained which is characterized in that the CCD is driven in such a way that the current value is constant.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 4 is a diagram for explaining an embodiment of the CCD driving method of the present invention. In this figure, the same symbols as those shown in FIG. 2 represent the same components.

The feature of the present invention is that it is a driving method that keeps the gate-on time tr of φt, the width tα of the sampling pulse φs, and the duty ratio of the transfer drive pulse constant regardless of changes in the sampling frequency fs.
Figure 4a shows the timing of the drive pulse during high-speed sampling operation, and Figure 4b shows the timing of the drive pulse during low-speed sampling operation.
The duty ratios (to/Ts, to ₁ /Ts ₁ ) of the pulses φ ₁ and φ ₂ with respect to tα, tr, and period Ts are kept equal. Therefore, the charge at the input section where the signal is sampled using the diode cut-off method is 20,φt
The amount of charge 20b transferred to the bottom of the gate remains constant regardless of fs. First, a description will be given of an example of a DC charge injection operation when applying only a DC bias to ID and _G2 . Width tα of sampling pulse φs
By fixing , the amount of charge charged from ID to the bottom of the _G2 gate during sampling is fixed.
Also, from φs off (low level) to transfer gate φt
The time until it opens may vary with fs, but it does not change the CCD output voltage V ₀ . Next, by keeping the on time tr of the pulse φt supplied to the transfer gate φt constant, φt _is
Because the valid time transferred to the gate is constant.
The transferred charge 20b is also kept constant regardless of fs. Therefore, the sum of the signal voltage detected at the output section of the CCD and the offset (corresponding to the bias charge) V ₀
is obtained as a constant value regardless of fs (solid line 23 in Figure 3).

Furthermore, for a sinusoidal analog signal, the signal amplitude at the output section is not dependent on fs and is maintained constant. In this case, if the duty ratio with respect to the period of the transfer pulses φ ₁ and φ ₂ is kept constant (for example, duty 50%), the hold width of the output signal that causes the off timing of φ ₁ or φ ₂ can be changed. The duty ratio to the period is kept constant.

Therefore, since the effective hold width is held constant, the signal amplitude when extracting the energy component of the signal, such as when passing through a low-pass filter for removing aliasing distortion, becomes constant regardless of fs. This means that no device gain variation occurs. In the above example, it is assumed that φ ₁ and φ ₂ are complementary pulses. Also,
It does not matter whether φ ₁ or φ ₂ is supplied to the gate of the reset MOSFET; if φ ₁ or φ ₂ is used as a reset pulse, φ ₁ or φ ₂ is also supplied to the transfer gate nearest to the output gate. A pulse will be supplied.

FIG. 5 is for explaining another embodiment of the CCD driving method of the present invention. This embodiment is characterized in that the pulse applied to the transfer drive gate _φ1 is the same as φt. Of course, tα and tγ as described in the previous embodiment are maintained constant regardless of fs. In this case, as is clear from the above explanation, the charge 20 that is charged from the input diode ID to the bottom of the _G2 gate and the charge 20a that remains under the _G2 gate without being transferred to the electrode of the transfer gate φt is fs does not depend on Therefore, the charge generated at the CCD output section is also constant. This charge is transferred and outputted by 20b in FIG. When a sinusoidal analog signal is applied to the input gate, the amplitude of the signal voltage observed at the output section no longer depends on fs. However, depending on the sampling frequency,
Effective hold width of output signal (Ts−tr)/Tr,
(Ts ₁ − tr)/Ts ₁ changes. For example, in a configuration in which _φ1 is supplied to the reset MOSFET and the final transfer stage, the operation mode is such that a signal is generated at a low level of _φ1 , and the hold width increases as fs decreases.

In this case, it is preferable to sample and hold (zero-order hold) the amplitude modulated waveform generated in the CCD output in a fixed window, without directly supplying the CCD output to the low-pass filter section for removing aliasing distortion. By doing this, the energy component of the signal (signal amplitude after passing through the low-pass filter) is fixed, so that gain fluctuations in the device can be avoided. Furthermore, if a configuration is used in which _φ2 is supplied to the final transfer stage closest to the reset MOSFET and the output gate, a signal is generated at the low level of _φ2 , so the hold width becomes smaller as fs decreases. In this case as well, if the amplitude modulation waveform generated in the CCD output is held in zero order, the energy component of the signal is maintained. Therefore, device gain variations are avoided.

Incidentally, the driving waveform as shown in FIG. 4 can be easily obtained by delaying the master clock equal to the width of the gate pulse of _φ1 and setting an appropriate gate. The sampling pulse φs is obtained by delaying and inverting the master clock that is in phase with the pulse of _φ1 , and the NR gate of the pulse _φ1 that is not delayed, and the transfer gate pulse φt is obtained by delaying the master clock by tr and the inverse of the master clock. Obtained by NR gate with phase pulse. Therefore, it is easy to implement an IC with a MOS structure.
On-chip IC implementation on a CCD chip is also possible.

As is clear from the above description, according to the driving method of the present invention, the gain of the device can be kept constant regardless of changes in the sampling frequency. The driving method of the present invention is particularly useful in compressing and expanding the time axis using a CCD. If the output amplitude is kept constant regardless of changes in fs, the signal processing circuit in a system using a CCD will be simpler. Furthermore, this driving method is effective even when master clock jitter occurs, which causes a slight change in sampling frequency. Moreover, the circuit configuration for implementing this driving method is simple and can be easily implemented if IC is considered. Further, the CCD driving method of the present invention is not limited to the CCD structure shown in FIG. 1, but any structure may be used as long as the diode cut-off method can be applied. Further, the present invention is not limited to p-type semiconductor substrates, but can also be applied to CCDs using n-type semiconductor substrates, and the polarity of the pulses in this case is reversed.
Furthermore, it goes without saying that the present invention can be applied not only to two-phase drive but also to drive using multi-phase drive pulses.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a cross-sectional view of the structure and potential distribution near the input section of the CCD, Figure 2 is a diagram for explaining an example of a conventional CCD driving method, and Figure 3 is a diagram showing changes in the sampling frequency of the CCD output voltage. A diagram showing
FIG. 4 is a diagram for explaining an embodiment of the CCD driving method according to the present invention, and FIG. 5 is a diagram according to the present invention.
FIG. 7 is a diagram for explaining another example of the CCD driving method. In the figure, 11: semiconductor substrate, 1
2: Input diode, 13, 14: Impurity layer, 2
0, 20a, 20b: Charge, 22, 23: CCD
Output voltage characteristics.

Claims (1)

[Claims] 1 The input section is composed of surface channels, and the transfer section adjacent to the input section is composed of embedded channels.
In a method of driving a CCD using the diode cut-off method, the width of the sampling pulse for signal sampling applied to the first input gate is set closest to the second gate for temporarily accumulating the signal charge at the input section. A CCD driving method characterized by driving a CCD so that the effective on-time of a transfer pulse for opening and closing a transfer gate and the duty ratio of a pulse for driving a transfer section are constant regardless of changes in sampling frequency.