JPH0219455B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a dot matrix display panel.

Conventionally, in driving a dot matrix display panel, for example, in the case of a panel having a switching display in each pixel, a Y driver 3 is connected to vertical electrodes _Y1 to _YN of a panel 1, as shown in FIG. An X driver 2 is connected to the horizontal electrodes X ₁ to X _M , and the X driver 2 has a period 2T ₀ from the terminal 4 as shown in the time chart of FIG.
The clock pulses shown in FIG. 2 are applied to the electrodes X _{1 -X M} of the panel 1, and _the waveforms shown in FIG. That is, FIG. 2 is a diagram showing the timing of the X driver of FIG. 1, which shows a conventional example. In FIG. 2, reference numeral 5 is a start signal for starting the driving of the horizontal electrode drive circuit (X driver 2). X1-X4 is X driver 2
The output waveform of is shown. 4 is a clock pulse for shifting sampling data. When the start pulse 5 is input, it is captured by the clock pulse 4, and the X driver 2 starts sampling the image input and outputting the voltage of the image signal. The start pulse 5 is shifted every one clock pulse 4. Therefore, since the output of the X driver is shifted on every rising edge of the clock pulse signal,
The voltage of the sequentially sampled image signal is output with a delay time of 2TO during the sampling period. By the way, the operating frequency of the X driver 2 side is much faster (more than 100 times) than that of the Y driver 1, so the power consumption is large.For this reason, the X driver 2 is serially divided and only the necessary parts are sequentially processed. Consideration has been given to reducing power consumption by operating the device. However, since the frequency of the clock pulse is very high in this method, there are many drawbacks such as a delay with the block selection signal when switching the divided blocks, resulting in malfunction. was necessary.

The present invention has been made in view of the above drawbacks, and aims to reduce power consumption of the drive circuit, and
The purpose is to ensure and stabilize circuit operation.

The present invention will now be described in detail with reference to the drawings. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a diagram showing signal waveforms at various parts in FIG. The drive circuit (X driver 2) that drives the horizontal electrodes in FIG. 1 is as follows in FIG.
Drive circuit (X driver) that drives horizontal electrodes
It is divided into 21, 22, 23 and 24. Further, the clock pulses for driving the four X drivers are 41, 42, 43 and 4, respectively.
4. Here, the start signal input terminal of each of the X drivers 21 to 24 is connected to the terminal 5, and the terminal 8
The image signal input terminals of each of the X drivers 21 to 24 are connected to the image signal input terminals of each of the X drivers 21 to 24, the output terminals of each of the X drivers 21 to 24 are alternately connected to the horizontal direction electrodes X ₁ to X _4n+4 of the panel 1, and the Y
Start signal input terminal of driver 3, terminal 7 has Y
The clock pulse input terminal of the driver 3 is connected to the vertical direction electrodes Y 1 to Y N of the panel 1, and each output of the Y driver 3 is connected to the vertical direction electrodes Y ₁ to _{Y N} of the panel 1.
In addition, outputs 41 to 4 of the clock pulse generator 4 are connected to the clock pulse input terminals of each of the X drivers 21 to 24.
4 are connected to each other.

In operation, the outputs of the X drivers 21-24 are alternately connected to the horizontal electrodes of the panel 1, and the clock pulses shown in FIG. 4 41-44 are supplied from the clock pulse generator 4. . Therefore, when a start signal as shown in FIG. 4 and 5 is input to terminal 5, the image signal from terminal 8 becomes the fourth
Sequentially sampled as shown in Figures _X1 to _X5 ,
The data is written to each pixel in the row selected by the Y driver. (This example describes the case without a line memory circuit, but
In some cases, waveforms X ₁ -X ₅ are only temporarily held in line memory and written to each pixel. ) By the way, in the case of the present invention, the clock pulse has a period of 8T ₀ , which is 1/4 compared to 2T ₀ when not divided, so the power consumption is 1/4, and there is no need to worry about clock pulse delays, etc. In addition, if each X driver 21 to 24 is further divided serially into several blocks, not only can the power consumption be further reduced by the number of divisions, but the clock pulse period can be increased to _8T0. Therefore, depending on the connection method, it is possible to operate even if the delay of the clock pulse is quite large. In addition, in this embodiment, the fourth
As _shown in _{Figures 1} ～
Since the voltage of the image signal of each output of each X driver 21 to 24 that is applied to X _4n+4 is written to each pixel in a time shorter than the sampling period,
There is virtually no reduction in resolution.

If there is a concern about resolution deterioration, it is possible to further provide gates to the outputs of each of the X drivers 21 to 24 to avoid this problem, and even in that case, the effects of the present invention are the same.

As described above, according to the present invention, four
By configuring the horizontal driver to be divided and driven by more than one type of clock pulses 41 to 44, there is no need to worry about delays in clock pulses during mounting, and power consumption can be significantly reduced. It has the excellent effect of

Although an example of a switching element panel has been described here, the same effect can be obtained with other matrix panels.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one conventional embodiment, and the second
The figure is a diagram showing the time chart of FIG. 1. FIG. 3 shows an embodiment according to the present invention, and FIG. 4 shows a time chart thereof. DESCRIPTION OF SYMBOLS 1... Display panel, 2, 21-24... X driver, 3... Y driver, 4, 41-44... Clock pulse end, 5, 6... Start signal input end, 7... Clock pulse input end, 8... Image signal input end.

Claims (1)

[Claims] 1. In a display drive circuit that drives a matrix type display device in which display pixels are intersections between horizontal electrodes and vertical electrodes that are crossed in a matrix, at least the horizontal electrode drive circuit that drives the horizontal electrodes has a phase difference. 1. A display drive circuit comprising parts driven by four or more different types of clock pulses and an even number of clock pulses.