JPH0325012B2 - - Google Patents
Info
- Publication number
- JPH0325012B2 JPH0325012B2 JP18708884A JP18708884A JPH0325012B2 JP H0325012 B2 JPH0325012 B2 JP H0325012B2 JP 18708884 A JP18708884 A JP 18708884A JP 18708884 A JP18708884 A JP 18708884A JP H0325012 B2 JPH0325012 B2 JP H0325012B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- film
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 22
- 238000001020 plasma etching Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000009719 polyimide resin Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 26
- 230000005669 field effect Effects 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000010849 ion bombardment Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置およびその製造法に関し、
とくに集積回路においてリフトオフ法を適用して
電極・下層配線を高歩留りで形成し、かつ多層配
線に適した平坦化を実現する半導体装置およびそ
の製造方法に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same;
In particular, the present invention relates to a semiconductor device and a method for manufacturing the same in which the lift-off method is applied to an integrated circuit to form electrodes and lower layer wiring at a high yield, and to achieve planarization suitable for multilayer wiring.
化合物半導体基板上に電界効果トランジスタ
（FET）や集積回路を製作する場合において、基
板表面上への各種電極や下層配線の形成はリフト
オフ法が用いることが一般的である。SiLSIの製
造で汎用されているウエツト・エツチング法、す
なわち電極金属や下層配線金属を酸性ないし塩基
性の薬液でエツチングする方法を化合物半導体基
板に適用すると、薬液が基板と化学反応を起すと
いう問題が生じるためである。さらにSi超LSIと
同程度の微細加工が要求される点からもウエツ
ト・エツチング法は不適当である。微細化に対し
ては、薬液の代わりにガスプラズマで発生したイ
オンを用いる、いわゆるプラズマ・エツチング法
や、反応性イオン・エツチング法が考えられてい
るが、被エツチング材に対する化合物半導体基板
の選択性が低く、ウエツト・エツチング法と同じ
問題がある。加えて、プラズマ照射やイオン衝撃
によつて化合物半導体基板にダメージが印加され
るといる不可能な問題が残る。
When manufacturing a field effect transistor (FET) or an integrated circuit on a compound semiconductor substrate, a lift-off method is generally used to form various electrodes and lower wiring on the surface of the substrate. When applying the wet etching method commonly used in SiLSI manufacturing, in which electrode metals and lower layer wiring metals are etched with an acidic or basic chemical solution, to a compound semiconductor substrate, there is a problem that the chemical solution causes a chemical reaction with the substrate. This is because it occurs. Furthermore, the wet etching method is inappropriate because it requires microfabrication on the same level as Si super LSI. For miniaturization, so-called plasma etching methods that use ions generated by gas plasma instead of chemical solutions and reactive ion etching methods are being considered, but the selectivity of compound semiconductor substrates with respect to the material to be etched has been considered. This method has the same problem as the wet etching method. In addition, there remains the impossible problem of damage being applied to the compound semiconductor substrate by plasma irradiation or ion bombardment.
集積回路の微細化に対して電極、配線の電気抵
抗を小さくするためには、電極および配線金属の
厚さを増加する必要がある。この場合、電極、配
線の形成にリフトオフ法を適用すると、たとえば
第３図Ａ，Ｂに示すようにバリ３０がゲート電極
２に発生する。このようなバリを残して多層配線
を行うと、バリの部分で層間絶縁膜に割れが生じ
たり、上下配線間に電界集中が生じたりすること
が原因で短絡現象が発生し、集積回路の歩留りが
低下するという問題がある。なお第３図Ａの２１
はフオトレジストを示す。
In order to reduce the electrical resistance of electrodes and interconnections for miniaturization of integrated circuits, it is necessary to increase the thickness of electrodes and interconnection metals. In this case, if a lift-off method is applied to form electrodes and wiring, burrs 30 are generated on the gate electrode 2, as shown in FIGS. 3A and 3B, for example. If multilayer wiring is performed with such burrs left behind, cracks may occur in the interlayer insulating film at the burrs, and short circuits may occur due to electric field concentration between the upper and lower wiring, which will reduce the yield of integrated circuits. There is a problem that the amount decreases. In addition, 21 in Figure 3 A
indicates photoresist.
上述のバリをなくすために、たとえば第４図Ａ
〜Ｄに製造工程概要を示す多層レジスト法が試み
られている。この多層レジスト法は、リフトオフ
に用いるレジストを厚くし、同時にレジスト断面
形状を逆台形にすることでバリの発生を防ぐこと
を狙つたものである。しかしながら、この多層レ
ジスト法では微細化の点からも最下層のレジスト
を反応性イオン・エツチングすることが一般的で
あり、半導体表面のダメージが懸念される。加え
て、多層レジスト法は工程が多くかつ複雑なた
め、制御性、再現性が悪く歩留り、生産性が低い
という欠点がある。なお、第４図で２１，２３は
フオトレジスト、２２は中間層、２はゲートで電
極を示す。 In order to eliminate the above-mentioned burrs, for example,
A multilayer resist method, the outline of the manufacturing process of which is shown in FIGS. This multilayer resist method aims to prevent the occurrence of burrs by increasing the thickness of the resist used for lift-off and at the same time making the cross-sectional shape of the resist an inverted trapezoid. However, in this multilayer resist method, it is common to perform reactive ion etching on the bottom resist layer from the viewpoint of miniaturization, and there is a concern that damage to the semiconductor surface may occur. In addition, since the multilayer resist method involves many and complicated steps, it has the disadvantage of poor controllability and reproducibility, resulting in low yield and productivity. In FIG. 4, 21 and 23 are photoresists, 22 is an intermediate layer, and 2 is a gate electrode.
上述した問題を解決する方法として、たとえば
第５図Ａ〜Ｄの製造工程の概要を示した絶縁膜
（スペーサ）リフトオフ法がある。多層レジスト
法の下層レジストの部分を絶縁膜１１で置き替え
たもので、リフトオフ後の形状が平坦化されると
いう利点を持つている。しかしながら、絶縁膜の
加工には反応性イオン・エツチングを適用するた
め、やはり半導体基板表面のダメージが問題とな
る。たとえば絶縁膜として窒素珪素膜を用いたス
ペーサ・リフトオフ法でGaAs基板上に電界効果
トランジスタ（FET）を作成すると、FETのし
きい値電圧（Vth）のばらつきが大きくなること
が確認された。 As a method for solving the above-mentioned problems, there is, for example, an insulating film (spacer) lift-off method, the manufacturing process of which is outlined in FIGS. 5A to 5D. This is a method in which the lower resist portion of the multilayer resist method is replaced with an insulating film 11, and has the advantage that the shape after lift-off is flattened. However, since reactive ion etching is applied to process the insulating film, damage to the semiconductor substrate surface still becomes a problem. For example, when a field effect transistor (FET) is fabricated on a GaAs substrate using the spacer lift-off method using a silicon nitride film as an insulating film, it has been confirmed that the variation in the threshold voltage (Vth) of the FET increases.
本発明は、以上述べた各種技術の問題点をすべ
て解決する半導体装置およびその製造方法を提供
するものである。
The present invention provides a semiconductor device and a method for manufacturing the same that solves all of the problems of the various techniques described above.
すなわち本発明の半導体装置は、基板表面に電
極および下層配線と同等以上の厚さに積層形成し
た、ウエツト・エツチング法に適用した絶縁材料
からなる下層絶縁膜および反応性イオン・エツチ
ング法に適用した絶縁材料からなる上層絶縁膜の
二層絶縁膜と、二層絶縁膜それぞれに適用したエ
ツチング法により基板直上に形成した二層絶縁膜
の開口部と、開口部に電極および下層配線の金属
材料を蒸着、リフトオフすることにより埋め込ま
れた電極および下層配線とを備えた構造を有した
構成としている。かかる構成は、化合半導体基板
表面に二種類の絶縁材料により上、下二層の絶縁
膜を形成し、上層絶縁膜上に所定のフオトレジス
ト・パターンを形成して、このフオトレジスト・
パターンをマスクとして上層の絶縁膜を反応性イ
オン・エツチングし、次いでフオトレジスト・パ
ターンと上層の絶縁膜をマスクとして下層の絶縁
膜をウエツト・エツチングすることにより上、下
層の両絶縁膜にフオトレジスト・パターンと同一
の開口部を形成した後電極および下層配線の金属
を蒸着し、リフトオフする工程により得られる。 That is, the semiconductor device of the present invention includes a lower insulating film made of an insulating material applied to the wet etching method, which is laminated on the surface of the substrate to a thickness equal to or greater than that of the electrodes and lower layer wiring, and a lower insulating film made of an insulating material applied to the reactive ion etching method. The two-layer insulating film is an upper insulating film made of an insulating material, the opening of the two-layer insulating film is formed directly above the substrate by the etching method applied to each of the two-layer insulating films, and the metal material of the electrode and lower wiring is formed in the opening. The structure includes electrodes and lower layer wiring buried by vapor deposition and lift-off. In this structure, upper and lower insulating films are formed on the surface of a compound semiconductor substrate using two types of insulating materials, and a predetermined photoresist pattern is formed on the upper insulating film.
The upper insulating film is reactive ion etched using the pattern as a mask, and then the lower insulating film is wet-etched using the photoresist pattern and the upper insulating film as a mask. - Obtained by forming an opening identical to the pattern, then vapor depositing metal for the electrode and lower layer wiring, and lifting off.
本発明により得られた半導体装置は、二層絶縁
膜中に電極、下層配線が埋め込まれた状態とな
り、平坦な構造が得られるとともに、上層絶縁膜
を異方性の高い反応性イオン・エツチングにより
高精度に微細加工し、かつ反応性イオン・エツチ
ングは下層絶縁膜の部分で停止するので半導体基
板表面はイオン衝撃によるダメージから保護され
る。以下実施例について詳細に説明する。
In the semiconductor device obtained according to the present invention, the electrodes and the lower wiring are embedded in the two-layer insulating film, and a flat structure is obtained.The upper insulating film is etched by highly anisotropic reactive ion etching. The semiconductor substrate surface is protected from damage caused by ion bombardment because it is microfabricated with high precision and reactive ion etching stops at the underlying insulating film. Examples will be described in detail below.
第１図に本発明の構成を説明する構造断面図を
示す。半導体基板１の表面に二種の化学的性質の
異なる絶縁膜１１，１２を積層し、この二層絶縁
膜１１，１２に形成した開口部内にゲート電極
２、オーミツク電極３および下層配線４を埋め込
むことが本質である。
FIG. 1 shows a structural sectional view illustrating the configuration of the present invention. Two insulating films 11 and 12 having different chemical properties are laminated on the surface of a semiconductor substrate 1, and a gate electrode 2, an ohmic electrode 3, and a lower wiring 4 are embedded in the openings formed in the two-layer insulating films 11 and 12. That is the essence.
第２図Ａ〜Ｇに本発明の半導体装置の一実施例
の製造方法を示す。 FIGS. 2A to 2G show a method of manufacturing an embodiment of the semiconductor device of the present invention.
本実施例では、半導体基板たとえばGaAs基板
１上に電界効果トランジスタ（FET）を作成す
る場合を例示する。 In this embodiment, a case will be exemplified in which a field effect transistor (FET) is formed on a semiconductor substrate, for example, a GaAs substrate 1.
まず、導電層５を形成したGaAs基板１の表面
に通常のCVD法により下層の第１の絶縁膜１２、
たとえばSiO2（酸化珪素）膜１２を1000Åの厚さ
に形成し、続いてプラズマCVD法により他の絶
縁材料からなる上層の第２の絶縁膜１１、たとえ
ばSi−Ｎ（窒化珪素）膜１１を3500Åの厚さに形
成する。：（第２図Ａ）。 First, a lower first insulating film 12,
For example, a SiO 2 (silicon oxide) film 12 is formed to a thickness of 1000 Å, and then an upper second insulating film 11 made of another insulating material, such as a Si-N (silicon nitride) film 11, is formed by plasma CVD. Formed to a thickness of 3500 Å. : (Figure 2A).
この二層絶縁膜１１，１２の上に所定のフオト
レジスト・パターン２１を形成する。：（第２図
Ｂ）。 A predetermined photoresist pattern 21 is formed on the two-layer insulating films 11 and 12. : (Figure 2B).
このフオトレジスト・パターン２１をマスクと
して、たとえばCF4ガス・プラズマを用いた反応
性イオン・エツチング（ガス圧：５×10-2Torr、
パワー：100W、時間：２分）で上層のSi−Ｎ膜
１１をエツチングし、フオトレジスト・パターン
２１と同じ開口部３１を設ける。このとき、下層
のSiO2膜１２のエツチング速度は上層のSi−Ｎ
膜１１の1/5であり、反応性イオン・エツチング
は実質上、下層のSiO2膜１２のところで停止す
る。：（第２図Ｃ）。 Using this photoresist pattern 21 as a mask, reactive ion etching using, for example, CF 4 gas plasma (gas pressure: 5×10 -2 Torr,
The upper Si--N film 11 is etched with a power of 100 W and a time of 2 minutes to form an opening 31 that is the same as the photoresist pattern 21. At this time, the etching rate of the lower layer SiO 2 film 12 is the same as that of the upper layer Si-N.
1/5 of the film 11, and the reactive ion etching essentially stops at the underlying SiO 2 film 12. : (Figure 2C).
次いで、このフオトレジスト・パターン２１と
上層のSi−Ｎ膜１１をマスクとして、たとえばウ
エツト・エツチング、たとえば緩衝弗酸液で30秒
エツチングし下層のSiO2膜１２に開口部３２を
設ける。：（第２図Ｄ）。 Next, using this photoresist pattern 21 and the upper Si-N film 11 as a mask, wet etching is performed, for example, etching with a buffered hydrofluoric acid solution for 30 seconds to form an opening 32 in the lower SiO 2 film 12. : (Figure 2D).
上記工程の直後に、たとえばAu−Ge／Ni／
Auの合金を4000Åの膜厚に蒸着しリフトオフす
ることによりオーミツク電極３を形成する。：（第
２図Ｅ）。 Immediately after the above process, for example, Au-Ge/Ni/
An ohmic electrode 3 is formed by depositing an Au alloy to a thickness of 4000 Å and lifting it off. : (Figure 2 E).
次いで、450℃の熱処理の後、プラズマCVD法
により3000Åの厚さに上層のSi−Ｎ膜１１と同じ
材料の絶縁膜のSi−Ｎ膜１３を形成する。：（第２
図Ｆ）。 Next, after heat treatment at 450° C., an insulating Si-N film 13 made of the same material as the upper Si-N film 11 is formed to a thickness of 3000 Å by plasma CVD. :(Second
Figure F).
最後に、上記工程と全く同様の工程により、二
層の絶縁膜、すなわち下層のSiO2膜１２および
上層を形成するSi−Ｎ膜１１，１３に形成した開
口部に、たとえばTi／Au合金を7000Åの厚さに
蒸着し、リフトオフすることによりゲート電極２
および下層配線４を形成する。：（第２図Ｇ）。 Finally, by a process completely similar to the above process, a Ti/Au alloy, for example, is applied to the openings formed in the two-layer insulating film, that is, the lower SiO 2 film 12 and the upper Si-N films 11 and 13. The gate electrode 2 is deposited to a thickness of 7000 Å and lifted off.
and lower layer wiring 4 is formed. : (Figure 2G).
本実施例により二層絶縁間ウエハに作成した電
界効果トランジスタ（FET）のしきい値電圧の
分布を第６図に例示する。比較のため下層の絶縁
膜の無い状態で、第５図Ａ〜Ｄに示した従来の絶
縁膜（スペーサ）リフトオフ法により作成した電
界効果トランジスタ（FET）の場合のしきい値
電圧の分布の典型的な例を第７図に示す。第６
図、第７図において横軸は電界効果トランジスタ
（FET）のしきい値電圧Vth（Volt）、縦軸は電界
効果トランジスタ（FET）の電流駆動能力を意
味する性能指数Ｋフアクタ（ｍＡ／V2）である。
第６図および第７図を比較してみると、明らかに
反応性イオン・エツチングを行うと半導体基板表
面にダメージを与え、電界効果トランジスタ
（FET）の特性に悪影響をもたらしており、本発
明の有効性が確認される。 FIG. 6 illustrates the threshold voltage distribution of a field effect transistor (FET) fabricated on a two-layer insulating wafer according to this example. For comparison, a typical distribution of threshold voltage in the case of a field effect transistor (FET) fabricated by the conventional insulating film (spacer) lift-off method shown in Figures 5A to 5D without an underlying insulating film. A typical example is shown in Figure 7. 6th
7, the horizontal axis is the threshold voltage Vth (Volt) of the field effect transistor (FET), and the vertical axis is the figure of merit K factor (mA/V 2 ), which means the current drive ability of the field effect transistor (FET). ).
Comparing Figures 6 and 7, it is clear that reactive ion etching damages the surface of the semiconductor substrate and has an adverse effect on the characteristics of the field effect transistor (FET). Validity is confirmed.
本発明は、上層の絶縁膜の反応性イオン・エツ
チングと下層の絶縁膜のウエツト・エツチングに
対し、上層、下層の絶縁膜がそれぞれエツチング
の選択性を持つことが本質である。また下層の絶
縁膜のエツチングは、半導体基板にダメージを与
えなければ本発明の目的を達するものであり、本
実施例に示したウエツト・エツチングに限定され
るものでなく、プラズマ・エツチングなどの方法
を適用することも勿論可能である。この意味で二
層絶縁膜の材料の組合せは何ら実施例に限定され
るものではなく、たとえばSi−Ｎ／PIQやPIQ／
SiO2など任意の組合せが可能である。 The essence of the present invention is that the upper and lower insulating films each have etching selectivity with respect to reactive ion etching of the upper insulating film and wet etching of the lower insulating film. Furthermore, etching of the underlying insulating film can achieve the purpose of the present invention as long as it does not damage the semiconductor substrate, and is not limited to wet etching as shown in this embodiment, but may also be performed using methods such as plasma etching. Of course, it is also possible to apply. In this sense, the combination of materials for the two-layer insulating film is not limited to the examples; for example, Si-N/PIQ, PIQ/
Any combination such as SiO 2 is possible.
また、本実施例では下層の絶縁膜をウエツト・
エツチングするにあたりSiO2膜の厚さを1000Å
と薄くし、サイド・エツチングを小さくして微細
加工の精度の向上を図つたが、必要とする精度に
応じて膜厚を任意に選びうることは言うまでもな
い。 In addition, in this example, the underlying insulating film is wetted.
When etching, the thickness of the SiO 2 film is 1000Å.
Although we aimed to improve the precision of microfabrication by making the film thinner and reducing side etching, it goes without saying that the film thickness can be arbitrarily selected depending on the required precision.
以上述べたとおり、本発明によれば、半導体装
置の構造は、あたかも二層の絶縁膜中に電極、下
層配線が埋め込まれた状態となり、かつ平坦な構
造が得られる。加えて、異方性の高い反応性イオ
ン・エツチングによつて厚い上層の絶縁膜を加工
しているため、高精度な微細加工が可能であり、
かつこの反応性イオン・エツチングは下層の絶縁
膜の部分で停止するため、化合物半導体基板表面
はイオン衝撃によるダメージから保護される。さ
らに、下層の絶縁膜をウエツト・エツチングする
ことは、エツチング後の清浄な表面に電極および
下層配線の金属材料を蒸着するという効果を有す
る。
As described above, according to the present invention, the structure of the semiconductor device is as if the electrodes and the lower wiring are embedded in a two-layer insulating film, and a flat structure can be obtained. In addition, since the thick upper insulating film is processed using highly anisotropic reactive ion etching, highly accurate microfabrication is possible.
Moreover, since this reactive ion etching stops at the underlying insulating film, the surface of the compound semiconductor substrate is protected from damage caused by ion bombardment. Furthermore, wet etching the underlying insulating film has the effect of depositing metal materials for the electrodes and underlying interconnects onto the clean surface after etching.
第１図は本発明の構成を説明する構造断面図、
第２図Ａ〜Ｇは本発明の半導体装置の一実施例の
製造方法を示す図、第３図Ａ，Ｂは従来のリフト
オフ法による電極形成を説明する図、第４図Ａ〜
Ｄは従来の多層レジスト法を説明する図、第５図
Ａ〜Ｄは従来の絶縁膜（スペーサ）リフトオフ法
を説明する図、第６図は本発明による実施例で作
成した電界効果トランジスタ（FET）の特性の
二層絶縁膜ウエハにおけるしきい値電圧の分布
図、第７図は従来の絶縁膜（スペーサ）リフトオ
フ法による電界トランジスタ（FET）のしきい
値電圧の分布特性図である。
１……半導体基板、１１，１２……上層および
下層絶縁膜、１３……絶縁膜、２……ゲート電
極、２１，２３……フオトレジスト、２２……中
間層、３０……バリ、３……オーミツク電極、３
１，３２……開口部、４……下層配線、５……導
電層。
FIG. 1 is a structural sectional view explaining the configuration of the present invention;
2A to 2G are diagrams showing a manufacturing method of an embodiment of the semiconductor device of the present invention, FIGS. 3A and 3B are diagrams illustrating electrode formation by the conventional lift-off method, and FIGS. 4A to 4
D is a diagram explaining the conventional multilayer resist method, FIGS. 5A to D are diagrams explaining the conventional insulating film (spacer) lift-off method, and FIG. ) is a distribution diagram of the threshold voltage in a double-layer insulating film wafer with the characteristics of FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 11, 12... Upper layer and lower layer insulating film, 13... Insulating film, 2... Gate electrode, 21, 23... Photoresist, 22... Intermediate layer, 30... Burr, 3... ...Ohmic electrode, 3
1, 32...opening, 4...lower layer wiring, 5...conductive layer.
Claims (1)
厚さに積層形成した、ウエツト・エツチング法に
適応した絶縁材料からなる下層絶縁膜および反応
性イオン・エツチング法に適応した絶縁材料から
なる上層絶縁膜の二層絶縁膜と、 該二層絶縁膜それぞれに適応した前記エツチン
グ法により該基板直上に形成した該二層絶縁膜の
開口部と、 該開口部に該電極および下層配線の金属材料を
蒸着、リフトオフすることにより埋め込まれた電
極および下層配線とを備えてなる ことを特徴とする半導体装置。 ２ 前記二層絶縁膜の下層絶縁膜が酸化珪素、上
層絶縁膜が窒化珪素で構成されてなる特許請求の
範囲第１項記載の半導体装置。 ３ 前記二層絶縁膜の下層絶縁膜が酸化珪素、上
層絶縁膜がポリイミド樹脂で構成されてなる特許
請求の範囲第１項記載の半導体装置。 ４ 前記二層絶縁膜の下層絶縁膜を構成する酸化
珪素が2000Å以下の厚さとしてなる特許請求の範
囲第２項または特許請求の範囲第３項記載の半導
体装置。 ５ 化合物半導体基板表面に二種類の絶縁材料で
それぞれ構成する下層の第１の絶縁膜および上層
で第２の絶縁膜からなる二層膜を形成し、該第２
の絶縁膜上に所定のフオトレジスト・パターンを
形成し、該フオトレジスト・パターンをマスクと
して該第２の絶縁膜を反応性イオン・エツチング
し、次いで該フオトレジスト・パターンと該第２
の絶縁膜をマスクとして該第１の絶縁膜をウエツ
ト・エツチングすることにより該フオトレジス
ト・パターンと同一の開口部を該第１および第２
の絶縁膜からなる二層膜に形成し、しかる後電極
および下層配線を形成する金属を蒸着し、リフト
オフする各工程からなる半導体装置の製造方法。[Scope of Claims] 1. A lower insulating film made of an insulating material suitable for wet etching and an insulation suitable for reactive ion etching, which is laminated on the surface of a substrate to a thickness equal to or greater than that of the electrodes and lower wiring. a two-layer insulating film of an upper-layer insulating film made of a material; an opening in the two-layer insulating film formed directly above the substrate by the etching method adapted to each of the two-layer insulating films; and an electrode and a lower layer in the opening. 1. A semiconductor device comprising an electrode and a lower layer wiring embedded by vapor-depositing and lifting off a metal material for the wiring. 2. The semiconductor device according to claim 1, wherein the lower insulating film of the two-layer insulating film is made of silicon oxide, and the upper insulating film is made of silicon nitride. 3. The semiconductor device according to claim 1, wherein the lower insulating film of the two-layer insulating film is made of silicon oxide, and the upper insulating film is made of polyimide resin. 4. The semiconductor device according to claim 2 or claim 3, wherein the silicon oxide constituting the lower insulating film of the two-layer insulating film has a thickness of 2000 Å or less. 5 A two-layer film consisting of a lower first insulating film and an upper second insulating film each made of two types of insulating materials is formed on the surface of a compound semiconductor substrate, and the second insulating film is
A predetermined photoresist pattern is formed on the second insulating film, and the second insulating film is subjected to reactive ion etching using the photoresist pattern as a mask.
By wet etching the first insulating film using the insulating film as a mask, openings identical to the photoresist pattern are formed in the first and second insulating films.
A method for manufacturing a semiconductor device comprising the steps of forming a two-layer film consisting of an insulating film, then vapor-depositing metal to form electrodes and lower wiring, and lifting off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18708884A JPS6165458A (en) | 1984-09-06 | 1984-09-06 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18708884A JPS6165458A (en) | 1984-09-06 | 1984-09-06 | Semiconductor device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6165458A JPS6165458A (en) | 1986-04-04 |
| JPH0325012B2 true JPH0325012B2 (en) | 1991-04-04 |
Family
ID=16199900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18708884A Granted JPS6165458A (en) | 1984-09-06 | 1984-09-06 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6165458A (en) |
-
1984
- 1984-09-06 JP JP18708884A patent/JPS6165458A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6165458A (en) | 1986-04-04 |
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