JPH0332502B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a speed checking device for a variable frequency automatic train stopping device, and in particular, a receiving antenna for receiving information from an on-board device and a speed check device for an on-board device. The present invention relates to an improvement of a ground device for a speed checking device in which a plurality of combinations (inspection units) with wayside elements giving stop information are provided spaced apart in the running direction of a train.

Prior Art Conventionally, the ground equipment of this type of speed checking device generally has a receiving antenna such as a loop coil or a resonant circuit for receiving information from the on-board equipment, as shown in Fig. 8.
A ₁ , A ₂ , and ground elements C ₁ , C ₂ , which are resonant circuits that provide stop information to the on-board device when the reference speed is exceeded, are installed in the direction of train travel at intervals corresponding to the assumed reference speed. unit) are provided in plural sets spaced apart from each other in the train traveling direction, and the receiving antennas A ₁ ,
At _A2 , a timer 7 which is triggered by the output signal of the processing circuit 6 and outputs a time-up signal after a certain period of time has elapsed, and this signal A counter 8 is provided to count the number of operations of the timer relay TMR, which is driven by the timer relay TMR, and thus a time-up signal, and a counter relay group COR ₀ , COR ₁ , which operates in accordance with the counted value of the counter 8 is provided.
By enabling or disabling the ground terminals C ₁ and C 2 using the relay contacts QR' ₁ and QR _{' 2} of the control relays QR ₁ and QR _{2 that} operate according to the states of COR 2 and COR ₃ , it is possible to is configured to control the on-board device so as to provide stop information and, after time-up, pass information. In other words, only when the time from when the onboard element reaches the receiving antennas A ₁ and A ₂ to when it reaches the beacon C ₁ and C ₂ is longer than a predetermined time, the beacon is disabled and the stop information is sent to the onboard equipment. I've learned not to give. Note that the counter 8 can be set according to external conditions using a set relay contact STR'. It should be noted that for each relay contact in each figure, an operating contact is indicated by a V-shaped mark, and a falling contact is indicated by an inverted V-shaped mark.

Additionally, in order to handle signals from multiple receiving antennas with a single processing circuit, the counter relay COR ₀
and a switching circuit 9 that switches the receiving antennas A ₁ and A ₂ connected to the input side of the processing circuit 6 using relay contacts COR' ₁ and COR' ₁ of COR ₁ .

By the way, in the conventional device of this kind, the counter 8 is connected to relays TMR, COR ₀ , COR 1 , COR ₂ , COR 3 , COR 3 , COR 3 , COR 0 , COR ₁ , COR ₃ ,
Since it is composed of STR contacts, it has the disadvantage that the device is complex and expensive. For this reason, it is conceivable to use a known semiconductor counter circuit as a counter to make it contactless, but there is a concern that this circuit may impair security (fail-safe).

Purpose of the Invention The present invention was made by paying attention to the fact that it is impossible for a plurality of checking units arranged in the direction of train movement to function simultaneously, and improves the security of the device by adding a check circuit. It is an object of the present invention to provide a speed checking device for an automatic train stopping device that has a simple configuration and higher safety than conventional devices even when a semiconductor counter circuit is used.

Structure of the Invention In order to achieve the above object, the present invention provides a receiving antenna that receives information from an on-board device and a beacon that provides stop information to the on-board device when the reference speed is exceeded in the direction of train travel at an assumed reference speed. A plurality of combinations installed at corresponding intervals are provided at a distance from each other in the train traveling direction, and a time-up signal is sent after a certain period of time to the output side of a processing circuit that determines the presence or absence of a received signal of a predetermined frequency at the receiving antenna. A timer that outputs a timer and a counter that counts the time-up signal are provided, and the ground element corresponding to the state of the counter relay group corresponding to the count value of the counter is provided with stop information to the onboard device before time-up, and after time-up. a check circuit for detecting that only one of the counter relays is operating; A check relay driven by the output signal of this check circuit is provided, and the operating contacts of the check relay are interposed in series with the energizing circuits to all the control relays to constitute a speed checking device for an automatic train stop device.

Embodiments The present invention will be described below based on embodiments shown in the drawings.

FIG. 1 schematically shows a speed checking device of an automatic train stopping device, and 1 is a train equipped with an on-board device 2, which travels along a running path 3 from left to right in the figure. The speed of this train 1 is determined by the receiving antennas A ₁ , A ₂ and the ground coil C ₁ ,
Corresponding pairs of C ₂ (verification unit, A ₁ and C ₁ , A ₂ and
Verification is performed using ground equipment consisting of C ₂ ) and verification circuit 4.

As shown in FIG. 2, the on-board device 2 includes an oscillator 10 that normally oscillates at a frequency f ₀ and this oscillator 1.
0 as a feedback circuit and installed at the bottom of the head of the train 1, a processing circuit 12 that selects, amplifies, rectifies and smoothes the signal of frequency _f0 from the oscillator 10, and the output signal. It has an operating main relay MR, and the operating contacts of the main relay MR are used as a brake command circuit 13.

The processing circuit 12 is composed of a bandpass filter 14 that passes the frequency f ₀ that is the output of the oscillator 10, an amplifier 15 that amplifies the output, and a rectification and smoothing circuit 16 that rectifies and smoothes the output. When the output frequency of 10 changes from the frequency f ₀ , there will be no output, and the following main relay MR will fall.

The brake command circuit 13 outputs a brake command to apply the brakes because the main relay MR has fallen.

A total of two inspection units are provided on the running path 3: a combination of receiving antenna A ₁ and beacon C ₁ and a combination of receiving antenna A ₂ and beacon C ₂ . Receiving antenna A ₁ and beacon C ₁ , which also functions as a control antenna _, are installed in this order with an interval of L ₁ in the direction of train 1's progress. C ₂ are similarly installed at intervals of L ₂ .

Each of the receiving antennas A ₁ and A ₂ is a known circuit in which a coil, a capacitor, and a load resistor are connected in parallel as shown in _FIG .
Connected to 20 ₂ .

As shown in Fig. 3, each ground element C ₁ and C ₂ is a known circuit in which operating contacts of control relays QR _{1 and} QR2, which will be described later, are connected in parallel to a resonant circuit in which a coil and a capacitor are connected in parallel. .

The checking circuit 4 calculates the time it takes for the onboard element 11 of the train 1 to reach the beacon C ₁ which also functions as a control element from the receiving antenna A ₁ or the time it takes for the onboard element 11 of the train 1 to reach the beacon C ₂ from the receiving antenna A ₂ . It is determined whether each time is longer than a predetermined time, and when it is shorter than the predetermined time, the relay contact is opened to enable the resonance circuit of ground elements C ₁ and C ₂ to provide stop information to the onboard device.

As shown in FIG. 3, the verification circuit 4 selects a signal with a frequency f ₀ from among the signals received by the receiving antennas A ₁ and A ₂ in addition to the transformers 20 ₁ and 20 ₂ , amplifies it, and rectifies it. A smoothing processing circuit 21, a timer 22 that is triggered by its output signal and outputs a time-up signal after a certain period of time, a timer relay TMR that is driven by the output signal of this timer, and counts the number of times the timer relay operates, that is, the time-up signal. A semiconductor counter 23 that operates according to the count value of the counter 23, and a plurality of (three in the illustrated example) counter relay groups COR ₀ , COR ₁ ,
COR ₂ , the counter 23 and counter relay
A check circuit 24 for checking failures in COR ₀ , COR ₁ , and COR ₂ , a check relay CKR driven by the output signal of this check circuit 24, and a receiving antenna connected to the input side of the processing circuit 21 are connected to the counter. A switching circuit 25 that switches according to the contact conditions of relays COR ₀ and _{COR 1} , and a control relay that individually controls ground elements C ₁ and C 2 according to the contact conditions of the counter relays COR ₁ and COR ₂ and check relay CKR.
QR ₁ , QR ₂ and a set relay STR for setting the counter 23.

The processing circuit 21 is a known circuit that includes a bandpass filter 26 whose passband is frequency f ₀ , an amplifier 27 that amplifies its output signal, and a rectifier and smoothing circuit 28 that rectifies and smoothes the output signal. Secondary coils 20 ₁ and 20 ₂ are connected to the input terminal of a bandpass filter 26 via a switching circuit 25 .

The timer 22 is triggered by the output signal of the processing circuit 21, and outputs a signal for a predetermined time after a predetermined time.

The counter 23 is a known circuit made of semiconductor elements such as diodes and transistors, and the counting signal is input to the signal input terminal via the operating contact of the timer relay TMR, and the set signal is input to the operating contact of the set relay STR. It is input to the set terminal via the contact. This counter 23 is
Counting is possible while the set relay STR is operating, and when the timer relay TMR operates in this state, the count value becomes "1" and the first output terminal
OUT ₁ becomes output, then timer relay again
When the TMR operates, the count value becomes “2” and the second
Output terminal OUT ₂ becomes output.

Counter relay COR ₁ is driven by a signal at the first output terminal of counter 23 , and counter relay COR ₂ is driven by a signal at the second output terminal of counter 23 .

In the illustrated example, the counter relay COR ₀ is configured to be energized via the operating contact of the set relay STR and the drop contact of each counter relay COR ₁ and COR ₂ , but if the count value of the counter 23 is It may be configured to operate with the output signal of the counter 23 at times other than "1" and "2".

The check circuit 24 includes each counter relay.
Signals for operating COR ₀ , COR ₁ , and COR ₂ are individually input to the input terminals, and an output is provided only when only one of these counter relays is operating.

Once the check relay CKR operates when the set switch SW is pressed down, it continues to operate under normal conditions because it is connected to the output terminal of the check circuit 24 via a self-holding operating contact. Also, when the counter 23 is not operating, the set relay
The voltage applied through the falling contact of the STR keeps it operating normally.

The switching circuit 25 connects the operating contact of the counter relay COR ₀ to the secondary coil of the transformer 20 ₁ and the processing circuit 2.
1, and the operating contact of counter relay COR ₁ is connected between the secondary coil of transformer 20 ₂ and the processing circuit 21.
It is configured between the

Control relay QR ₁ is energized through the operating contacts of counter relay COR ₁ and check relay CKR in series, and control relay QR ₂ is energized through the operating contacts of counter relay COR 1 and check relay CKR.
Power is applied in series through each operating contact of COR ₂ check relay CKR.

The set relay STR is energized and operates under conditions such as train 1 entering a closed section where the speed check device is installed or a speed check device installation area, and the set relay STR is energized and operates when the train 1 has the speed check device installed. The vehicle is cut off and falls due to a blocked section or the area where the speed checking device is installed.

Next, the operation of the above device will be explained with reference to FIG.

The oscillator 10 of the on-board device always oscillates at a frequency of f ₀ , so the main relay MR operates and no brake command is output. Further, in the ground speed check device, when the start switch SW is closed while the set relay STR is falling, the check relay CKR is energized via the falling contact of the set relay STR. In this state, each counter relay COR ₀ , COR ₁ , COR ₂
And each control relay QR ₁ and QR ₂ have fallen.

Therefore, ground wires C ₁ and C ₂ are enabled.
In addition, the check circuit 24 has no signal because none of the counter relays COR ₀ , COR ₁ , and COR ₂ are energized;
CKR is energized through its operating contact and the drop contact of the set relay STR in series.

As train 1 runs, when set relay STR operates at time (t ₁ ), counter relay
COR ₀ is energized through the operating contact of set relay STR and the drop contacts of counter relays COR ₁ and COR ₂ . As a result, the switching circuit 25 connects the receiving antenna _A1 to the input side of the processing circuit 21, and the check circuit 24 has an output, so that the check relay CKR continues to operate.

As the train 1 progresses, when the onboard child 11 reaches the receiving antenna A ₁ at time (t ₂ ), the signal with the frequency f ₀ is received by the receiving antenna A ₁ and the signal with the frequency f ₀ is processed. Since it is input to the circuit 21, the timer 22
is triggered and outputs a signal for a certain period of time after a certain period of time, and as a result, timer relay TMR operates for a certain period of time.

When timer relay TMR operates, counter 2
3 becomes “1” and counter relay COR ₁ operates, so counter relay COR ₀ falls. Therefore, the check circuit 24 maintains the output state.

When the counter operates, the switching circuit 25 switches the receiving antenna A ₂ from the processing circuit ₂ instead of the receiving antenna A 1.
Connect to 1.

Furthermore, when counter relay COR ₁ operates, control relay QR ₁ operates, which short-circuits ground element C ₁ and makes it ineffective. Therefore, the time from the time the onboard child 11 reaches the receiving antenna A ₁ to the time it reaches the ground child C ₁ is the same as the time from when the onboard child 11 reaches the receiving antenna A ₁ until the control relay QR ₁ operates. within the time (T ₂ ), the onboard device 2 determines that the oscillation frequency of the oscillator 10 is equal to the resonance frequency of the ground element C ₁ (≠
f ₀ ), main relay MR drops and outputs a brake command. However, the time (T ₁ )
When the onboard device 11 reaches the beacon C ₁ after the elapsed time, the onboard device 2 detects that the oscillator 10 continues to oscillate at the frequency f ₀ because the beacon C ₁ has been short-circuited and has become invalid. , main relay MR continues to operate,
Does not output brake command.

As the train 1 progresses, when the onboard child 11 reaches the receiving antenna A ₂ at time (t ₃ ), a signal of frequency f ₀ is received by the receiving antenna A ₂ and sent to the processing circuit 2.
1, the timer 22 is triggered again and outputs a signal for a certain period of time (T ₁ ) after a certain period of time (T 1 ).
As a result, timer relay TMR operates again for a certain period of time.

When timer relay TMR operates, counter 2
3 becomes “2”, which causes counter relay COR ₂ to operate and counter relay
Since COR ₁ falls, the switching circuit 25 disconnects the receiving antenna A ₂ from the processing circuit 21.

Also, control relay QR ₁ is counter relay COR ₁
When the ground element C1 falls, the ground element _C1 is activated, and the control relay _QR2 is activated by the activation of the counter relay _COR2 , thereby disabling the earth element _C2 . Therefore, the time from when the onboard shelving element 11 reaches the receiving antenna A ₂ until it reaches the wayside element C ₂ (i.e., the running time of the train) is controlled from the time when the onboard shelving element 11 reaches the receiving antenna A ₂ . relay QR ₂
If it is within the time (T ₂ ) until the main relay MR operates, the onboard device 2 will cause the main relay MR to fall and output a brake command as described above, and after the time (T ₂ ), the main relay MR will Continues operation and does not output brake command.

When a train passes at time ( _t4 ) and the set relay STR falls, the second
Since the output OUT ₂ becomes non-output, the counter relay COR ₂ falls, thereby causing the control relay QR ₂
will fall and activate ground element C ₂ .

When counter relay COR ₂ falls, check circuit 24 checks all counter relays COR ₀ , COR ₁ ,
Since COR ₂ is in a de-energized state, there is no signal, but check relay CKR is energized through its own operating contact and the falling contact of set relay STR, and maintains its operating state.

Next, one embodiment of the check circuit 24 shown in FIG. 5 will be described.

This check circuit 24 includes a generator 30 of an alternating current signal of a constant frequency, a transistor 31 to which the alternating current signal is input to the base, a transformer 32, and a rectifier circuit 33 provided on the output side of this transformer.
It includes resistors 34 and 35 connected in series to each relay COR ₀ , COR ₁ , and COR ₂ . Each counter relay COR ₀ , COR ₁ , COR ₂ has resistance 34, 3 on the negative side.
It is connected to the negative side power supply (-V) via 5,
Check relay CKR is connected to the output side of rectifier circuit 33. The base of the transistor 31 is connected between the resistors 24 and 35 as well as the alternating current signal generator 30, and the collector is connected to the positive power supply (+V) via the primary coil of the transformer 32. The emitter is connected to ground (0V).

Note that instead of inputting the drive current flowing through the counter relays COR ₀ , COR ₁ , and COR ₂ to the check circuit 34 , the current is input directly to the check circuit 24 through the contacts of the counter relays COR ₀ , COR ₁ , and COR ₂ . You can do it like this.

In this check circuit 24, the transistor 31 connects all counter relays COR ₁ , COR ₁ ,
When COR ₂ is not energized, the base voltage is biased to the negative side (-V) and tries to change in the cut-off region as shown at 36 in Fig. 6, but it cannot change and remains off. , AC signals are not transmitted and there is no output. Also, transistor 3
1, even when two or more counter relays are energized, the base voltage becomes the voltage of the sum of the currents flowing through those counter relays, and the reference numeral 37 is shown in FIG.
As shown in , it is heavily biased towards the positive side and attempts to change in the saturation region, but is unable to do so and no AC output is produced. As a result, even if all the counter relays are not energized, the check circuit 24 has no AC output because the transistor 31 remains off, and if two or more counter relays are energized at the same time, the transistor 31 remains off. 31 remains on, so there is no AC output. However, when only one counter relay is energized, the base voltage of the transistor 31 is appropriate as shown by reference numeral 38 in FIG. Result transformer 32
An AC signal corresponding to the secondary side of the circuit is induced, the check circuit 24 becomes output, and the check relay
CKR is driven and operates.

The present invention is applicable not only to a device using a resonant circuit consisting of a coil and a capacitor as the receiving antennas A ₁ and A ₂ , but also to a device using loop coils as the receiving antennas A ₁ ′ and A ₂ ′ as shown in FIG. It can also be applied to the equipment used. Of course, the present invention can be applied not only to a device that checks the speed at two points, but also to a device that checks the speed at three or more points by increasing the number of stages of the counter 23. Furthermore, the check circuit 24
However, a circuit with a different configuration may be used as long as the circuit does not output when the counter 23 is out of order.

Effects of the Invention As described above, the present invention has a receiving antenna that receives information from an on-board device and a beacon that provides stop information to the on-board device when the reference speed is exceeded, in a direction corresponding to the assumed reference speed in the train traveling direction. A plurality of combinations installed at intervals are provided at intervals in the train traveling direction, and a certain period of time elapses on the output side of a processing circuit that determines the presence or absence of a received signal of a predetermined frequency from the on-board device at the receiving antenna. A timer that outputs a time-up signal later and a counter that counts the time-up signal are provided, and the ground element corresponding to the state of the counter relay group corresponding to the count value of this counter is configured to send stop information to the onboard device before time-up. , and detects that only one of the counter relay groups is operating to the speed check device of the automatic train stop device, which is configured to be controlled by a control relay so as to provide passing information after time-up. A check circuit and a check relay driven by the output signal of this check circuit are provided, and the operating contacts of this check relay are interposed in series with the energizing circuits for all control relays, so that if the counter malfunctions, The control relay does not operate due to the action of the check circuit and check relay,
The ground element is not disabled, and the security of the device is improved. Therefore, even if a known semiconductor circuit is used as the counter, the security is sufficiently high.

Note that when a known semiconductor circuit is used as the counter, the configuration becomes extremely simple.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an automatic train stopping device,
Fig. 2 is an electric circuit diagram showing an embodiment of the on-board device, Fig. 3 is an electric circuit diagram showing an embodiment of the speed checking device according to the present invention, and Fig. 4 is an explanation of the operation of the speed checking device. 5 is an electric circuit diagram showing one embodiment of the check circuit, FIG. 6 is an explanatory diagram of the operation of the same check circuit, FIG. 7 is a diagram showing another embodiment of the automatic train stopping device, and FIG. 1 is an electrical circuit diagram showing an example of a conventional speed checking device. 21... Processing circuit, 22... Timer, 23...
Counter, 24...Check circuit, A ₁ , A ₂ ,
A ₁ ′, A ₂ ′...Receiving antenna, C ₁ , C ₂ ... Ground coil,
QR ₁ , QR ₂ ...Control relay. COR ₁ , COR ₂ ... Counter relay, CKR... Check relay.

Claims (1)

[Scope of Claims] 1. A receiving antenna that receives information from an on-board device and a beacon that provides stop information to the on-board device when the inspection speed is exceeded are installed in the train traveling direction at intervals corresponding to the assumed inspection speed. A plurality of combinations are provided spaced apart from each other in the train traveling direction, and a time-up signal is sent after a certain period of time to the output side of a processing circuit that determines the presence or absence of a received signal of a predetermined frequency from the on-board device at the receiving antenna. A timer that outputs the time-up signal and a counter that counts the time-up signal are provided,
The above-mentioned ground transducer corresponding to the state of the counter relay group corresponding to the count value of this counter is controlled by the control relay so as to give stop information to the onboard device before time-up and passing information after time-up. The speed check device for the automatic train stop device configured includes a check circuit for detecting whether only one of the counter relay groups is operating, and a check relay driven by an output signal of the check circuit. A speed check device for an automatic train stop device, characterized in that the operating contacts of the check relay are interposed in series in the energizing circuits to all the control relays.