JPH0332503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a speed checking device for a variable frequency automatic train stopping device, and in particular, a receiving antenna for receiving information from an on-board device and a speed check device for an on-board device. The present invention relates to an improvement of a ground device for a speed checking device in which a plurality of combinations (inspection units) with wayside elements giving stop information are provided spaced apart in the running direction of a train.

Prior Art Conventionally, the ground equipment of this type of speed checking device generally has a receiving antenna such as a loop coil or a resonant circuit for receiving information from the on-board equipment, as shown in Fig. 8.
A ₁ , A ₂ , and ground elements C ₁ , C ₂ , which are resonant circuits that provide stop information to the on-board device when the reference speed is exceeded, are installed in the direction of train travel at intervals corresponding to the assumed reference speed. unit) are provided in plural sets spaced apart from each other in the train traveling direction, and the receiving antennas A ₁ ,
At _A2 , a timer 6 is connected to the output side of a processing circuit 5 which processes to determine the presence or absence of a received signal from the on-vehicle device of a predetermined frequency, and which is triggered by the output signal of this processing circuit 5 and outputs a time-up signal after a certain period of time has elapsed. A counter 7 is provided to count the number of operations of the timer relay TMR, which is driven by the timer relay TMR, and thus a time-up signal, and a counter relay group COR ₀ , COR ₁ , which operates in accordance with the count value of the counter 7 is provided.
By enabling or disabling the ground terminals C ₁ and C 2 by the relay contacts QR' _{1 and} QR' ₂ of the control relays QR ₁ and QR _{2, which operate according to the contact states of COR 2 and COR 3 , it is} possible to The system is configured to control the on-vehicle device so as to give stop information to the on-board device, and to give passing information after time-up. In other words, only when the time from when the onboard element reaches the receiving antennas A ₁ and A ₂ to when it reaches the beacon C ₁ and C ₂ is longer than a predetermined time, the beacon is disabled and the stop information is sent to the onboard equipment. I've learned not to give. Note that the counter 7 can be set according to external conditions using a set relay contact STR'. It should be noted that for each relay contact in each figure, an operating contact is indicated by a V-shaped mark, and a falling contact is indicated by an inverted V-shaped mark.

In addition, in order to handle signals from multiple receiving antennas in a single processing circuit, a hybrid transformer 8 is used to handle the signals from each receiving antenna additively (19th Railway Symposium Proceedings 336-340
(see p. 1982).

By the way, the conventional device uses, for example, the hybrid transformer 8 as described above in order to process signals from a plurality of receiving antennas. This is because when handling weak signals from the receiving antenna, it is more stable than switching using mechanical contacts or the like.

However, in devices using conventional hybrid transformers, in addition to the onboard components of trains equipped with on-board equipment, they also face powerful electrical equipment such as motors and choppers placed under the floor. Noise is also received, and this mixed noise may cause the device to malfunction.

Purpose of the Invention The present invention focuses on the fact that the received signals from each inspection unit arrive at the processing circuit in a prescribed order as the train progresses, and uses semiconductor elements to control the DC voltage of weak signals. The receiver is configured to selectively switch the receiving antenna by applying signal path switching technology, and therefore has a receiving antenna switching section that is simple in configuration, unaffected by noise, and highly reliable. An object of the present invention is to provide a speed checking device for an automatic train stopping device.

Structure of the Invention In order to achieve the above object, the present invention provides a receiving antenna that receives information from an on-board device and a beacon that provides stop information to the on-board device when the reference speed is exceeded, in the direction of train travel at an assumed reference speed. A plurality of combinations installed at corresponding intervals are provided at a distance from each other in the direction of train travel, and a fixed circuit is provided on the output side of a processing circuit that processes to determine the presence or absence of a received signal of a predetermined frequency from the on-board device at the receiving antenna. A timer that outputs a time-up signal after the elapse of time and a counter that counts the time-up signal are provided, and the ground element corresponding to the state of the counter relay group corresponding to the count value of this counter is sent to the onboard device before time-up to receive stop information. In the speed check device for an automatic train stop device configured to be controlled by a control relay so as to give passage information after time-up, the counter is configured with a semiconductor element, and the processing circuit of the receiving antenna group and Between,
A speed checking device for an automatic train stopping device is constructed by interposing a switching circuit using a semiconductor element for selecting only one of the receiving antennas depending on the state of the counter relay group and connecting it to the processing circuit.

Embodiments The present invention will be described below based on embodiments shown in the drawings.

FIG. 1 schematically shows a speed checking device of an automatic train stopping device, and 1 is a train equipped with an on-board device 2, which travels along a running path 3 from left to right in the figure. The speed of this train 1 is determined by the receiving antennas A ₁ , A ₂ and the ground coil C ₁ ,
Corresponding pairs of C ₂ (verification unit, A ₁ and C ₁ , A ₂ and
Verification is performed using ground equipment consisting of C ₂ ) and verification circuit 4.

As shown in FIG. 2, the on-board device 2 includes an oscillator 10 that normally oscillates at a frequency f ₀ and this oscillator 1.
0 as a feedback circuit and installed at the bottom of the front of the train 1, a processing circuit 12 that selects, amplifies, rectifies and smoothes the signal of frequency f ₀ from the oscillator 10, and its output signal. It has an operating main relay MR, and the operating contacts of the main relay MR are used as a brake command circuit 13.

The processing circuit 12 is composed of a bandpass filter 14 that passes the frequency f ₀ that is the output of the oscillator 10, an amplifier 15 that amplifies the output, and a rectification and smoothing circuit 16 that rectifies and smoothes the output. When the output frequency of 10 changes from the frequency f ₀ , there will be no output, and the following main relay MR will fall.

The brake command circuit 13 outputs a brake command to apply the brakes because the main relay MR has fallen.

A total of two inspection units are provided on the running path 3: a combination of a receiving antenna A ₁ and a beacon C ₁ and a combination of a receiving antenna A ₂ and a beacon C ₂ . A receiving antenna A ₁ and a beacon C ₁ which also serves as a control antenna are installed in this order with an interval of L ₁ in the direction of train 1's progress, and a receiving antenna A ₂ and a beacon C ₂ are installed apart from this reference unit. are similarly placed at an interval of L ₂ .

Each of the receiving antennas A ₁ and A ₂ is a known circuit in which a coil, a capacitor, and a load resistor are connected in parallel as shown in _FIG .
Connected to 30 ₂ .

As shown in Fig. 3, each ground element C ₁ and C ₂ is a known circuit in which operating contacts of control relays QR _{1 and} QR2, which will be described later, are connected in parallel to a resonant circuit in which a coil and a capacitor are connected in parallel. .

The checking circuit 4 determines the time required for the onboard element 11 of the train 1 to reach from the receiving antenna A ₁ to the ground element C ₁ serving as a control element, or the time required for the onboard element 11 of the train 1 to reach the ground element C ₂ from the receiving antenna A ₂ for a predetermined time. It is determined whether or not the time is longer than the predetermined time, and if it is shorter than the predetermined time, the relay contact is opened and the resonant circuit of ground elements C ₁ and C ₂ is enabled, thereby giving stop information to the onboard device.

As _shown in _{FIG .}
a processing circuit 20 that selects, amplifies, rectifies and smoothes a signal, and a timer 21 that is triggered by the output signal and outputs a time-up signal after a certain period of time.
, a timer relay TMR driven by the output signal of this timer, and a counter 22 that counts the number of times the timer relay operates, that is, a time-up signal.
and a group of multiple (three in the illustrated example) counter relays that operate according to the count value of the counter 22.
COR ₀ , COR ₁ , COR ₂ and the receiving antenna connected to the input side of the processing circuit 20 are connected to the counter relay.
Switching circuit 2 that switches depending on the contact conditions of COR ₀ and COR ₁
3, control relays QR ₁ and QR 2 that individually control the ground wires C ₁ and C ₂ based on the contact conditions of the counter relays COR _{1 and COR 2 ,} and a set relay STR for setting the counter 22. There is.

The processing circuit 20 is a known circuit that includes a bandpass filter 24 whose passband is frequency f ₀ , an amplifier 25 that amplifies its output signal, and a rectification and smoothing circuit 26 that rectifies and smoothes its output signal.

The timer 21 is triggered by the output signal of the processing circuit 20, and outputs a signal for a predetermined time after a predetermined time.

The counter 22 is a known circuit made of semiconductor elements such as diodes and transistors, and the counting signal is input to the signal input terminal via the operating contact of the timer relay TMR, and the set signal is input to the operating contact of the set relay STR. It is input to the set terminal via the contact. This counter 22 is
Counting is possible while the set relay STR is operating, and when the timer relay TMR operates in this state, the count value becomes "1" and the first output terminal
OUT ₁ becomes output, then timer relay again
When the TMR operates, the count value becomes “2” and the second
Output terminal OUT ₂ becomes output.

Counter relay COR ₁ is driven by a signal at the first output terminal of counter 22 , and counter relay COR ₂ is driven by a signal at the second output terminal of counter 22 .

Note that, in the illustrated example, counter relay COR ₀ is configured to be energized via the operating contact of set relay STR and the drop contact of each counter relay COR ₁ and COR ₂ , but if the count value of counter 22 is It may be configured to operate with the output signal of the counter 22 at times other than "1" and "2".

The switching circuit 23 uses semiconductor elements, and includes two pairs of transformers 30 ₁ , 31 ₁ , 30 ₂ , 31 ₂ respectively corresponding to the receiving antennas A ₁ and A ₂ and two pairs of semiconductor diodes 32 _{1 .} ,33 ₁ ,32 ₂ ,33 ₂
and operating contacts of counter relays COR ₀ and COR ₁ . The primary coils of the transformers 30 ₁ , 30 ₁ are connected to the corresponding receiving antennas A ₁ , A ₂ , the secondary coils are connected to the primary coils of the transformers 31 ₂ , 31 ₂ , and the secondary coils of the transformers 31 1 , 31 ₂ are connected to the corresponding receiving antennas _{A 1} , A 2 . The next coil is connected to a bandpass filter 24 of the processing circuit 20. Each diode 32 ₁ , 33 ₁ , 32 ₂ ,
33 ₂ is inserted between the secondary coils of the corresponding transformers 30 ₁ and 30 ₂ and the primary coils of the transformers 31 ₁ and 31 ₂ , respectively. The middle points of the secondary coil of the transformer 30 ₁ and the primary coil of the transformer 31 ₁ are connected to the DC power supply 34 via the operating contact of the counter relay COR ₀ , and the secondary coil of the transformer 30 ₂ and the middle point of the primary coil of the transformer 31 ₂ Each midpoint of the primary coil is connected to a DC power supply 34 via an operating contact of a counter relay _COR1 . The current value of the DC power supply 34 is a value that makes the diodes 32 ₁ , 33 ₁ , 32 ₂ , 33 ₂ conductive, but the current value of the transformer 30 ₁ , 31 ₁ ,
30 ₂ and 31 ₂ have DC currents flowing in opposite directions, so they do not saturate, and there is no problem in signal conduction.

Also, control relay QR ₁ is counter relay COR ₁
energized through the operating contacts and also the control relay
QR ₂ is energized via the operating contacts of counter relay COR ₂ .

The set relay STR is energized and operates under conditions such as train 1 entering a closed section where the speed check device is installed or a speed check device installation area, and the set relay STR is energized and operates when the train 1 has the speed check device installed. The vehicle is cut off and falls due to a blocked section or the area where the speed checking device is installed.

Next, the operation of the above device will be explained with reference to FIG.

The oscillator 10 of the on-board device always oscillates at a frequency of f ₀ , so the main relay MR operates and no brake command is output. In addition, since the set relay STR of the ground speed check device has fallen, each counter relay COR ₀ , COR ₁ ,
COR ₂ and each control relay QR ₁ and QR ₂ have fallen. Therefore, the diode 32 ₁ of the switching circuit 23,
Since no forward bias is applied to 33 ₁ , 32 ₂ , 33 ₂ , each diode remains off. Therefore, the receiving antennas A ₁ and A ₂ are connected to the processing circuit 2.
0 and receiving antenna A ₁ or A ₂
Even if it receives noise, it will not be input to the processing circuit 20.

As train 1 runs, when set relay STR operates at time (t ₁ ), counter relay
COR ₀ is energized through the operating contact of set relay STR and the drop contacts of counter relays COR ₁ and COR ₂ . Thereby, in the switching circuit 23, the diodes 32 ₁ and 33 ₁ are biased in the forward direction by the DC power supply 34, and the receiving antenna A ₁ is connected to the processing circuit 20. However, switching circuit 23 disconnects receive antenna A ₂ from processing circuit 20 because diodes 32 ₂ and 33 ₂ are not forward biased.

As the train 1 travels, when the onboard child 11 reaches the receiving antenna A ₁ at time (t ₂ ), both the diodes 32 ₁ and 33 ₁ are turned on, so the frequency f ₀
is received by the receiving antenna A ₁ and has a frequency f ₀
The signal is input to the processing circuit 20, and the timer 21 is triggered to output a signal for a certain period of time after a certain period of time, and as a result, the timer relay TMR operates for a certain period of time.

When timer relay TMR operates, counter 2
Since the content of 2 becomes "1" and counter relay COR ₁ operates, counter relay COR ₀ falls.

When the counter relay COR ₁ operates and the counter relay COR ₀ falls, the switching circuit 23 applies a forward bias to the diodes 32 ₂ and 33 ₂ to connect the receiving antenna A ₂ to the processing circuit 21, and also connects the receiving antenna A 2 to the processing circuit ₂₁ . , 33 ₁ becomes unbiased and disconnects the receiving antenna A ₁ from the processing circuit 20 .

Furthermore, when counter relay COR ₁ operates, control relay QR ₁ operates, which short-circuits ground element C ₁ and makes it ineffective. Here, the time from the time when the onboard child 11 reaches the receiving antenna A ₁ to the time when it reaches the wayside child C ₁ (that is, the running time of the train) is the time from when the onboard child 11 reaches the receiving antenna A ₁ to the time when the train reaches the ground child C 1. If it is within the time (T ₂ ) until QR ₁ operates, in this case, the ground coil 11 is not short-circuited and disabled, so the onboard device 2 detects that the oscillation frequency of the oscillator 10 is the resonance frequency of the ground coil. As a result, main relay MR drops and outputs a brake command. However, since the ground element _C1 is short-circuited and becomes invalid after the time ( _T2 ) has elapsed, the oscillator 10 of the onboard device 2 continues to oscillate at the frequency _f0 , and the main relay MR continues to operate.

As the train 1 progresses, when the onboard child 11 reaches the receiving antenna A ₂ at time (t ₃ ), a signal of frequency f ₀ is received by the receiving antenna A ₂ and sent to the processing circuit 2.
0, the timer 21 is triggered again and outputs a signal for a certain period of time (T ₁ ) after a certain period of time (T 1 ).
As a result, timer relay TMR operates again for a certain period of time.

When timer relay TMR operates, counter 2
2 becomes “2”, which causes counter relay COR ₂ to operate and counter relay
COR ₁ falls and switching circuit 23 becomes diode 32
₂ , 33 ₂ becomes unbiased and disconnects the receiving antenna A ₂ from the processing circuit 20.

Also, control relay QR ₁ is counter relay COR ₁
When the ground element C1 falls, the ground element _C1 is activated, and the control relay _QR2 is activated by the activation of the counter relay _COR2 , thereby disabling the earth element _C2 . Therefore, the time from when the onboard shelving element 11 reaches the receiving antenna A ₂ until it reaches the wayside element C ₂ (i.e., the running time of the train) is controlled from the time when the onboard shelving element 11 reaches the receiving antenna A ₂ . relay QR ₂
If it is within the time (T ₂ ) until the main relay MR operates, the onboard device 2 will cause the main relay MR to fall and output a brake command as described above, and after the time (T ₂ ), the main relay MR will Sustain the action.

When a train passes at time (t ₄ ) and the set relay STR falls, the counter 23 stops and the counter relay COR ₂ falls, which causes the control relay QR ₂ to fall and enable the ground wire C ₂ . and a brake command is issued.

The above device includes diodes 32 ₁ , 33 ₁ , 32
₂ , 33 ₂ are not forward biased, the received signals of the receiving antennas A ₁ , A ₂ will not enter the processing circuit and therefore one receiving antenna e.g. A ₂ is not connected to the processing circuit 20 of the other Even if the receiving antenna _A1 receives noise, it will not be affected by this noise. In addition, diodes 32 ₁ , 33
₁ , 32 ₂ , and 33 ₂ have an open-circuit failure, the signal of frequency f ₀ will not be input to the processing circuit 20, so the timer relay and, by extension, the control relays QR ₁ and QR ₂ will not operate.
When the onboard child 11 reaches the corresponding ground child C ₁ , C ₂ , stop information is given to the onboard device 2 . Furthermore, when the diodes 32 ₁ , 33 ₁ , 32 ₂ , 33 ₂ are short-circuited, both the receiving antennas A ₁ and A ₂ are connected to the processing circuit 20, and therefore the input level to the processing circuit 20 is reduced. , timer 21 is not triggered and timer relay TMR and therefore control relays QR ₁ , QR ₂
doesn't work.

Switching can be performed not only by diodes but also by other semiconductors. FIG. 5 shows an embodiment of the switching circuit 39 using transistors instead of diodes, and each transistor 35 ₁ , 36 ₁ , 3
5 ₂ , 36 ₂ are resistors 37 ₁ , 38 ₁ , 37 ₂ , 38 ₂
Individually self-biased by In this switching circuit, when counter relay COR ₀ is operating, transistors 35 ₁ and 36 ₁ are turned on to connect receiving antenna A ₁ to processing circuit 20, and when counter relay COR 1 is operating, transistors 35 1 and 36 1 are turned on, and when counter relay COR ₁ is operating, transistors 35
₂ , 36 ₂ is turned on and connects the receiving antenna A ₂ to the processing circuit 20 . If the transistor has an open circuit failure, the signal with frequency f ₀ will not be input to the processing circuit 20, and if the transistor has a short circuit failure, both receiving antennas A ₁ and A ₂ will be connected to the processing circuit 20, and the input level to the processing circuit 20 will decrease. , timer relay TMR does not work.

FIG. 6 shows yet another embodiment of the switching circuit.
This switching circuit 40 includes an amplifier circuit using transistors 41 ₁ and 41 ₂ in addition to transformers 30 ₁ and 30 ₂ . The transistors 41 ₁ , 42 ₂ have bases connected to one end of the secondary coils of the transformers 30 ₁ , 30 ₂ via capacitors 42 ₁ , 42 ₂ , and emitters connected to the transformers 30 via resistors 46 ₁ , 46 ₂ .
The bases are connected to the other ends of _the secondary coils 44 ₁ , 44 ₂ and the collectors are resistors 45 _{1 ,} 45 ₂
It is connected to the positive side terminal of a DC power source (not shown) via operating contacts of counter relays COR ₀ and COR ₁ , and to the processing circuit 20 via capacitors 43 ₁ and 43 ₂ .

In this switching circuit 40, when the counter relay COR ₀ is operating, the transistor 41 ₁ is operated to connect the receiving antenna A ₁ to the processing circuit 26, and when the counter relay COR ₁ is operating, the transistor 41 _{2 is} operated.
operates to connect the receiving antenna A ₂ to the processing circuit 26, and the signal at frequency f ₀ is amplified and sent to the processing circuit 20.
is input. In addition, transistors 41 ₁ , 41 ₂
However, regardless of whether the failure is an open circuit failure or a short circuit failure, the receiving antenna loses its amplification function.
The input level of the signal of frequency f ₀ from A ₁ and A ₂ to the processing circuit 26 decreases, and timer relay TMR does not operate.

The present invention is applicable not only to a device using a resonant circuit consisting of a coil and a capacitor as the receiving antennas A ₁ and A ₂ , but also to a device using loop coils as the receiving antennas A ₁ ′ and A ₂ ′ as shown in FIG. It can also be applied to the equipment used. Of course, the present invention can be applied not only to a device that checks the speed at two points, but also to a device that checks the speed at three or more points by increasing the number of stages of the counter 23. Furthermore, other semiconductor switching elements such as thyristors may be used instead of diodes and transistors. Further, the counter may be a known semiconductor circuit, but may also be composed of relay contacts.

Effects of the Invention As described above, the present invention provides a speed checking device with the following features:
Since the switching circuit for switching the receiving antenna connected to the processing circuit is constructed using semiconductor switching elements, the construction is significantly simpler than conventional devices using relay contacts or hybrid transformers. Furthermore, as long as the switching element is not turned on, even if noise is input to the corresponding receiving antenna, it will not be affected by the noise. Furthermore, even if a switching element fails, the output is cut off and the train is controlled to stop, making it a fail-safe device, and therefore highly reliable.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an automatic train stopping device,
Fig. 2 is an electric circuit diagram showing an embodiment of the on-board device, Fig. 3 is an electric circuit diagram showing an embodiment of the speed checking device according to the present invention, and Fig. 4 is an explanation of the operation of the speed checking device. Fig. 5 is an electric circuit diagram showing another embodiment of the switching circuit, Fig. 6 is an electric circuit diagram showing still another embodiment of the switching circuit, and Fig. 7 is another embodiment of the automatic train stopping device. FIG. 8 is an electric circuit diagram showing an embodiment of a conventional speed checking device. 20...processing circuit, 21...timer, 22...
Counter, 23, 39, 40...Switching circuit, 32
₁ , 33 ₁ , 33 ₂ , 32 ₂ , 35 ₁ , 36 ₁ , 35 ₂ ,
36 ₂ , 41 ₁ , 41 ₂ ... semiconductor element, A ₁ , A ₂ ,
A ₁ ′, A ₂ ′...Receiving antenna, C ₁ , C ₂ ... Ground coil,
COR ₀ , COR ₁ , COR ₂ ...Counter relay,
QR ₁ , QR ₂ ...Control relay.

Claims (1)

[Scope of Claims] 1. A receiving antenna that receives information from an on-board device and a beacon that provides stop information to the on-board device when the inspection speed is exceeded are installed in the train traveling direction at intervals corresponding to the assumed inspection speed. A plurality of combinations are provided spaced apart from each other in the train traveling direction, and a time-up signal is sent after a certain period of time to the output side of a processing circuit that determines the presence or absence of a received signal of a predetermined frequency from the on-board device at the receiving antenna. a timer that outputs the time-up signal and a counter that counts the time-up signal,
The above-mentioned ground transducer corresponding to the state of the counter relay group corresponding to the count value of this counter is controlled by the control relay so as to give stop information to the onboard device before time-up and passing information after time-up. In the speed checking device for an automatic train stopping device configured, the counter is configured with a semiconductor element, and between the receiving antenna group and the processing circuit,
A speed checking device for an automatic train stop device, characterized in that a switching circuit using a semiconductor is interposed to select only one of the receiving antennas according to the state of the counter relay group and connect it to the processing circuit. .