JPH0736280B2 - Shift register - Google Patents

Description

TECHNICAL FIELD The present invention relates to a shift register that can be reset by an external signal.

[Prior Art] FIG. 4 is a diagram showing a conventional n-stage shift register having a reset function.

In the figure, a register 40 has n flip-flops with reset terminals connected in series. Each flip-flop has an input terminal, an output terminal, a clock terminal, and a reset terminal. When a clock pulse is input to the clock terminal, the data input to the input terminal is output from the output terminal. . Then, when a "0" level signal is input to the reset terminal, the content of the flip-flop is reset to "0".

The clock terminal of each flip-flop is commonly connected to the external clock terminal, and the clock signal CK is input to the external clock terminal.

The reset terminal of each flip-flop is commonly connected to the external reset terminal, and the reset signal ▲ ▼ is input to the external reset terminal.

Data DI is input to the input terminal of the first-stage flip-flop, and data Y is output from the output terminal of the last-stage flip-flop.
Is output.

First, the content of all the flip-flops of the register 40 is reset to "0" by the reset signal ▲ ▼. Then, each time one clock pulse is input, one data DI is input from the input terminal, and the data held in each flip-flop is sequentially shifted to the subsequent flip-flops, and the data is output from the output terminal. One is output as Y. Therefore, after n "0" s are output from the output terminal of the final stage flip-flop, the data DI input to the input terminal is sequentially output from the output terminal.

[Problems to be Solved by the Invention] The flip-flop with a reset terminal used in the shift register has a larger number of gates because it can be reset as compared with a flip-flop without a reset terminal.
Since the shift register uses flip-flops with reset terminals for all bits, the number of gates is significantly increased as compared with a shift register having no reset function.

Moreover, since many reset terminals are connected to the external reset terminal, a large load is applied, and the time required for resetting increases.

These phenomena become more remarkable as the resist length becomes longer.

Therefore, an object of the present invention is to provide a shift register in which the number of gates required for the reset function does not increase even if the resist length becomes long, and the load on the reset terminal is small.

[Means for Solving Problems] A shift register according to the present invention is a shift resist that can be reset by an external signal, and includes first and second register sections, a counter section, and first and second And an output control unit.

The first register unit is composed of a plurality of flip-flops connected in series, and each time a clock pulse is input,
The data signal input to the first-stage flip-flop is sequentially transferred to the subsequent-stage flip-flop and output from the final-stage flip-flop.

The second register section is composed of a plurality of flip-flops connected in series, and each time a clock pulse is input,
The signals input to the first-stage flip-flops are sequentially transferred to the subsequent-stage flip-flops and output from the final-stage flip-flops.

The counter unit has a reset function, and outputs a predetermined signal after being input with a predetermined number of clock pulses after being reset by an external signal.

The first output control section is for deriving an output signal of the first register section to an input of the second register section in response to a predetermined signal from the counter section.

The second output control section is for deriving the output signal of the second register section as an output data signal in response to a predetermined signal from the counter section.

[Operation] In the shift register according to the present invention, first, when the counter section is reset, the output signals of the counter section cause the first and second output control sections to output corresponding outputs of the first and second register sections, respectively. The signal is not derived. This state is maintained until a predetermined number of clock pulses are input to the counter section. On the other hand, in each of the first and second register units, each time a clock pulse is input, a signal is input to the first-stage flip-flop, and the signal held by each flip-flop is sequentially transferred to the subsequent-stage flip-flop. It is output from the output flip-flop at the final stage.

When a predetermined number of clock pulses are input, a predetermined signal is output from the counter section, whereby the first and second output control sections cause the final stage flip-flops of the first and second register sections, respectively. Will be derived.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a shift register according to the present invention.

In this embodiment, a specific number of counters, for example, a 2m-ary counter is used to configure a shift resister with an arbitrary number of stages, for example, n stages. Here, 2m + 1 <n <2m
^Let m be chosen to be ⁺¹ . This shift register has a first register 30 which is composed of 2m flip-flops without a reset function and a second register 30 which is composed of (n-2m-1) flip-flops which is not equipped with a reset function.
The register 31, a 2m-ary counter 32, a flip-flop 33 with a reset function, and a mask gate 34 composed of a 2-input AND gate.

Each of the flip-flops which does not have a reset function and which constitutes the first and second shift registers 30 and 31 has an input terminal, an output terminal and a clock terminal, and when a clock pulse is input to the clock terminal. The data input to the input terminal is output from the output terminal and held.

The output data DO _A of the first register 30 is the flip-flop 3
3, the output data DO _B of the flip-flop 33 is input to the input terminal of the second register 31, and the output data DO _C of the second register 31 is input to one input terminal of the mask gate 34. To be done. In addition, the first register 30,
The common clock signal CK is input to the clock terminals of the flip-flop 33, the second register 31, and the counter 32. Further, the output signal C of the counter 32 is input to the reset terminal of the flip-flop 33 and the other input terminal of the mask gate 34.

The 2m-ary counter 32 has a clock terminal, a reset terminal, and an output terminal, and is composed of m flip-flops 51 and (m-1) inverters 52, as shown in FIG. When the reset signal ▲ ▼ of “0” level is input, the 2m-adic counter 32 outputs the signal of “0” level until 2m clock pulses are input, and the m clock pulses are input. Then, a "1" level signal is output.

In this shift register, when the reset signal ▲ ▼ becomes "0" level, the output signal C of the counter 32 keeps "0" level and the flip-flop 33 becomes "0" level until 2m clock pulses are input. And the mask gate 34 outputs the signal Y of "0" level. During this time, the data DI input to the input terminal of the register 30 is shifted to the 2mth stage flip-flop of the register 30 immediately after reset, and the reset state of the flip-flop 33 is released when 2m clock pulses are input. Also, since (n-2m-1) <2m, (n-2m-
Each flip-flop of the 1-stage shift register 31 holds the “0” level output signal of the flip-flop 33.

Flip-flop 33 at the (2m + 1) th clock pulse
The output signal of “0” level is latched by the first stage flip-flop of the second register 31, and the output data DO _{A of} the first shift register 30 is latched by the flip-flop 33. Further, the output data DO _C of the second register 31 is output from the mask gate 34.

Thereafter, every time a clock pulse is input, DI is input from the input terminal of the first register 30 and the output data DO _B of the flip-flop 33 is sequentially input to the second register 31.
Will be shifted to. In this way ((2m + 1) +
(N−2m−1)), that is, the mask gate 34 outputs a signal Y of “0” level until n clock pulses are input, but after n clock pulses are input. Immediately after reset, the data DI input to the first register 30 is sequentially output.

The table shows the results of comparison between the conventional shift register with reset function and the shift register with reset function according to the present invention.

As shown in the table, when the number of stages n of the shift register is about 30, the shift register according to the present invention reduces the number of gates by about 3% as compared with the conventional shift register.
The ratio increases as the number of stages n increases, n = 512
Will reduce the number of gates by about 18%.

The rate of increase in the number of gates with respect to the shift register having no reset function also decreases as the number of stages n increases in the shift register according to the present invention, and n = 51.
With 2, the increase is about 2%.

The load on the external reset terminal is significantly reduced as compared with the conventional shift register because the reset signal is input only to the counter in the shift register of the present invention.

[Effects of the Invention] As described above, according to the present invention, since the flip-flops forming the register section do not require the reset function, it is possible to reduce the number of gates required for the reset function for each flip-flop. Moreover, since the reset signal is only input to the counter unit, the load on the external reset terminal does not increase.

Further, according to the present invention, even if a relatively large number of shift register stages are required, the shift register is divided into two serially connected register units, and therefore the registers can be reset. The number of stages of the counter for multiplying may be about half the number of stages of the entire shift register, and the number of gates required for resetting the shift register can be further reduced.

Further, according to the present invention, since the shift register is divided into two register portions, the time required for resetting can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a shift register according to the present invention, FIG. 2 is a diagram showing a conventional shift register, and FIG.
It is a figure which shows the structure of a 2m-ary counter. In the figure, 30 is a first register, 31 is a second register, 32 is a counter, 34 is a mask gate, 33 is a flip-flop with a reset function, CK is a clock signal, DI is input data, DO is output data, and Y is Indicates output data, ▲ ▼ indicates a reset signal, and C indicates an output signal.

Claims (1)

[Claims] 1. A shift register which can be reset by an external signal, wherein a plurality of flip-flops are connected in series, and an input data signal input to a first-stage flip-flop is sequentially input every time a clock pulse is input. A first register unit that transfers to the flip-flop of the subsequent stage and outputs from the flip-flop of the final stage and a plurality of flip-flops are connected in series. Every time a clock pulse is input, it is input to the flip-flop of the first stage. A second register unit for sequentially transferring a signal to a flip-flop in the subsequent stage and outputting it from the flip-flop in the final stage, and having a reset function, and after being reset by the external signal, a predetermined number of clock pulses are input. A counter unit that outputs a predetermined signal afterwards, and in response to the predetermined signal from the counter unit. A first output control unit for deriving an output signal of the first register unit to an input of the second register unit, and the second register unit in response to the predetermined signal from the counter unit. A second output control unit for deriving the output signal of the above as an output data signal.