JPH0426739B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In an electronic computer equipped with a hardware history information recording mechanism consisting of a random access memory (RAM), an address counter B, and a write data register, In order to resolve the shortage of performance evaluation measurements and measurement time, an address counter A dedicated to performance evaluation measurements of the computer, an adder, a mode latch for selecting a history recording mode and a performance evaluation measurement mode, and a A multiplexer (MPX) that uses a mode latch to change the address for the random access memory (RAM) and the input data for the adder, and a means for inputting the output of the adder to the random access memory (RAM). By providing this, the random access memory (RAM) for recording history information counts the performance evaluation measurement data of the computer.

[Industrial application field]

The present invention relates to a control method for counting performance evaluation measurement data of an electronic computer equipped with a hardware history information recording mechanism using a random access memory included in the history information recording mechanism.

Recent trends in electronic computers require products with even higher performance than before, but in order to achieve this, efficient design of both hardware and software is required, and extremely detailed performance evaluations are required. Measurement has become essential. Specifically, the number of measurements,
It is necessary to increase the measurement time.

However, there is also a strong demand for cost reduction, and a circuit system for performance evaluation measurement that can be realized with minimal addition of hardware is required.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a diagram illustrating a conventional history information recording mechanism and a performance evaluation measurement mechanism, where a indicates the history information recording mechanism and b indicates the performance evaluation measurement mechanism.

First, a conventional history information recording mechanism will be explained with reference to FIG.

As is clear from this figure, the so-called history information recording mechanism counts up an address counter 5 of a random access memory (RAM) 4 consisting of, for example, n bits x m words at the clock speed, and records the information in a predetermined hardware memory. The state of each point of the hardware, such as registers and flipflops (FF), is read as history data into the write data register 2 and stored at the corresponding address in the random access memory (RAM) 4, which is repeated to ensure that the hardware is always up to date. The condition was recorded.

On the other hand, the performance evaluation measurement mechanism of the computer shown in Figure b uses the K-bit (k<n) counter 1 corresponding to each performance evaluation measurement item.
0~ were provided, and each performance evaluation measurement data was counted independently in each counter 10~.

The performance evaluation measurement items (PA items) mentioned here include, for example, the address when accessing the main memory (MS) does not exist in the logical address-real address conversion table or the virtual address-real address conversion table. When accessing the main memory (MS), it is necessary to refer to the table stored in the main memory (MS), which directly affects the performance of the computer. Count the number of hits (number of non-hits).

In an electronic computer equipped with a cache memory, the access time varies greatly depending on whether or not target data and instructions exist in the cache memory, so the number of 'non-hits' is counted.

In recent electronic computers, instructions are executed through pipeline processing in order to improve processing performance. At this time, if there is a conflict between registers, the flow of the pipeline is disrupted and the expected performance is not achieved. Therefore, the number of collisions between the registers is counted. And so on.

Therefore, in order to improve the accuracy of the performance evaluation measurement, it is necessary to provide sufficient measurement items and measurement time.

However, as shown in the figure, the conventional performance evaluation measurement (PA) counters 10 to 10 are configured, for example, only with a k-bit counter circuit, so the number of counts is limited, and a sufficient number of measurement items and measurement times are required. There was a problem in that data could not be obtained and performance evaluation measurements of electronic computers could not be performed accurately.

In view of the above-mentioned conventional drawbacks, the present invention focuses on the fact that the capacity of random access memory (RAM) used in the history information recording mechanism is relatively large, and that history information is not necessary except at the time of a failure. , it is an object of the present invention to provide a method for performing performance evaluation measurements using a large capacity random access memory used in the history information recording mechanism.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of a performance evaluation measurement method for an electronic computer according to the present invention.

In the present invention, in an electronic computer equipped with a hardware history information recording mechanism composed of a random access memory (RAM) 4, an address counter B5, and a write data register 2, performance evaluation measurement of the computer is performed. Dedicated address counter A1, adder 3, and mode latch 9 for selecting history recording mode and performance evaluation measurement mode.
and multiplexers (MPX) 6, 7, 8 for switching the address for the random access memory (RAM) 4 and the input data for the adder 3 by the mode latch 9, and the output of the adder 3. is input to the random access memory (RAM) 4, and the random access memory (RAM) 4 for recording history information is configured to count the performance evaluation measurement data of the computer.

[Operation] That is, according to the present invention, in an electronic computer equipped with a hardware history information recording mechanism composed of a random access memory (RAM), an address counter B, and a write data register, the electronic computer In order to solve the problem of the number of performance evaluation measurements and the lack of measurement time, an address counter A dedicated to the performance evaluation measurement of the computer, an adder,
a mode latch for selecting a history recording mode and a performance evaluation measurement mode; a multiplexer (MPX) for switching an address for the random access memory (RAM) and input data for the adder by the mode latch; and the adder. By providing an input means for the random access memory (RAM), the output of the random access memory (RAM) for recording history information is provided.
Since it is designed to count the performance evaluation measurement data of an electronic computer, the capacity of the performance evaluation measurement counter only needs to be small, and since a large amount of data can be accumulated, long-term performance evaluation measurement is possible. This has the effect of improving evaluation accuracy.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
The above-mentioned FIG. 1 is a diagram showing an example of the configuration of a performance evaluation measurement method for an electronic computer according to the present invention, and includes an address counter A1, an adder 3, a mode latch 9, and multiplexers (MPX) 6, 7, 8 are the means necessary to carry out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In a normal state, the mode latch 9 of the present invention is reset, and each multiplexer (MPX) is selected to be on the 'H' side, that is, the counting mechanism functions as a history information recording mechanism.

In this state, the hardware history data of the computer concerned also changes at the clock speed.
The information is set in the write register 2 and stored moment by moment at the address specified by the address counter A1 of the random access memory (RAM) 4, functioning as an original history information recording mechanism.

Here, if the mode latch 9 is set to logic '1' from an operation panel (not shown), etc.
The multiplexers (MPX) 6, 7, and 8 are selected on the 'P' side, that is, so that the counting mechanism functions as a performance evaluation measurement mechanism.

In this state, the address of the random access memory (RAM) 4 is designated by the address counter B5 via the multiplexer (MPX) 8, and the address counter A1 counts performance evaluation measurement data.

The address counter A1 is prepared as many as the number of performance evaluation measurement items, and the data for each measurement item is counted every moment. is input.

Therefore, there is no need for a large k-bit counter as in the prior art, and it is sufficient to provide a number of bits that can be counted within a fixed period of time, for example, about 4 bits.

At this time, the performance evaluation measurement data previously stored in the random access memory (RAM) 4 is set in the write data register 2 via the multiplexer (MPX) 6, and is stored in the address counter A1. The adder 3 adds the current performance evaluation measurement data and the current performance evaluation measurement data stored in the same address. It functions so that data is stored at the address specified by address counter B5.

Therefore, the performance evaluation measurement items in the present invention are:
Number of words m in the random access memory (RAM) 4
The performance evaluation measurement data can also be taken from the random access memory (RAM) 4.
This means that only the number of bits can be counted, and a large number of measurement items can be measured over a long period of time.

As described above, the present invention focuses on the fact that the random access memory used in the history information recording mechanism has a relatively large capacity, and that history data is not used except when the computer fails. The present invention is characterized in that the random access memory is configured to store performance evaluation measurement data of the computer.

〔Effect of the invention〕

As explained above in detail, the computer performance evaluation measurement method of the present invention uses a hardware history information recording mechanism consisting of a random access memory (RAM), an address counter B, and a write data register. In order to solve the problem of the number of performance evaluation measurements of the computer and the lack of measurement time, an address counter A dedicated to the performance evaluation measurement of the computer, an adder, a history recording mode and a performance a mode latch that selects the evaluation measurement data; a multiplexer (MPX) that uses the mode latch to switch between an address for the random access memory (RAM) and input data for the adder; By providing an input means to the random access memory (RAM), the random access memory (RAM) for recording history information can count the performance evaluation measurement data of the computer. The counter only needs a small capacity and can accumulate a large amount of data, making it possible to perform performance evaluation measurements over a long period of time, which has the effect of improving evaluation accuracy.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a performance evaluation measurement method for a computer according to the present invention, and FIG. 2 is a diagram illustrating a conventional history information recording mechanism and a performance evaluation measurement mechanism. In the drawing, 1 is an address counter A, 2 is a write data register, 3 is an adder,
4 is random access memory (RAM), 5 is address counter B or address counter, 6-
Reference numeral 8 indicates a multiplexer (MPX), 9 a mode latch, and 10 to k-bit counters for performance evaluation measurement.

Claims (1)

[Claims] 1 Random access memory (RAM) 4, address counter B5, and write data register 2
In an electronic computer equipped with a hardware history information recording mechanism consisting of: an address counter A1 dedicated to performance evaluation measurement of the computer, an adder 3, a history recording mode and a performance evaluation measurement mode are selected. mode latch 9
and multiplexers (MPX) 6, 7, 8 for switching the address for the random access memory (RAM) 4 and the input data for the adder 3 by the mode latch 9, and the output of the adder 3. is input to the random access memory (RAM) 4, and the random access memory (RAM) 4 for recording history information is controlled to count performance evaluation measurement data of the computer. performance evaluation measurement method.