JPH0430190B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology and technology that is particularly effective when applied to electronic circuit devices.
The present invention relates to an effective technique that can be used to prevent electrostatic damage to gates.

[Background technology]

According to studies conducted by the present inventors, semiconductor integrated circuit devices, particularly MOS type semiconductor integrated circuit devices, are easily destroyed by static electricity applied from the outside. Therefore, as shown in FIG. 1, a resistor R is interposed in series between the input pad section P and the internal input circuit 20, and a
It has been proposed to form a protection circuit by inserting MOSFETQ1 in parallel. The resistance R is formed, for example, by a diffusion layer. Also for clamps
The operating threshold of MOSSFET Q1 is set so that it becomes conductive at a voltage higher than the normal signal level.

However, the inventors have found that the above-described circuit alone may not be sufficient to prevent damage caused by static electricity. For example, when high-energy static electricity is applied, the clamping MOSFET Q1 may not be able to sufficiently clamp it.

Therefore, as shown in FIG.
A parasitic MOSQ2 is formed on the side near the
A destruction prevention circuit has been proposed that utilizes MOSQ2 to release high-voltage static electricity applied to the input pad portion P. In this case, the drain D and gate G of the parasitic MOS Q2 have a resistance R made of a diffusion layer, etc.
Commonly connected to. Further, the potential Vs of the source S is fixed to the ground potential or power supply potential.

This parasitic MOSQ2 has two diffusion layers N ⁺ , N ⁺
This occurs because a channel is formed under the oxide film 12 when a metal electrode, for example, an aluminum electrode M, is provided on the field oxide film (LOCOS) 12 and the insulating film 14 between them.

In this case, one diffusion layer N ⁺ connects the drain D,
The other diffusion layer N ⁺ forms a source S, respectively.
Further, the aluminum electrode M forms the gate G. The threshold voltage of this parasitic MOS Q2 is considerably higher than that of a normally formed MOS. Therefore, when a voltage higher than the input signal level is applied to the input pad portion P, the parasitic MOS Q2 is rendered conductive, thereby preventing damage to the internal input circuit 20 and the like.

In addition, in FIG. 4, 10 indicates a semiconductor substrate. A guard ring 16 made of a diffusion layer is formed along the periphery of the semiconductor substrate 10 . The semiconductor substrate 10 is cut along a cutting line X along the guard ring 16.

By the way, according to the study conducted by the present inventor, it is clear that in the circuit described above, the parasitic MOSQ2 occupies a relatively large area around the input pad portion P, as can be seen from FIG. Summer. For this reason, the layout around the input pad part P becomes difficult, and the above-mentioned parasitic
It becomes impossible to allocate a sufficient layout area to MOSQ2. In the parasitic MOS Q2 whose layout area is thus restricted, even if a high voltage is applied to the input pad portion P, it will not be possible to sufficiently reduce the voltage. In other words, the function as an electrostatic damage prevention circuit is degraded.

[Purpose of the invention]

This invention was made in view of the above-mentioned problems, and its purpose is to prevent electrostatic damage caused by the pads provided close to the input pads without making the layout around the input pads difficult. Enables sufficient layout area to be given to the parasitic MOS for prevention, thereby ensuring the ability to prevent electrostatic discharge damage, and making effective use of the limited layout area of the semiconductor substrate. An object of the present invention is to provide an electrostatic damage prevention circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a circuit that prevents damage caused by static electricity applied to a semiconductor integrated circuit device from an input pad section, a resistor is provided in series between the input pad section and the internal input circuit, and a resistor is provided in series between the input pad section and the internal input circuit. There is a parasitic problem between the guard ring provided along the periphery of the board and the pad part above.
A MOS is formed, the drain of this parasitic MOS is connected to the pad part, and its source is connected to the guard ring, and when a high potential is applied to the pad part, the parasitic MOS becomes conductive and the internal This prevents damage to the input circuit, thereby providing sufficient layout area for the parasitic MOS for preventing electrostatic damage provided near the input pad without complicating the layout around the input pad. This achieves the purpose of making it possible to reliably obtain the function of preventing electrostatic discharge damage, and also to make it possible to effectively utilize the limited layout area of the semiconductor substrate.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 5 shows an embodiment of the electrostatic damage prevention circuit according to the present invention. Moreover, FIG. 6 shows an outline of the planar layout state. Furthermore, FIG. 7 shows the cross-sectional state in an abstract manner.

First, the circuits shown in FIGS. 5, 6, and 7 constitute a circuit that protects the internal input circuit 20 from damage caused by static electricity applied from the input pad portion P of the semiconductor integrated circuit device. The internal input circuit 20
It is composed of MOSFET. Furthermore, the internal circuit is F-MOS or N-MOS.
It constitutes DRAM (dynamic RAM).

A resistor R is interposed in series between the input pad section P and the internal input circuit 20. This resistance R is formed by the diffusion layer N ⁺ . A voltage clamping MOSFET Q1 is inserted in parallel to the internal input circuit 20 side of the resistor R. for this clamp
MOSFETQ1 is formed as a regular MOSFET. Its drain is the internal input circuit 20
and the resistor R. Further, its gate and source are connected to ground potential. When the drain potential, that is, the input potential of the internal input circuit 20 becomes higher than the normal signal level, it becomes conductive and operates to clamp the input potential. However, as described above, a sufficient destruction prevention effect cannot be expected by using this clamping MOSFET Q1 alone. Sufficient destruction prevention effect is due to parasitic
It is now possible to obtain it through MOSQ3.

The parasitic MOSQ3 for preventing electrostatic damage is the 6th,
As shown in FIG. 7, a guard ring 16 is provided along the periphery of the semiconductor substrate 10 of the semiconductor integrated circuit device.
and the pad portion P. The guard ring 16 is provided to prevent the inside of the semiconductor substrate 10 from being contaminated due to penetration of impurity ions such as sodium. This guard ring 1
6 is provided surrounding the edge of the semiconductor substrate 10. This guard ring 16 is formed of an N diffusion layer N ⁺ in the embodiment. This diffusion layer N ⁺ is used to form a parasitic MOS Q3. The drain D of this parasitic MOS Q3, together with the gate G,
It is connected to the pad part P mentioned above. Further, its source S is connected to the guard ring 16. When a high potential is applied to the pad portion P, the parasitic MOS Q3 is made conductive to prevent the internal input circuit 20 from being destroyed.

To explain more specifically, the above parasitic MOSQ
3, a drain D is an N diffusion layer N ⁺ formed between the pad portion P and the guard ring 16.
This N diffusion layer N ⁺ forms the resistor R mentioned above. That is, the resistor R and the drain D of the parasitic MOS Q3 are formed by the same diffusion layer N ⁺ .

Further, the parasitic MOS Q3 uses the N diffusion layer N ⁺ forming the guard ring 16 as the source S.
In other words, the guard ring 16 and the source S of the parasitic MOS Q3 are formed of the same diffusion layer N ⁺ . As a result, the potential Vs of the source S of the parasitic MOS Q3 is
It is fixed at the same potential as the guard ring 16. Guard ring 16 is normally placed at the same potential as substrate 10 .

Furthermore, the pad part P and the guard ring 1
Field oxide layer (LOCOS) between 6 and 12
A metal electrode, that is, an aluminum electrode M here, is provided on the insulating film 14. This aluminum electrode M becomes the gate G of the parasitic MOS Q3. A part of the aluminum electrode M forming the gate G is connected to the input pad P side.

Note that X indicates a cutting line of the semiconductor substrate 10. The guard ring 16 is formed along the cutting line X to protect the inside of the substrate 10 from contamination.

Now, in the electrostatic damage protection circuit configured as described above, the parasitic MOSQ3 for lowering the high potential applied to the pad part P utilizes the space between the pad part P and the guard ring 16. It is formed by What should be noted at this time is that the space between the pad part P and the guard ring 16 is more specifically the innermost side of the pad part P on the internal input circuit 20 side and the outermost side of the guard ring 16. where the space between is not normally available for forming circuits. Therefore, by making full use of the space, the parasitic MOSQ3 can occupy an area sufficient to prevent electrostatic damage. This makes it possible to reliably obtain the effect of preventing electrostatic damage. Further, the limited area of the board can be effectively utilized, and the layout around the pad portion P, especially inside the pad portion P, can be made much easier.

〔effect〕

As described above, in the electrostatic damage prevention circuit according to the present invention, the layout area is sufficient for the parasitic MOS for electrostatic damage prevention provided close to the input pad part without making the layout around the pad part difficult. As a result, the function of preventing electrostatic damage can be reliably obtained, and the limited layout area of the semiconductor substrate can be effectively utilized.

Although the invention made by the present inventor has been specifically explained above based on examples, this invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, MOSFETQ1 for the above clamp
can also be omitted. Also, the above resistance is a parasitic
It may be separate from the diffusion layer forming the drain of the MOS.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although MOS-DRAM has been explained, it is not limited thereto. For example, S-RAM (static
It can also be applied to semiconductor circuit devices other than MOS type (RAM) or semiconductor circuit devices that require electrostatic damage countermeasures.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an electrostatic damage prevention circuit other than the present invention. FIG. 2 is a circuit diagram showing another example of an electrostatic breakdown prevention circuit other than the present invention.
FIG. 3 is a diagram schematically showing a planar layout state of the circuit shown in FIG. 2. FIG. 4 is an abstract diagram showing a cross-sectional state of a part of the circuit shown in FIG. 2. FIG. 5 is a circuit diagram showing an embodiment of the electrostatic damage prevention circuit according to the present invention. FIG. 6 is a diagram schematically showing a planar layout state of the circuit of FIG. 5. FIG. 7 is an abstract diagram showing a cross-sectional state of a part of the circuit shown in FIG. 10... Semiconductor substrate, 12... Field oxide film layer, 14... Insulating layer, M... Metal electrode (aluminum electrode), 16... Guard ring, X... Cutting line, 20... Internal input circuit, P ...Input pad section, R...Resistor, Q1...For clamp
MOSFET, Q2, Q3...parasitic MOS, G...gate, D...drain, S...source, N ⁺ ...
Diffusion layer.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit having a parasitic transistor between an input pad portion provided inside a guard ring surrounding the periphery of a semiconductor substrate and an internal input stage circuit, the guard ring of the semiconductor substrate A semiconductor integrated circuit device characterized in that a parasitic transistor of the electrostatic breakdown prevention circuit is provided between the outermost peripheral side of the input pad and the innermost side of the input pad.