JPH0312461B2 - - Google Patents
Info
- Publication number
- JPH0312461B2 JPH0312461B2 JP57023063A JP2306382A JPH0312461B2 JP H0312461 B2 JPH0312461 B2 JP H0312461B2 JP 57023063 A JP57023063 A JP 57023063A JP 2306382 A JP2306382 A JP 2306382A JP H0312461 B2 JPH0312461 B2 JP H0312461B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- diffusion
- substrate
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/922—Bond pads being integral with underlying chip-level interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、MISFET構造の半導体装置の端子
における静電破壊保護のための構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for protecting a terminal of a semiconductor device having a MISFET structure from electrostatic discharge damage.
一般に、MISFET構造のICにおいては、IC外
部からの端子への静電気に対し、絶縁層や接合が
破壊されやすい。 Generally, in an IC with a MISFET structure, the insulating layers and junctions are easily destroyed by static electricity applied to the terminals from outside the IC.
従来、静電破壊に対する保護のために、端子よ
り内部には様々な保護回路を設けているが、端子
部分では第１図に示す如く単に基板１と絶縁層２
とボンデイングパツド３とからなつており何ら保
護のための対策が講じられていないため、ボンデ
イングパツドの下の絶縁層が破壊されるという欠
点を有していた。 Conventionally, in order to protect against electrostatic discharge damage, various protection circuits have been provided inside the terminal, but in the terminal area, as shown in FIG.
and a bonding pad 3, and since no protection measures have been taken, the insulating layer under the bonding pad is destroyed.
本発明は上記欠点を除去するためになされたも
ので、静電気による端子の破壊に対しこれを強く
する構造を提供することを目的とする。以下、本
発明の実施例を図面を用いて詳細に説明する。 The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a structure that makes the terminals more resistant to destruction due to static electricity. Embodiments of the present invention will be described in detail below with reference to the drawings.
また、第２図は本発明の一実施例を示すもので
ある。第２図においては、基板１の表面に前記基
板１とは逆の導電型で不純物濃度が比較的にうす
い拡散層５と、前記拡散層５の表面に前記拡散層
５と同じく前記基板１とは逆の導電型で不純物濃
度が前記拡散層５に比べ比較的に濃い拡散層６を
形成し、前記拡散層６との上に絶縁層２をはさん
でボンデイングパツド３を形成するとともに、前
記拡散層６と電気的に接続する。ここで前記拡散
層５と前記拡散層６とは同じ導電型の拡散層であ
るので電気的に等しく考えられる。従つて前記ボ
ンデイングパツド３に静電気が加えられた場合、
前記ボンデイングパツド３と前記拡散層６とは同
電位になり前記絶縁層２は破壊されず、前記静電
気による電圧は前記基板１と前記拡散層５との間
に加わる。 Further, FIG. 2 shows an embodiment of the present invention. In FIG. 2, a diffusion layer 5 having a conductivity type opposite to that of the substrate 1 and having a relatively low impurity concentration is formed on the surface of the substrate 1, and a diffusion layer 5 having a relatively low impurity concentration is formed on the surface of the substrate 1. Forming a diffusion layer 6 having an opposite conductivity type and having an impurity concentration relatively higher than that of the diffusion layer 5, and forming a bonding pad 3 with an insulating layer 2 sandwiched between the diffusion layer 6 and the diffusion layer 5, It is electrically connected to the diffusion layer 6. Here, since the diffusion layer 5 and the diffusion layer 6 are diffusion layers of the same conductivity type, they are considered to be electrically equal. Therefore, when static electricity is applied to the bonding pad 3,
The bonding pad 3 and the diffusion layer 6 are at the same potential, the insulating layer 2 is not destroyed, and the voltage due to the static electricity is applied between the substrate 1 and the diffusion layer 5.
この際、拡散層５と基板１との接合部分におい
て、拡散層５側で拡散層５の濃度が比較的うすい
ので空乏層が大きく広がつており、また基板１側
でも空乏層が当然広がつているから、拡散層５で
大きく広がつて形成された空乏層と基板１側に形
成された空乏層とによつて、静電気による電圧を
吸収することができて、拡散層５と基板１との接
合部分の熱破壊を防止することができる。 At this time, at the junction between the diffusion layer 5 and the substrate 1, the concentration of the diffusion layer 5 on the side of the diffusion layer 5 is relatively low, so the depletion layer spreads greatly, and the depletion layer also naturally spreads on the side of the substrate 1. Therefore, the voltage caused by static electricity can be absorbed by the depletion layer that is widely spread in the diffusion layer 5 and the depletion layer that is formed on the substrate 1 side. It is possible to prevent thermal damage to the joints.
以上のごとく本発明によれば、ボンデイングパ
ツドの下に前記ボンデイングパツドと電気的に接
続された基板と逆の導電型の濃度の異なる第１と
第２の拡散層５と６を形成することにより、絶縁
膜２の破壊を防止すると共に、拡散層５に形成さ
れる大きく広がる空乏層と基板１に形成される空
乏層によつて、静電気による電圧を吸収して拡散
層５と基板１との間の接合をも保護するので、静
電気による端子の破壊に対し破壊強度を著しく向
上させる効果がある。 As described above, according to the present invention, first and second diffusion layers 5 and 6 having different concentrations of conductivity type opposite to that of the substrate electrically connected to the bonding pad are formed under the bonding pad. This prevents breakdown of the insulating film 2, and also absorbs voltage due to static electricity by the widely expanding depletion layer formed in the diffusion layer 5 and the depletion layer formed in the substrate 1. Since it also protects the bond between the terminal and the terminal, it has the effect of significantly improving the breaking strength against breakdown of the terminal due to static electricity.
第１図は半導体装置の端子付近の従来の断面
図、第２図は半導体装置の端子付近の本発明の第
２の実施例の断面図である。
１……基板、２……絶縁層、３……ボンデイン
グパツド、５，６……拡散層。
FIG. 1 is a conventional cross-sectional view of the vicinity of a terminal of a semiconductor device, and FIG. 2 is a cross-sectional view of a second embodiment of the present invention near a terminal of a semiconductor device. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Insulating layer, 3...Bonding pad, 5, 6...Diffusion layer.
Claims (1)
形成される前記半導体基板と逆導電型であつて不
純物濃度が比較的うすい第１の拡散層と、前記第
１の拡散層の表面部分に形成される前記第１の拡
散層と同じ導電型であつて前記第１の拡散層の不
純物濃度よりも濃い第２の拡散層と、前記第１と
第２の拡散層の上に形成される絶縁層と、前記絶
縁層を介して前記第１と第２の拡散層の上に形成
され前記絶縁膜を貫いて前記第２の拡散層と電気
的に接続されるボンデイングパツドとからなり半
導体装置。1 a semiconductor substrate, a first diffusion layer formed on a surface portion of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and having a relatively low impurity concentration; a second diffusion layer having the same conductivity type as the first diffusion layer and having a higher impurity concentration than the first diffusion layer; and an insulating layer formed on the first and second diffusion layers. and a bonding pad formed on the first and second diffusion layers via the insulating layer and electrically connected to the second diffusion layer by penetrating the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023063A JPS58140134A (en) | 1982-02-16 | 1982-02-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57023063A JPS58140134A (en) | 1982-02-16 | 1982-02-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58140134A JPS58140134A (en) | 1983-08-19 |
| JPH0312461B2 true JPH0312461B2 (en) | 1991-02-20 |
Family
ID=12099956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57023063A Granted JPS58140134A (en) | 1982-02-16 | 1982-02-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140134A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4838101A (en) * | 1971-09-10 | 1973-06-05 | ||
| JPS5842271A (en) * | 1981-09-07 | 1983-03-11 | Nec Corp | Semiconductor integrated circuit device |
-
1982
- 1982-02-16 JP JP57023063A patent/JPS58140134A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58140134A (en) | 1983-08-19 |
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