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JPH0553307B2 - - Google Patents
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JPH0553307B2 - - Google Patents

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Publication number
JPH0553307B2
JPH0553307B2 JP61266741A JP26674186A JPH0553307B2 JP H0553307 B2 JPH0553307 B2 JP H0553307B2 JP 61266741 A JP61266741 A JP 61266741A JP 26674186 A JP26674186 A JP 26674186A JP H0553307 B2 JPH0553307 B2 JP H0553307B2
Authority
JP
Japan
Prior art keywords
insulating film
field
field insulating
drain electrode
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61266741A
Other languages
Japanese (ja)
Other versions
JPS63122173A (en
Inventor
Noriaki Ooba
Yoshio Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP61266741A priority Critical patent/JPS63122173A/en
Publication of JPS63122173A publication Critical patent/JPS63122173A/en
Publication of JPH0553307B2 publication Critical patent/JPH0553307B2/ja
Granted legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は集積回路の外部導出ピンに接続されか
つサージ吸収用MOSトランジスタを有した入力
または出力保護回路を具備した半導体集積回路に
関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit equipped with an input or output protection circuit connected to an external lead-out pin of the integrated circuit and having a surge absorbing MOS transistor. Regarding circuits.

(従来の技術) 上記入力保護回路の回路図を示したのが第2図
である。これは入力パツド1、抵抗R1,R2、
フイールドトランジスタTr1、MOSトランジス
タTr2から構成される。入力パツド1に侵入し
たサージは抵抗R1,R2により鈍化し、フイー
ルドトランジスタTr1、MOSトランジスタTr2
によつて吸収される。
(Prior Art) FIG. 2 shows a circuit diagram of the above-mentioned input protection circuit. This is input pad 1, resistors R1, R2,
It is composed of a field transistor Tr1 and a MOS transistor Tr2. The surge that enters the input pad 1 is slowed down by the resistors R1 and R2, and the surge enters the field transistor Tr1 and the MOS transistor Tr2.
absorbed by.

第3図aは上記トランジスタTr2のパターン
平面図、同図bは同図aのB−B線に沿う断面図
であり、2はソース、3はドレイン、4はゲート
電極、5はドレイン電極(メタル)、6はフイー
ルド絶縁膜、7は層間絶縁膜である。この図のよ
うに従来は、ドレイン側のフイールドエツジ(フ
イールド絶縁膜6のエツジ部)とメタル5のエツ
ジが、図示矢印で示されるようにほとんど一致、
あるいはフイールドエツジによりメタル5の方が
内側(拡散層3側)になつていた。
FIG. 3a is a pattern plan view of the transistor Tr2, and FIG. 3b is a cross-sectional view taken along the line B-B in FIG. 6 is a field insulating film, and 7 is an interlayer insulating film. As shown in this figure, conventionally, the field edge on the drain side (the edge of the field insulating film 6) and the edge of the metal 5 almost coincide as shown by the arrows in the figure.
Alternatively, the metal 5 was on the inside (on the diffusion layer 3 side) due to the field edge.

(発明が解決しようとする問題点) 上記したように従来は、メタル5がフイールド
エツジとほとんど一致していたか、あるいはフイ
ールドエツジより内側に位置していた。この時メ
タル5がサージ等により高電位になると、フイー
ルドエツジ付近の空乏層が狭くなり、その部分に
特に電界が強くかかるため、フイールドエツジ部
が痛んでしまい、その部分でリークし、チツプそ
のものがこわれてしまう。このことはフイールド
絶縁膜6下にフイールドインプラ層P+がうつて
ある時には、特にフイールドエツジ付近の空乏層
が狭くなるため、フイールドエツジ付近の痛みが
顕著である。
(Problems to be Solved by the Invention) As described above, conventionally, the metal 5 was almost coincident with the field edge or was located inside the field edge. At this time, when the metal 5 becomes high potential due to a surge, etc., the depletion layer near the field edge narrows, and a particularly strong electric field is applied to that area, damaging the field edge, causing leakage at that area, and damaging the chip itself. It will break. This means that when the field implant layer P + is deposited under the field insulating film 6, the depletion layer especially near the field edge becomes narrower, so that the pain near the field edge is noticeable.

本発明はフイールドエツジ部の空乏層を広く
し、その部分を保護すことを目的とする。
An object of the present invention is to widen the depletion layer at the field edge portion and protect that portion.

[発明の構成] (問題点を解決するための手段と作用) 本発明は、集積回路の外部導出ピンに接続され
かつサージ吸収用MOSトランジスタを有した入
力または出力保護回路を具備し、該保護回路のサ
ージ吸収用MOSトランジスタのドレイン側のフ
イールド絶縁膜上において前記トランジスタのド
レイン電極を、前記ドレイン側のフイールド絶縁
膜のエツジ部よりも前記フイールド絶縁膜と該膜
及びその上の前記ドレイン電極間の層間絶縁膜と
を加えた厚さの半分以上、前記フイールド絶縁膜
を覆う側にとび出させたつまりドレイン電極とび
出し部を設けたことを特徴とする。そしてこのド
レイン電極とび出し部に、外部導出ピンから入力
パツドを介してサージが入力された場合に、前記
ドレイン電極とび出し部にサージによる高電圧が
かかつたのを利用して、前記ドレイン電極とび出
し部の下方にあるフイールドエツジ部の空乏層を
広くして電界を弱め、その部分を保護するもので
ある。
[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention includes an input or output protection circuit connected to an external lead-out pin of an integrated circuit and having a surge absorbing MOS transistor. The drain electrode of the transistor is placed on the field insulating film on the drain side of the MOS transistor for surge absorption of the circuit, and the distance between the field insulating film and the film and the drain electrode thereon is higher than the edge of the field insulating film on the drain side. The device is characterized in that a drain electrode protruding portion is provided that protrudes from the side covering the field insulating film by more than half the thickness of the field insulating film plus the interlayer insulating film. When a surge is input to this drain electrode protrusion from an external lead-out pin via the input pad, the drain electrode is The depletion layer in the field edge section below the protruding section is widened to weaken the electric field and protect that section.

(実施例) 以下図面を参照して本発明の一実施例を説明す
る。第1図aは同実施例の要部のパターン平面
図、同図bは同断面図であるが、これは第3図
a,bに対応させた場合の例であるから、対応個
所には同一符号を付して説明を省略し、特徴とす
る個所の説明を行なう。本実施例の特徴は、入力
保護回路のサージ吸収用トランジスタのドレイン
3側のフイールド絶縁膜6上において前記トラン
ジスタのドレイン電極5を、前記ドレイン側のフ
イールド絶縁膜6のエツジ部よりもフイールド絶
縁膜6の厚さと層間絶縁膜7の厚さとを加えた厚
さdの半分(d/2)以上、フイールド絶縁膜6
を覆う側にとび出させたつまりドレイン電極とび
出し部5aを設けたことである。
(Example) An example of the present invention will be described below with reference to the drawings. Fig. 1a is a pattern plan view of the main part of the same embodiment, and Fig. 1b is a cross-sectional view of the same, but since this is an example in which it corresponds to Figs. 3a and b, the corresponding parts are The same reference numerals are used to omit the explanation, and the characteristic parts will be explained. The feature of this embodiment is that on the field insulating film 6 on the drain 3 side of the surge absorption transistor of the input protection circuit, the drain electrode 5 of the transistor is placed on the field insulating film 6 on the side of the field insulating film 6 on the drain side. The thickness of the field insulating film 6 is at least half (d/2) of the thickness d, which is the sum of the thickness of the field insulating film 6 and the thickness of the interlayer insulating film 7.
In other words, the drain electrode protruding portion 5a is provided to protrude from the side that covers the drain electrode.

上記のような構成とすれば、ドレイン電極5
に、入力パツド1を介してサージが入力された場
合、ドレイン3の周囲には空乏層が広がつている
が、この空乏層のうち特にフイールド絶縁膜6の
エツジ部での空乏層は、ドレイン電極とび出し部
5aにかかるサージ(高電位)により、ドレイン
3から遠ざかる方向に広げられ、従つてフイール
ドエツジ部付近の電界が弱まり、その部分が保護
されるものである。
With the above configuration, the drain electrode 5
When a surge is input through the input pad 1, a depletion layer spreads around the drain 3, and this depletion layer, especially at the edge of the field insulating film 6, The surge (high potential) applied to the protruding electrode portion 5a causes it to expand in the direction away from the drain 3, thereby weakening the electric field near the field edge portion and protecting that portion.

実験によれば、ドレイン電極とび出し部5aの
とび出し両がd/2以下の場合は効果がうすく、
d/2以上の場合に使用に耐える効果が得られ
た。
According to experiments, the effect is weak when both sides of the drain electrode projecting portion 5a are d/2 or less;
In the case of d/2 or more, an effect that can withstand use was obtained.

なお本発明は実施例のみに限られることなく種
種の応用が可能である。例えば実施例では本発明
を入力保護回路に適用した場合を説明したが、集
積回路から出力を集積回路外部へ外部導出ピンを
介して出力する部分でも、第2図と同じような構
成をとつて出力保護回路とすることもあるので、
本発明はこの場合にも適用できる。
Note that the present invention is not limited to the embodiments and can be applied in various ways. For example, in the embodiment, a case where the present invention is applied to an input protection circuit has been explained, but a structure similar to that shown in FIG. It may also be used as an output protection circuit, so
The present invention can also be applied to this case.

[発明の効果] 以上説明した如く本発明によれば、フイールド
エツジ部付近の空乏層が、ドレイン電極にサージ
を受けた時に広がつてフイールドエツジ部の電界
が弱まるため、フイールドエツジ部を保護し得る
半導体集積回路が提供できるものである。
[Effects of the Invention] As explained above, according to the present invention, the depletion layer near the field edge expands when the drain electrode receives a surge, weakening the electric field at the field edge, thereby protecting the field edge. The semiconductor integrated circuit that can be obtained can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは本発明の一実施例を説明するための
パターン平面図、同図bは同断面図、第2図は入
力保護回路図、第3図aは従来回路のパターン平
面図、同図bは同断面図である。 2……ソース、3……ドレイン、4……ゲート
電極、5……ドレイン電極、5a……ドレイン電
極とび出し部、6……フイールド絶縁膜、7……
層間絶縁膜。
FIG. 1a is a pattern plan view for explaining an embodiment of the present invention, FIG. 1b is a sectional view of the same, FIG. 2 is an input protection circuit diagram, and FIG. Figure b is a sectional view of the same. 2... Source, 3... Drain, 4... Gate electrode, 5... Drain electrode, 5a... Drain electrode protrusion, 6... Field insulating film, 7...
Interlayer insulation film.

Claims (1)

【特許請求の範囲】[Claims] 1 集積回路の外部導出ピンに接続されかつサー
ジ吸収用MOSトランジスタを有した入力または
出力保護回路を具備し、該保護回路のサージ吸収
用MOSトランジスタのドレイン側のフイールド
絶縁膜上において前記トランジスタのドレイン電
極を、前記ドレイン側のフイールド絶縁膜のエツ
ジ部よりも前記フイールド絶縁膜と該膜及びその
上の前記ドレイン電極間の層間絶縁膜とを加えた
厚さの半分以上、前記フイールド絶縁膜を覆う側
にとび出させたことを特徴とする半導体集積回
路。
1 Equipped with an input or output protection circuit connected to an external lead-out pin of an integrated circuit and having a surge absorption MOS transistor; The electrode covers the field insulating film by at least half the thickness of the field insulating film plus the interlayer insulating film between the film and the drain electrode above the edge part of the field insulating film on the drain side. A semiconductor integrated circuit characterized by protruding to the side.
JP61266741A 1986-11-11 1986-11-11 Semiconductor integrated circuit Granted JPS63122173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61266741A JPS63122173A (en) 1986-11-11 1986-11-11 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61266741A JPS63122173A (en) 1986-11-11 1986-11-11 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS63122173A JPS63122173A (en) 1988-05-26
JPH0553307B2 true JPH0553307B2 (en) 1993-08-09

Family

ID=17435058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61266741A Granted JPS63122173A (en) 1986-11-11 1986-11-11 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS63122173A (en)

Also Published As

Publication number Publication date
JPS63122173A (en) 1988-05-26

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Legal Events

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EXPY Cancellation because of completion of term