JPH0434685B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit for processing output pulses of various detectors including pulse generators used for position detection of NC machine tools, etc. This invention relates to a circuit that converts a certain type of pulse pattern into several types of pulse patterns.

[Background technology]

A conventional example of such a circuit is shown in FIG.

In Figure 1, 1 is a multiplier (e.g.
LS153), 2 is a D flip-flop (e.g.
LS377), and is configured to convert pulse inputs X and Y according to the format specified by mode select signals S ₁ and S ₀ and output UP and DOWN signals.

Figure 2 shows how it is converted.

For example, when inputting the pulse pattern shown in (a), mode select signals S ₁ and S ₀ are set to (1,
1), (1,0), (0,0) specified (a), (c),
(workman)
It is converted into the pulse pattern shown in .

Furthermore, when inputting the pulse pattern shown in (E), the mode select signals S ₁ and S ₀ are designated as (0, 1), and the pulse pattern is converted to the pulse pattern shown in (F).

By the way, (A) is an example of an output pulse of an incremental rotary encoder, and the rotation direction is detected by the phase difference between the two-phase pulses.

(E) is an example of the output pulse of the magnetic displacement detector, and depending on the direction of movement, only one of the pulses becomes "Low" for each predetermined amount of movement.
That is, the conventional circuit shown in FIG. 1 has the function of converting the pulse patterns (A) and (E) into UP and DOWN signals.

However, as for the pulse pattern, as shown in Fig. 3 (g), the enable signal becomes "Low" for each predetermined amount of movement regardless of the direction of rotation, and the direction of movement is determined by the up/down signal ( UP／
There is also a type of detection based on "High" or "Low" of DOWN), and a circuit that can handle this is desired.

With the conventional circuit shown in Fig. 1, it is impossible to obtain the output shown in (g) above, and if you try to achieve it by adding a NAND gate or something else, the number of parts will increase significantly. The drawback is that it lacks practicality.

[Purpose of the invention]

The present invention has been made with the aim of eliminating the above-mentioned drawbacks, and is capable of processing pulses that can reduce the number of parts compared to conventional circuits, satisfy the conventional functions, and output pulse patterns such as (g) above. It provides a circuit.

[Summary of the invention]

The gist of the present invention is that this circuit is configured only with a D flip-flop and a ROM, and the output of the detector input to the circuit is held at the previous value for one clock by the D flip-flop. An address signal is synthesized from the previous value, current value, and mode select signal, and the address signal is
By inputting the ROM into the ROM,
The data stored in the memory is read out as a predetermined output signal.

[Embodiments of the invention]

A specific embodiment of the present invention will be described with reference to FIG.

3 is a bipolar ROM, and a small ROM such as 256W x 4B is sufficient.

2 is a D flip-flop. X, Y are pulse inputs of various patterns, and _S0 to _S3 are mode select signals. The select signal remains as is.
X, Y are delayed once by D flip-flop 2,
Y', and set it again to 1 with D flip-flop 2.
It is inputted into ROM3 as time delay X'', Y''.

That is (Y″, X″, Y′, X′, S ₀ , S ₁ , S ₂ , S ₃ )
The 8-bit signal becomes the address A ₀ to A ₇ signal of the ROM3.

Now, the case where the pulse pattern shown in FIG. 3(A) is processed will be described with reference to FIG. 5.

The input two-phase pulse is delayed once (one clock pulse CP) by the D flip-flop, and
Assume that the waveform becomes as shown in Y′. Then, X″,
Y″ is delayed one more time and takes on the waveform shown in the figure.

The predetermined select signals S ₀ to _{S 3} at this time are assumed to be (0, 0, 0, 0) to simplify the explanation.

Then, the address signal A ₀ input to ROM3
~ _A7 is "0H", "0H",... as shown in Figure 5.
..., "8H", "AH", ....

ROM3 will access and read the data stored at each address,
At this time, if you store data "4H" in address "0H", data "AH" in address "8H", and data "4H" (hereinafter omitted) in address "AH" in advance, the Output signals D ₀ to _{D 3} as shown in FIG. 5 are obtained.

This results in the pulse patterns shown in (a) and (g) above.

The relationship between addresses and data at this time is shown in FIG. 6 as a state diagram. The double circle is the usual place, the circle is the place where the input pulse rises, the number inside the circle is the address, and the number outside the circle is the data. The solid line arrow indicates the forward direction, and the dotted line arrow indicates the reverse direction.

As mentioned above, the address is 00H→08H→0AH→
If it changes like this, the data becomes 4H→AH→4H→…
It turns out that...

From the above, it is clear that various outputs can be obtained by changing the data written in the ROM 3 in advance.

For example, if you want to obtain an output that is 1/4 of the output in (A), as shown in (D) in Figure 2, you can set the address ,, in Figure 6 to 4H for forward rotation. . That is, if the mode select signals S ₃ to S ₀ are (1, 0, 0, 0), the address
All you have to do is write the data corresponding to 80H, 88A, 8AH...

In other words, the upper four digits of the address signal are specified by the mode select signal, so (0, 0, 0, 0)
This means that seven types of data groups can be output from (1, 1, 1, 1).

Therefore, this circuit can perform the following conversions.

() (A/B2 phase) → (UP, DOWN) () (A/B2 phase) → (UP/DOWN, E) () (UP, DOWN) → (UP/DOWN,
E) () (UP/DOWN, E) → (UP,
DOWN) Furthermore, it is also possible to output pulse patterns that are currently unknown.

〔Effect of the invention〕

As described above, according to the present invention, one type of pulse pattern can be converted into several types of pulse patterns with an extremely small number of parts, so that a multifunctional pulse processing circuit can be realized in a compact manner.

[Brief explanation of drawings]

Fig. 1 shows a conventional example, Fig. 2 shows an example of input/output pulses in the conventional example, Fig. 3 shows a conventional pulse pattern, Fig. 4 shows a specific embodiment of the present invention, and Fig. 5 shows an input/output pulse of the present invention. Pulse Example, FIG. 6 is a state diagram illustrating the present invention. 1: Multiplier, 2: D flip-flop, 3: Bipolar ROM.

Claims (1)

[Claims] 1. A pulse processing circuit that converts a two-phase pulse output from a pulse generator into one of a plurality of preset pulse patterns of other formats, comprising: a D flip-flop; The circuit includes a ROM, inputs the two-phase pulse signal of the pulse generator to the D flip-flop to obtain the two-phase pulse signal delayed by one clock, and inputs the two-phase pulse signal delayed by one clock to the D flip-flop again. input to other terminals, and the above 2 clocks are delayed by 2 clocks.
Obtain a phase pulse signal, synthesize an address signal with the two-phase pulse signal delayed by one clock, the two-phase pulse signal delayed by two clocks, and a mode select signal input by specifying a conversion format. By inputting an address signal to the ROM, predetermined data written in the ROM in advance is read out according to the address signal, thereby converting the two-phase pulse signal of the pulse generator into another format of pulse signal. A pulse processing circuit characterized by converting.