JPH051499B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data processing device incorporating a counter.

In recent years, LSI technology has made remarkable progress, and its functions have become more sophisticated and diversified along with higher integration. In particular, peripheral hardware functions such as counters, serial interfaces, and A/D converters are becoming increasingly diverse and multifunctional. Among these, the counter function is a function suitable for measuring the period and pulse width of pulses generated by a controlled object, and is an essential function for detecting and controlling the rotational speed and rotational speed of a motor, for example. It is integrated into a microcomputer chip as one function. Generally, in microcomputers, a counter (hereinafter referred to as a free running counter (FRC)) that counts a predetermined counting clock is used to measure pulse periods, pulse widths, etc.
(hereinafter referred to as CPTR) and a cabin register (hereinafter referred to as CPTR) that temporarily holds the counted data. When a counter with this type of configuration receives a pulse signal from the object being measured, it outputs a value that indicates the counting status of the FRC at that time.
Store it in CPTR (hereinafter referred to as "capture") until the next pulse signal is input.
Continue FRC counting operation. When the next pulse signal is input, the current value of FRC is captured. CPTR retains previously captured data during this time. To find the pulse width and period, temporarily save the previous data stored in CPTR to another register, and then find the difference from the previous data when the FRC value is written. good.

Furthermore, when attempting to perform highly accurate control, measures against noise and optimal control must be taken into consideration. For this reason, by comparing information such as pulse width and period obtained from previously recorded data with newly obtained information, it is possible to determine whether or not noise is occurring, the degree of acceleration or deceleration, or to calculate the degree of acceleration or deceleration caused by noise. A method has been adopted in which an average is calculated from the captured data and the results are used to perform various controls.

(Prior Art) A conventional data processing device having a counter will be described below with reference to the block diagram shown in FIG.

The microcomputer 100 includes an execution unit 101,
program memory 102, data memory 103,
It has an interrupt control unit 104 and a counter 105,
These are interconnected via an internal bus 106. Program counter (hereinafter referred to as PC)
101-1, a program status word (hereinafter referred to as PSW) 101-2, and a general-purpose register set 101-3. Store in. The counter 105 has an FRC 105-1, a cabin register 105-2 for holding the cabin data, a cabin command line 105-3, and a cabin end signal output line 105-4. FRC105-1 is Kyabuchia command line 105
-3 signal becomes active, the current
The value of FRC 105-1 is stored in CPTR 105-2, and a signal is output to cabin end signal output line 105-4 to notify interrupt control unit 104 that one cabin operation has ended. In response to this, the interrupt control unit 104 activates the interrupt request line 104-1 to issue an interrupt request to the execution unit 101.
As a result, the execution unit 101 executes the interrupt processing.

Here, the sequence processing procedure using an interrupt will be described using the flowchart shown in FIG.

In this software processing, the Kyabuchia command line 10
The time interval of the signal input to 5-3, that is, information such as pulse width and period, is obtained by subtracting between the captured data, and the result of the subtraction is transferred to a predetermined address in the data memory. Perform processing. The data memory 103 includes a cab parameter save area 103-1, a calculation result storage area 103-2, a PC 101-1, and a PSW.
101-2, a stack area 103-3 for saving the general-purpose register set 101-3 (hereinafter referred to as status), and a cache data possible area 10 for temporarily storing the previously cached value.
Set 3-4. A memory pointer specifying an address in the calculation result storage area 103-2 and cabin number information that holds the number of cabins have been stored in advance in the cabin parameter save area 103-1.

The signal from Cabuchi command line 105-3 becomes active, and the value of FRC105-1 becomes CPTR1.
When transferred to 05-2, the terminal signal line 1
A signal is output at 05-4 and a cab interrupt occurs. In FIG. 1, the execution unit 101 temporarily saves the contents of the status in the stack area 103-3 in the data memory 103 in order to retain the contents of the processing up to that point. Thereafter, the cabin number information and memory pointer are read from the cabin parameter save area 103-1. next
Read the value of CPTR 105-2 and store it in the cabin data storage area 103-4 in the data memory 103.
Read the data that was previously captured from
This value is calculated from the value of CPTR 105-2 and the result is transferred to the address specified by the memory pointer.

Next, the value of the CPTR 105-2 just read out is transferred to the cabin data storage area 103-4.
Thereafter, the memory pointer is incremented, the cabin count information is decremented, and the information is returned to the cabin parameter save area 103-1. When the number of cabin operations reaches a predetermined number, that is, when the decremented value becomes 0, it is assumed that the collection of speed information has been completed through a series of cabin operations, and the process branches to the cabin procedure completion process, for example, averaging processing. It performs processes such as determining the degree of acceleration or deceleration. If the predetermined number of times has not yet been completed, PC101-1, PSW1
01-2, the general purpose register set 101-3 is restored from the stack area 103-3 and the cache interrupt service is completed.

As mentioned above, in conventional interrupt-based software processing in microcomputers, when an interrupt occurs, the previous cabin data is read from memory, subtracted from the latest cabin data, and the result is stored in the data memory. , In addition to these processes, CPU interrupt processing, saving and restoring registers such as PC 101-1, PSW 101-2, and general-purpose register set 101-3, returning to the main routine, fetching and decoding of individual instructions, etc. Significant overhead is involved. These overheads account for a significant portion of the total interrupt service routine;
As the number of interrupts increases, the time for the CPU to perform the original data processing decreases, which has the major disadvantage of reducing the CPU's processing ability.If high-precision control is required, This decrease in processing capacity becomes a very big problem.

(Object of the Invention) Therefore, the object of the present invention is to effectively utilize the hardware for controlling instruction execution to perform the above-mentioned function of calculating the above-mentioned computer data and transferring the result of the calculation, by intervening with software interrupt processing.
An object of the present invention is to provide a data processing device that reduces the burden on a CPU and minimizes a decrease in processing performance.

(Structure of the Invention) According to the present invention, when an interrupt occurs during the execution of program processing in a central processing unit, the corresponding interrupt processing is counted by a counter and in data processing executed by the central processing unit. and a count data processing control unit that performs data control on the value set, and when an interrupt occurs, the program processing is temporarily interrupted, and the interrupt processing is executed without saving the state of the central processing unit at the time of interruption. In this interrupt processing, when an interrupt command is generated from the count data processing control section, the count value of the counter is processed using the arithmetic and logic operation unit of the central processing unit.

(Effects of the Invention) In the present invention, processing requests (hereinafter referred to as
To deal with the occurrence of I/O requests)
No CPU interrupt handling routine is required. That is, upon the generation of an I/O request, it is possible to automatically perform subtraction of the capacitor data to obtain information such as pulse width and period, and to transfer the calculation results to the memory (hereinafter, the subtraction and transfer process will be described below). macro service).

Macro service is I/O from counting device
When a request occurs, the normal program execution of the CPU is stopped, and status information such as the PC, PSW, general register set, etc., and data are held at their positions. Macro service is CPU
Since this is done by effectively utilizing part of the hardware used for controlling instruction execution during normal program execution, there is no need to add special hardware for macro service. When the data processing control means finishes the macro service, the CPU resumes execution of the interrupted program using the status and data that it held. Since this program interruption is not visible to the operator from the software perspective, it appears as if a macro service was automatically inserted in the middle of program processing. In this way, macro services can minimize the number of interrupts that involve software processing, so the CPU
can improve execution efficiency. When the macro service is completed a predetermined number of times, a conventional interrupt request is generated to notify the CPU of the completion of the macro service, and subsequent processing is performed by program execution.

(Example) An example of the present invention is shown in FIG. 3, and will be explained using the drawings. The counting device 105 is FRC105-
1 and CPTR 105-2, and when the value of FRC 105-1 is calculated by the cabin command signal 105-3, a cabin end signal 105-4 is output. The count data processing control section 500 includes an I/O request control section 205, an I/O processing execution request line 205-1, and an I/O processing execution mode specification line 205-.
2, and an I/O request receiving unit 206 that controls the operation of the CPU 510. The data memory unit 103 also has an operation result storage area 103-2, a stack area 103-3 for saving status,
The CPU 510 is the program memory 1 to be executed next.
PC 101-1 pointing to address 02, PSW 101-2 indicating the operating status of the entire CPU, general-purpose register set 101-3 holding data being processed,
An arithmetic and logic unit (hereinafter referred to as ALR) 201 that has an arithmetic and logic operation function, an instruction register 202 that holds the next instruction to be executed, an instruction decoder 203 that decodes the contents of the instruction register 202 and generates various control signals, and an instruction It is composed of an execution control unit 204 that controls the overall operation of the CPU 510 based on the output of the decoder 203. Further, a macro service register group 207 necessary for macro service is provided in a part of the data memory 103. This macro service register group 207 includes a pointer (hereinafter referred to as I/OP) 207-1 that specifies the address of the cache register, and a pointer (hereinafter referred to as BP) that specifies the address of the data memory that holds the previously cached data. )20
7-2. Memory pointer (hereinafter referred to as MR) that specifies the address in the operation result storage area 103-2 that stores the result of subtraction of two cabocha data.
207-3, and a terminal counter (hereinafter referred to as TC) 207-4 that can hold the number of times of kabuchiya. All of the above parts are connected to an internal bus 106.

Referring to this block diagram, perform the counting below.
This section describes the operation of macro services in data processing.

The counting device 105 is connected to the Kyabuchia command line 10.
When an active signal is input from 5-3, the value of FRC105-1 at that time is transferred to CPTR105-2.
105-4
Output. In response, the I/O request control unit 205 sets the I/O processing request line 205-1 to the I/O request receiving unit 206 to an active level, and
At the same time, the I/O processing execution mode designation line 205-2 is set to high level.

If the I/O request receiving unit 206 detects that the I/O processing execution mode designation line 205-2 is at a high level when the I/O processing request line 205-1 becomes active, this I/O request is accepted. A macro service code is set in the instruction register 202 for processing by macro service. The execution control unit 204 prohibits updating of the PC 101-1, and updates the PC 101-1.
1-1, PSW 101-2, and general-purpose register set 101-3 are held, and the following processing is started.

First, the I/O request control unit 205
The address of the macro service register group 207 is output to the top, and the execution control unit 204 reads the address of the macro service register group 207.
Next, the execution control unit 204 is specified by the I/OP 207-1 of the macro service register group 207.
Read the cabocha data from CPTR105-2. Next, the execution control unit 204 reads the previously captured value from the memory at the address specified by the BP 207-2 of the macro service register group 207, and subtracts this previously captured value from the value of the CPTR. The result of this subtraction is MP20
Stored and read out the calculation result storage area 103-2 in the data memory 103 specified by 7-3.
The value of CPTR105-2 is stored in the memory at the address specified by BP207-2. Next TC20
Decrement 7-4 and store it in TC207-4, increment the value of memory pointer MP that specifies the address to store the calculation result, and then
Store in 07-3. The above series of processing completes the subtraction and transfer processing of the cabocha data in one macro service, but when the value of TC207-4 becomes 0 as a result of the subtraction, a series of macro
Recognizing that the service has been completed, the I/O request control unit 205 activates the I/O processing execution request line 205-1 again and connects the I/O processing execution mode specification line 205-1 to generate a conventional interrupt request.
-2 is the low level. Then, the I/O request accepting unit 206 starts an interrupt processing program and executes software processing such as averaging a series of data obtained by executing the macro service.

(Effects of the Embodiment) As described above, in this embodiment, when the cab end signal is generated due to the end of the cab, the macro service automatically performs the subtraction and transfer processing of the cab data. PC101-1 and PSW101- which were unavoidable in the interrupt processing routine that involves software processing.
2. The time spent on saving and restoring the general-purpose register set 101-3, branching to interrupt programs, reading instructions, decoding, etc. can be significantly reduced, and the decrease in CPU processing capacity can be reduced. It can be suppressed as much as possible.

As described above, the data processing device based on the present invention provides an innovative count data processing means, and is applicable and has extremely high practical effects.

[Brief explanation of the drawing]

Fig. 1 is a simple block diagram showing an example of a microcomputer with a built-in conventional counting function, Fig. 2 is a flowchart of the interrupt processing shown in Fig. 1, and Fig. 3 is a detailed block diagram of an embodiment of the present invention. It is a diagram. 100...Microcomputer, 101...
Execution unit, 101-1...Program counter (PC), 101-2...Program status word (PSW), 101-3...General-purpose register set, 102...Program memory, 103
...Data memory, 103-1...Kiyabuchiya
Parameter save area, 103-2... Calculation result storage area, 103-3... Stack area, 103-
4... Kiyabutiya data storage area, 104...
Interrupt control unit, 104-1...Interrupt request line, 1
05...Counting device, 105-1...Free
Running counter (FRC), 105-2...
Kiyabutiya Register (CPTR), 105-3...
...Kyabuchiya command line, 105-4...Kyabuchiya end signal output line, 106...Internal bus, 201...
...Arithmetic logic unit (ALU), 202...Instruction register, 203...Instruction decoder, 204...
...Execution control unit, 205...I/O request control unit, 2
05-1...I/O processing request line, 205-2...
I/O processing execution mode specification line, 206...I/O request reception unit, 207...Macro service register group, 207-1...I/OP, 207-2...
BP, 207-3...MP, 207-4...TC,
500... Count data processing control unit, 510...
...Central processing unit (CPU).

Claims (1)

[Scope of Claims] When an interrupt occurs during execution of program processing by a central processing unit, the data processing device executes corresponding interrupt processing by the central processing unit, comprising: a counter for counting clocks; storage means for temporarily storing the value of the counter in synchronization with an input signal; request control means for generating both the interrupt processing request and the macro service processing request when the count value is stored in the storage means; It has an execution control unit that detects the macro service processing request and controls the macro service processing operation, and a data memory that stores various data, and the execution control unit detects the macro service processing request and controls the macro service processing operation. Temporarily interrupting the program processing of the processing unit, maintaining the state of the central processing unit at the time of the interruption without saving, and storing the value stored in the storage means and a predetermined address on the data memory. The arithmetic and logic operation unit of the central processing unit calculates the value of the macro service processing request, and the subtraction result is transferred to a predetermined address on the data memory, and the request control means performs a predetermined process based on the macro service processing request. When the macro service processing request has been executed a number of times, the macro service processing request is canceled and only the interrupt processing request is valid, thereby saving the state of the central processing unit at the time of interruption and executing the program processing based on the interrupt processing request. Data processing equipment.