JPH0564471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In order to configure a solid-state display device, the present invention uses a vertical channel type stacked type insulated gate type semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor provided on a substrate.
) and its production method.

The present invention separates (trims) the gate electrode of the defective IGF from the lead (bus line) after the device is completed.
This uses a fixed display device that can improve yield, and since a sublimable material is used for the gate electrode, the sheet resistance of the conductive film (third conductive film) is 10 to 100Ω/ □ is large. Therefore, the lead (fourth conductive film) as a bus line is closely connected to this gate electrode conductor.
By setting the sheet resistance to 0.5Ω/□ or less,
It is characterized by eliminating the delay operation that occurs in devices with a matrix configuration.

In addition, by forming a contact with the conductor (second conductive film) that is close to the source or drain using the lead with a sheet resistance of 0.5Ω/□ or less, the gate electrode of the inverter and its load can be
The purpose is to connect the IGF to the source or drain without adding any extra manufacturing steps.

The present invention provides a first conductive electrode on an insulating substrate,
A first semiconductor, a first insulator, a second semiconductor, a second conductive electrode, and a second insulator (interlayer insulator) are stacked in six layers on two sides of the stack. The present invention relates to providing an IGF in which a channel formation region is achieved by a third semiconductor formed on a first insulator, and a solid-state display device applying the IGF.

The present invention provides a composite semiconductor device having such a matrix structure on a substrate, and a liquid crystal display type, an electronic device, etc.
It is intended to be used as a control unit and its peripheral circuit for display devices such as chromic (ECD) display type and EL (electroluminescence) type.

When providing a flat solid state display device, a liquid crystal solid state display device is known in which a pair of electrodes are provided on parallel light-transmitting substrates, such as glass or plastic plates, and liquid crystal is injected between the electrodes.

This display element can be represented by a capacitor (hereinafter referred to as C) as its equivalent circuit. For this purpose, IGF and C are arranged in a 2×2 matrix, for example, as shown in FIG.

In FIG. 1, each address of the matrix constitutes one picture element by two IGFs 10 and 10' forming a pair and C35 as a display section.

These are connected to the bit line as columns (Y direction) 51 and 52, and on the other hand, the gates are connected and leads with a sheet resistance of 0.5Ω/□ or less (equivalent to a film thickness of 800 Å or more for aluminum) are connected to the row (X Direction) 5
3 and 54 (word line bus lines).

Furthermore, 51 is connected to the output of an inverter 50 forming part of a decoder and driver.

Then, for example, 51 and 53 are set as "1", and 5
When 2 and 54 are set to "0", both IGFs 10 and 10' are turned on, and IGFs at other addresses are turned off. Then, by selecting arbitrary bit lines and word lines one by one and turning them on, the electrically equivalent element C
A display section 35 can be selectively turned on.

Generally, when the number of active picture elements in a solid-state display device is, for example, 640 x 525, all of the picture elements are
It is almost impossible to operate IGF normally considering its product yield.

For this reason, the present invention provides a pair of IGFs, and if gate leakage occurs in one of the IGFs, the leaking IGF is separated and removed by laser trimming (hereinafter referred to as LT) from the lead in the X direction. A so-called redundant element was provided for each picture element. The gate electrode of this IGF is LT
Since a sublimable metal, such as a metal whose main component is chromium, is used for the
It is large at 100Ω/□. Therefore, it is extremely important to provide a gate lead with low sheet resistance without using a new contact mask for the gate electrode. In addition, this lead can be used to connect a second
This is advantageous because it can be accomplished without a corresponding increase in the number of masks.

In this way, by combining the present invention based on its design specifications, it was possible to create a solid-state display device for flat televisions that can replace cathode ray tubes.

FIG. 2 shows a longitudinal cross-sectional view of a laminated IGF for carrying out the present invention and its manufacturing process.

This drawing shows a manufacturing example of a longitudinal cross-sectional view taken along plane A-A' on the inverter-driven side of two IGFs provided by one laminate for driving display picture elements shown in FIG. The same holds true when multiple units are manufactured on the same board.

In the drawing, a first conductive film 2 on an insulating substrate 1, such as a quartz glass or borosilicate glass substrate, or an organic film, is provided as a lower electrode and one electrode of a picture element. In this embodiment, a transparent conductive film whose main component is tin oxide doped with fluorine is formed to a thickness of 0.3 μm. This was subjected to selective etching using the first mask. Further, on this upper surface, a first non-single crystal semiconductor 3 having a conductivity type of P or N type is formed.
(hereinafter simply referred to as S1) of 100 to 3000 Å, a first insulator 4 (hereinafter simply referred to as S2) (0.3 to 3μ), and a second semiconductor 5 having the same conductivity type as the first semiconductor (hereinafter simply referred to as S3). (0.1 to 0.5μ) were laminated (stuff, referred to as S). With this lamination
It has a NIN and PIP structure (I is an insulator or a semi-insulator).

On this top surface, ITO (indium tin oxide),
_The second conductive film 6 ( _{hereinafter S5}
Here, a metal (500 to 3000 Å) containing chromium as the main component is used in close contact with the semiconductor, and aluminum is further added to the top surface with a thickness of 0.5 to 2 μm, for example.
It was used in a stacked state with a thickness of 1μ. Furthermore, a second insulator 7 (hereinafter simply
S5) was laminated to a thickness of 0.5 to 5 μm, for example, 1 μm. This insulator is made of silicon oxide film, silicon nitrogen film, or
Organic resin such as PIQ was used.

Next, unnecessary portions of this laminate 60 were removed using a second photomask.

The N and P layers of the first and third semiconductors are N ⁺ N or P ⁺ P, and N ⁺ NINN ⁺ , P ⁺ PIPP ⁺ (I is an insulator or semi-insulator) are P or N, and the first and second Lowering the contact resistance with the second electrode was effective.

In this manner, a laminate 60 consisting of the first conductor 12, the first semiconductor 13, the first insulator 14, the second semiconductor 15, the second conductor 16, and the second insulator 17 is formed. It was obtained by forming using a mask.

Here, plasma gas phase etching is performed using, for example, HF gas or a mixed gas of CF ₊₄ O ₂ at 0.1 to 0.5 torr.
The etching speed was 500 Å/min at 30 W.

After this, these laminates S1, 13, S2, 14,
Intrinsic or P ^- or N ^- covering S3, 15, conductor 16, and insulator 17 to form a channel forming region
A type of non-single crystal semiconductor was laminated as the third semiconductor 24. This third semiconductor 24 is formed on the substrate by silane glow discharge (PCVD method), photo CVD method,
Using the LTCVD method (also called HOMOCVD method), the
℃, 0.1torr, 30W, 13.56MHz, and is amorphous or semi-amorphous with hydrogen or fluorine added, or a non-single crystal with a polycrystalline structure. It uses silicon semiconductor. The present invention focuses on amorphous or semi-amorphous semiconductors.

Furthermore, in the same reactor, a silicon nitride film 25 is formed on the top surface of the silicon nitride film 25 by optical CVD method using disilane and ammonia by a gas phase reaction using mercury excitation method, without exposing the third semiconductor surface to the atmosphere. Saha 300
~2000Å.

This insulating film may be immersed in a nitrogen or ammonia atmosphere activated by electromagnetic energy at a frequency of 13.56 MHz to 2.45 GHz at 100 to 400° C. to form silicon nitride in a solid phase gas phase reaction.

In addition, DMS (H ₂ Si (CH ₃ ) ₂ ), MMS (H ₃ Si
Silicon carbide may be formed by a PCVD method using (CH ₃ )) or a photoCVD method.

The third semiconductor 24 forms a diode junction with S1 and S3.

In FIG. 2B, a third conductive film 18 was then formed to a thickness of 100 to 2000 Å to cover the gate insulating film 25. As shown in FIG.

The conductive film 18 was a light-transmitting conductive film such as ITO (indium tin oxide), tin oxide, or indium oxide, or a heat-resistant and sublimable conductive film containing Si, Mo, or Cr as a main component.

This third conductive film having sublimation property has a thickness of 100 to 2000 Å, preferably 300 to 2000 Å, for trimming.
1200 Å, resulting in a sheet resistance of 10~
It has increased to 100Ω/□.

Thereafter, a portion of the structure was covered with resist using a third mask, and then anisotropic etching was performed. Then the second
As shown in FIG. It was possible to completely remove the conductor. This anisotropic etching is made of chromium, ITO
In this case, it could be carried out by ion etching of _CC14 . Furthermore, using this gate electrode as a mask, the gate insulating film and the upper surface of the third semiconductor are removed by ion etching using CF ₄ , and the gate electrode 19 and the channel forming region 9 under the gate insulating film are etched only along the side surfaces of the stack. was able to be created. After this, a fourth photoetching step was carried out. This step is for bringing the third conductive film 18 for the gate electrode into contact with the second conductor under the interlayer insulator 17 using the fourth conductive film based on design specifications. Furthermore, an open hole 21 was made. At the same time, as shown in FIG. 3, unnecessary portions other than the gates provided by anisotropic etching were etched on all sides of the laminate.
Then, the two sides of the laminate 60 are IGF10,1
0' was provided independently. In addition, two IGFs 20 and 20' are constructed for the inverter, and a fourth conductive film is laminated on the upper surface of the conductive film to a thickness of 0.5 to 3 μm, for example, 1.5 μm, by vacuum evaporation using a conductor whose main component is aluminum. Sheet resistance 0.5Ω/□
It is preferably 0.1Ω/□ or less.

Then, Fig. 2 D, the part 50 of Fig. 3, and the part 4
As shown in Figure A, the second conductive films 51, 16 and the gate electrode 19'' could be electrically connected.

Thereafter, a resist was formed on the upper surface, and the aluminum for the word line (X direction) 53 shown in FIG. 3 was etched using a fifth mask. At the same time, as shown in FIG. 2D, a connection 41 between the second conductor 16 and the gate electrode 19'' was established by a contact 21.

Thus, Figure 2D was obtained.

As is clear from FIG. 2D, the two IGFs 20 and 20' have two channels 9 and 9' using both sides of the stacked body 60, and have a source or drain 13 and a drain or source 15. , gates 19, 19''.

Furthermore, in the IGF of the present invention, the electron mobility is 5 to 30 times higher than that of holes, so it is preferable to use an N-channel type. Furthermore, it is effective to configure a pair of P-channel IGFs on other parts of the substrate to form complementary transistors.

FIG. 3 is a plan view of a portion of the solid-state display device of the present invention shown in FIG. 1 using the IGF shown in FIG. 2.

Figure 3 shows 1, 1, 1, 2, 2, 1 in Figure 1,
Corresponding to address 2,2, especially IGF of address 1,1
and a plan view of an inverter 50. Furthermore, Fig. 4 A and B are B-B' and C of Fig. 3, respectively.
-C' is a vertical cross-sectional view. Also, A- in Figure 3
FIG. 2D corresponds to the longitudinal cross-sectional view of A'.

The electrode 36 extending from the lower electrode 12 of this IGF (provided on the lower side in FIG. 4B) is
It is connected to a liquid crystal (capacitor) 35 composed of picture elements. A ground electrode 34 of the liquid crystal 35 is provided on the other substrate 1' side.

In FIG. 3, the gate electrodes 19 and 19' provided along the stacked body 60 are connected to the leads 5 in the X direction provided perpendicularly to the stacked body 60.
It is connected to 3. The second conductive film 51 provided inside the stacked body 60 was configured as a lead wiring in the Y direction. In this way, it was possible to have a matrix configuration in the X and Y directions and a 1Tr/pixel structure.

Furthermore, as is clear from FIGS. 2 to 4, this display could be manufactured by photoetching five times. Conventional horizontal channel type
It was used seven times in the multilayer wiring structure at IGF, but
The configuration of the present invention was able to reduce this number of times by two. Further, the area required for the IGF of the display of the present invention is 1% or less of the total area.

The display area was 91% and the lead area was 8%. When the present invention manufactures a large 20-inch display, the minimum line width of the mask is 25μ using current mask manufacturing technology. However, the present invention requires
Although 25μ is used as the leads in the X and Y directions, the channel length of this IGF is 1μ or less, which has the great advantage of not being subject to mask precision limitations. Since the IGF has a short channel length, the area required for the IGF on the substrate can be reduced, and the accuracy of photolithography does not limit the upper limit of the operating frequency.

Furthermore, since these picture elements operate at high frequencies, the frequency characteristics of IGF are extremely important.
The IGF of the present invention was able to have a cutoff frequency of 10 MHz or more (17.5 MHz) (N-channel IGF) at V _DD = 5 V and V _GG = 5 V. V _fh =0.2~
2V was made possible by controlling the concentration of boron impurity in the third semiconductor 24.

Furthermore, in the present invention, the IGFs are configured as a pair, and the gate electrode of one of the defective IGFs is irradiated from above with laser light, for example, a YAG laser light with a Q switch, to sublimate and vaporize the gate electrode. As a result, the lead 53 is separated from the lead 53, reducing the overall panel yield by 10%.
We were able to improve the yield to 50% (defective picture elements are considered good if there are 5 or fewer defective picture elements). In addition, laser light (here wavelength 1.06μ or
(using a 0.53μ YAG laser) has a diameter of 10-30μ. However, since the gate electrodes of the pair of IGFs of the present invention are separated by about 30 μm, the pixels on the shot side of one of the IGFs could be removed without any hindrance to the other IGFs forming the pair.

Another embodiment of the invention is shown in FIG.

FIG. 5A corresponds to the enlarged plan view of FIG. 1 55 (55 in FIG. 3). Also, Figure 5B is Figure 5A
It is a longitudinal cross-sectional view of AA' of.

As is clear from the drawing, the gate electrodes 19,1
A source or drain electrode 12 of the IGF is present below 9'. Further, the IGF electrode and the picture element electrode 36 are separated by 82, as shown in FIG. Therefore, as shown in 81, the current goes around the IGF and goes to one electrode 36 of the picture element.
It is connected to As a result, it was possible to avoid disposing the gate electrode above one electrode of the picture element without using any particular anisotropic etching.

In FIG. 5B, if the electrode 12 and the laminate 60 are made to have the same shape in the same process, no misalignment between the electrode and the laminate will occur during the process, and an increase in parasitic capacitance can be prevented.

In FIGS. 3 and 5, only the picture element portions are filled with liquid crystal 35 using IGF overcoat polyimide resin. Also, the peripheral area of the picture element is 2
It also serves as a spacer (thickness 3 to 15 μm) between the two electrodes 36 and 34 (see Figure 4B), and in addition, this spacer is used to blacken the peripheral area of the picture element (non-reflective) and use it as a black matrix. I used them together. This black matrix made it possible to improve the contrast of this picture element. In addition, there are 35 areas that are displayed, such as GH (guest host)
A liquid crystal such as a mold is filled, and this picture element is IGF10,1
Control was performed by turning on and off 0'.

In the present invention, the distance between the two electrodes 36 and 34, which have been subjected to alignment treatment for the liquid crystal 35, is set to 3 to 15 μm, for example, GH type liquid crystal is injected into the gap, and in addition, red, green, It is possible to display this disc play in color by embedding a blue filter. Then, the three elements of red, green, and blue may be arranged alternately.

Of course, each pixel itself can be colored red, green, etc. by EL.
It goes without saying that the light may be emitted in blue.

Furthermore, in FIG. 4A, an inverter is shown, but between the drain electrode (power supply potential) 37 and the source electrode (ground potential) 39, there is an input 38 of the IGF, and a load for the depletion type.
The gate electrode of IGF 20' and output 51 are connected by 41.

Furthermore, because of the laminated type IGF, the inverter (see Figure 4A), resistor, It became possible to make a capacitor. It became possible to develop it into a full-color display.

In the present invention, it is effective to use a semiconductor instead of the first insulator of the laminate and use the periphery of this side as a channel forming region. However, although such a structure has the advantage that there is no step of forming a third semiconductor, on the other hand, since the surface of this semiconductor is exposed to an etching atmosphere, the interface state density is lower than that of the method using the third semiconductor described above. It has the disadvantage that it is larger than the other IGFs, and variations occur between each IGF.

The non-single crystal semiconductor in the present invention is silicon, germanium or carbon silicon (SixC _1-X 0<x<
1) was used.

The third conductive film constituting the gate electrode in the present invention contains chromium as a main component. That is, copper in Cr,
Silver or the like may be added within a range that does not impair sublimability. Additionally, phosphorus and boron may be added. In addition, silicon may be provided on the upper surface of the guest insulator in close contact with the guest insulator, and a sublimable metal film such as Cr or Mo may be provided in multiple layers.

[Brief explanation of drawings]

FIG. 1 shows an equivalent circuit of a solid-state display device of the present invention having a matrix structure in which an insulated gate type semiconductor device and a capacitor are used as picture elements. Figure 2 A, B, C,
D is a vertical cross-sectional view showing the steps of the stacked insulated gate semiconductor device of the present invention. FIG. 3 is a longitudinal cross-sectional view of a solid-state display device showing a flat display in which the stacked insulated gate semiconductor device of the present invention, a capacitor, and a display portion are integrated. Figure 4 is Figure 3B-
A vertical cross-sectional view of B' and C-C' is shown. FIG. 5 shows another structure of the invention.

Claims (1)

[Claims] 1. A first semiconductor, a first insulator, a second semiconductor, a second conductive film, and an interlayer insulator are arranged in approximately the same shape on an electrode of a first conductive film on an insulating substrate. a stacked laminate, the first and second semiconductors forming a drain and a source, a third semiconductor adjacent to a side of the laminate forming a channel forming region; In the insulated gate type semiconductor device in which a gate insulating film on a third semiconductor and a gate electrode provided by a third conductive film are disposed on a side surface of the stacked body, the third conductive film and the gate electrode are An insulated gate field effect semiconductor device, characterized in that the second conductive film and the second conductive film are connected to each other by a fourth conductive film through an opening provided in the interlayer insulator. 2 selectively removing the first conductive film on the insulating substrate to form a first electrode; and forming a first conductive film on the electrode.
After forming a semiconductor, a first insulator, a second semiconductor, a second conductive film, and an interlayer insulator, they are selectively removed, and a second semiconductor is formed adjacent to the side surface of the stacked body in approximately the same shape. forming a gate electrode using the semiconductor of No. 3, a gate insulator, and a third conductive film;
selectively removing the interlayer insulator, the third semiconductor, the gate insulator, and the gate electrode to form a contact opening; and forming a fourth conductive film to form the second conductive film. A method for manufacturing an insulated gate field effect semiconductor device, comprising the step of connecting the film and the third conductive film to each other.