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JPH0691034B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0691034B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0691034B2
JPH0691034B2 JP18910086A JP18910086A JPH0691034B2 JP H0691034 B2 JPH0691034 B2 JP H0691034B2 JP 18910086 A JP18910086 A JP 18910086A JP 18910086 A JP18910086 A JP 18910086A JP H0691034 B2 JPH0691034 B2 JP H0691034B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
region
area
via hole
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18910086A
Other languages
Japanese (ja)
Other versions
JPS6344724A (en
Inventor
良一 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18910086A priority Critical patent/JPH0691034B2/en
Publication of JPS6344724A publication Critical patent/JPS6344724A/en
Publication of JPH0691034B2 publication Critical patent/JPH0691034B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔概要〕 本発明は半導体装置の製造方法において、 ビアホール上に形成したAlをレーザ光照射で溶融してビ
アホールを埋込む際、レーザ光照射領域の周辺端部に対
応する導電層に所謂よりを生じて高品質の半導体チップ
を製造し得ない不都合をなくすため、 レーザ光照射領域の周辺端部が半導体チップにおける集
積回路の形成された領域の外側に対向するようにレーザ
光を照射することにより、 表面によりのない高品質の半導体チップを得るようにし
たものである。
DETAILED DESCRIPTION OF THE INVENTION [Outline] In the method for manufacturing a semiconductor device, the present invention corresponds to a peripheral edge portion of a laser light irradiation region when Al formed on the via hole is melted by laser light irradiation to fill the via hole. In order to eliminate the inconvenience that high quality semiconductor chips cannot be produced due to so-called twisting in the conductive layer, the peripheral edge of the laser light irradiation area should face the outside of the area where the integrated circuit is formed in the semiconductor chip. By irradiating with a laser beam, a high quality semiconductor chip free from the surface is obtained.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法、特に、ビアホール(コ
ンタクトホール及びスルーホールの総称)にAl堆積膜を
パルスレーザ光照射で溶融して埋込む半導体装置の製造
方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which an Al deposited film is melted and embedded in a via hole (a generic term for a contact hole and a through hole) by pulsed laser light irradiation.

〔技術の背景〕[Background of technology]

第3図はビアホールにAlを堆積する断面図を示す。1は
Si基板、2は層間絶縁膜、2aはビアホールである。この
ビアホール2aにAl3を堆積するに際し、スパッタや蒸着
等の方法を用いると、特に、アスペクト比(深さ/直
径)の高いビアホールでは、同図(A)に示すようにビ
アホール側壁への付着率が悪く、Si基板1との接続不良
を生じ易い。同様にして多層Al配線構造では、上層Al配
線と下層Al配線との接続不良を生じ易い。
FIG. 3 shows a sectional view of depositing Al in the via hole. 1 is
Si substrate, 2 is an interlayer insulating film, and 2a is a via hole. When depositing Al3 in the via hole 2a, if a method such as sputtering or vapor deposition is used, particularly in the case of a via hole having a high aspect ratio (depth / diameter), as shown in FIG. Is poor, and poor connection with the Si substrate 1 is likely to occur. Similarly, in the multilayer Al wiring structure, a connection failure between the upper layer Al wiring and the lower layer Al wiring is likely to occur.

このような接続不良を生じないようにするには、Al3の
上方からパルスレーザ光4を照射することによってAl3
を溶融して同図(B)に示すようにビアホール2aを埋込
んでAl層3aとなすことが考えられる。
In order to prevent such a connection failure, the pulse laser beam 4 is irradiated from above the Al3 so that the Al3
It is conceivable that the via hole 2a is filled with the aluminum oxide by melting it to form the Al layer 3a.

然るに、一般に、第4図に示す如く、パルスレーザスポ
ット領域5の周辺端部に対応するAl層6には膜厚が増大
して所謂「より」6aを生じ、チップ表面を平坦に形成し
得ない。特に、半導体チップ1個分の領域の一辺をAと
した場合、この一辺Aの領域内に「より」6aが入るよう
な領域5をもつパルスレーザ光を用いると、高品質の半
導体装置が得られない不都合がある。
However, in general, as shown in FIG. 4, the Al layer 6 corresponding to the peripheral edge portion of the pulse laser spot region 5 has an increased film thickness to produce a so-called "strand" 6a, which can form a flat chip surface. Absent. In particular, when one side of the area for one semiconductor chip is A, the use of the pulsed laser light having the area 5 in which the "strand" 6a is included in the area of the one side A provides a high quality semiconductor device. There is an inconvenience.

〔発明の手段〕[Means for Invention]

本発明になる半導体装置の製造方法は、第1図に示す如
く、レーザ光照射領域11の周辺端部が半導体チップにお
ける集積回路の形成された領域7の外側にあたる様にレ
ーザ光を照射する。
In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, the laser light is irradiated so that the peripheral edge portion of the laser light irradiation region 11 is outside the region 7 where the integrated circuit is formed in the semiconductor chip.

〔作用〕[Action]

レーザ光照射領域の周辺端部が半導体チップにおける集
積回路の形成された領域の外側になるようにしたため、
表面に「より」のない高品質の半導体チップを得ること
ができる。
Since the peripheral edge of the laser beam irradiation area is outside the area where the integrated circuit is formed in the semiconductor chip,
It is possible to obtain a high-quality semiconductor chip without "twist" on the surface.

〔実施例〕〔Example〕

第2図は半導体チップにレーザスポット領域を位置合わ
せした図を示す。同図(A)中、7は1個の半導体チッ
プ内の集積回路の形成された領域で、その領域を斜線で
示す。8はスクライブラインで、半導体チップを大量生
産する際に用いる作成ラインである。9はパルスレーザ
スポットで、その領域を破線で包囲して示す如く、半導
体チップの集積回路形成領域7の領域より僅かに大に設
定されている。
FIG. 2 shows a diagram in which the laser spot region is aligned with the semiconductor chip. In FIG. 1A, 7 is a region in which an integrated circuit is formed in one semiconductor chip, and the region is indicated by diagonal lines. A scribe line 8 is a production line used when mass-producing semiconductor chips. Reference numeral 9 denotes a pulse laser spot, which is set slightly larger than the area of the integrated circuit forming area 7 of the semiconductor chip, as shown by surrounding the area with a broken line.

このように半導体チップの集積回路形成領域7とレーザ
スポット領域とを位置合わせし、試料の移動周期とパル
スレーザのパルス照射周期とを同期させ、照射を行なう
と、第1図に示す如く、パルスレーザスポット領域11の
周辺端部は半導体チップ集積回路形成領域7(一辺Aで
示す)の外側に形成され、Al層10の「より」10aは半導
体チップ7の領域外に形成される。つまり、「より」10
aが形成される位置はスクライブライン8に上になり、
ここは半導体チップとして不要の部分である。
In this way, when the integrated circuit forming region 7 of the semiconductor chip and the laser spot region are aligned and the sample movement period and the pulse irradiation period of the pulse laser are synchronized and irradiation is performed, as shown in FIG. The peripheral edge of the laser spot region 11 is formed outside the semiconductor chip integrated circuit forming region 7 (shown by one side A), and the “twist” 10a of the Al layer 10 is formed outside the region of the semiconductor chip 7. In other words, “more” 10
The position where a is formed is above the scribe line 8,
This is an unnecessary part as a semiconductor chip.

第2図(A)ではパルスレーザスポット9の領域を半導
体チップ7の1個分の領域より僅かに大に設定したもの
であるが、同図(B)の破線に示す如く、パルスレーザ
スポット9′の領域を半導体チップ7の4個分の領域よ
り僅かに大に設定してもよい。このようにすれば、より
高能率で照射を行ない得る。
In FIG. 2A, the area of the pulse laser spot 9 is set slightly larger than the area of one semiconductor chip 7, but as shown by the broken line in FIG. The area ′ may be set to be slightly larger than the area for four semiconductor chips 7. By doing so, irradiation can be performed with higher efficiency.

なお、ビアホール2aに埋込む物質としては純粋のAlの
他、Alと他の物質との合成物でもよい。
The substance to be buried in the via hole 2a may be pure Al or a compound of Al and another substance.

〔発明の効果〕〔The invention's effect〕

本発明によれば、レーザ光照射領域の周辺端部が半導体
チップにおける集積回路の形成された領域の外側に位置
するようにレーザ光を照射したため、表面に発生する
「より」をチップの集積回路形成領域から除外できる等
の特長を有する。
According to the present invention, since the laser light is irradiated so that the peripheral end portion of the laser light irradiation region is located outside the region where the integrated circuit is formed in the semiconductor chip, the “twist” generated on the surface is integrated into the integrated circuit of the chip. It has the feature that it can be excluded from the formation area.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明方法の一実施例を示す図、 第2図は半導体チップとレーザスポット領域とを位置合
わせした図、 第3図はビアホールにAlを堆積する断面図、 第4図はAl層に形成されるよりを示す図である。 図において、 1はSi基板、 2は層間絶縁膜、 2aはビアホール、 3,10はAl層、 4はパルスレーザ光、 7は半導体チップ集積回路形成領域、 8はスクライブライン、 9,9′,11はレーザスポット領域、 10aは「より」、 Aは半導体チップの集積回路形成領域の一辺である。
FIG. 1 is a diagram showing an embodiment of the method of the present invention, FIG. 2 is a diagram in which a semiconductor chip and a laser spot region are aligned with each other, FIG. 3 is a sectional view in which Al is deposited in a via hole, and FIG. 4 is Al. It is a figure which shows what is formed in a layer. In the figure, 1 is a Si substrate, 2 is an interlayer insulating film, 2a is a via hole, 3 and 10 are Al layers, 4 is a pulse laser beam, 7 is a semiconductor chip integrated circuit formation region, 8 is a scribe line, 9 and 9 ', Reference numeral 11 is a laser spot area, 10a is "strand", and A is one side of an integrated circuit formation area of a semiconductor chip.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ビアホール(2a)上に形成したアルミニウ
ム(3)、又は、アルミニウムと他の物質との合成物を
レーザ光(4)で溶融して該ビアホール(2a)を埋込む
際、該レーザ光(4)照射領域(11)の周辺端部が半導
体チップにおける集積回路の形成された領域(7)の外
側に対向するように該レーザ光(4)を照射することを
特徴とする半導体装置の製造方法。
1. When the aluminum (3) formed on the via hole (2a) or a compound of aluminum and another substance is melted by a laser beam (4) to fill the via hole (2a), A semiconductor characterized by irradiating the laser light (4) so that the peripheral edge of the laser light (4) irradiation region (11) faces the outside of the region (7) in which the integrated circuit is formed in the semiconductor chip. Device manufacturing method.
JP18910086A 1986-08-12 1986-08-12 Method for manufacturing semiconductor device Expired - Lifetime JPH0691034B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18910086A JPH0691034B2 (en) 1986-08-12 1986-08-12 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18910086A JPH0691034B2 (en) 1986-08-12 1986-08-12 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6344724A JPS6344724A (en) 1988-02-25
JPH0691034B2 true JPH0691034B2 (en) 1994-11-14

Family

ID=16235352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18910086A Expired - Lifetime JPH0691034B2 (en) 1986-08-12 1986-08-12 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0691034B2 (en)

Also Published As

Publication number Publication date
JPS6344724A (en) 1988-02-25

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