JPH0691149B2 - Method for evaluating integrated circuit device and semiconductor device for evaluating integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention, when evaluating the yield in the case of manufacturing a memory circuit or a logic circuit formed by repeating unit circuits, evaluates the yield for each technological element of manufacture. The present invention relates to a highly efficient yield evaluation method capable of evaluating and estimating the yield of the integrated circuit device as a whole and clarifying the yield factor of each technical element, and an apparatus for implementing the method.

[Conventional technology]

Conventionally, when evaluating the yield of an integrated circuit at the development stage, the target integrated circuit itself was prototyped and the yield was evaluated, but at the beginning of development, the yield of the target integrated circuit was low and evaluation was impossible. There was a drawback that there is.

On the other hand, in parallel with this, a dedicated test element group (TEG) pattern is formed on the same wafer as the target integrated circuit or on another wafer, these are measured, and the yield is evaluated for each technological element. (Kondo et al., The Institute of Electronics and Communication Engineers, Vol. 62, No. 4, 39
See page 3, April 1979 "). An example of a conventional yield evaluation TEG pattern is shown in FIG. FIG. 5A is a pattern diagram showing an example of a pattern for measuring a wire break and a short circuit or a leak between the wires when the wire passes through a step directly. Further, FIG. 5 (b) is a pattern diagram showing a lower layer wiring and an upper layer wiring connected in multiple stages by contact holes, and the yield of contact connection is evaluated.

[Problems to be Solved by the Invention]

Such a conventional example has the following drawbacks.

In order to make various evaluations within one chip, it is necessary to allocate the regions within a limited chip area, and therefore the area allocated to one evaluation item becomes small. For example, in the case of FIG. 5 (a), the total length of wiring is about
It was 20 mm. On the other hand, for example, 256 Kbit static RA
Taking the case of M (256K SRAM) as an example, the total length of the first layer aluminum wiring is 2.8 m. Here, the yield Y at which the wiring is not broken is represented by the following equation.

Y = exp (-D · L) where D is the defect rate and L is the wiring length. Assuming that the yield of 256K SRAM is determined by disconnection and short circuit in the six important mask layers, and assuming that the yield level at the time of evaluation is 10%, the yield for each element is approximately 83%. When the yield Y for each element is Y = 83%, D = 6.6 × 10 ^-5 /
mm, the yield for the above TEG is YT = 99.9
%. If 45 chips (10 mm □, 4 inch wafer) can be obtained from one wafer, the number of defective products in one lot (25 wafers) will be 1-2, and the yield evaluation accuracy will be significantly deteriorated. If the yield level further increases, evaluation becomes impossible. This situation is shown in Fig. 5 (b).
The case is almost the same.

[Means for Solving the Problems]

In order to solve such a problem, the present invention provides a method for evaluating a yield of an integrated circuit device, which comprises repeating unit circuits, divides the integrated circuit device in which circuit constituent elements are arranged into a predetermined scale, and divides the divided integrated circuits. The yield of the wiring layer connection, the line leak of the wiring layer, and the leak between the wiring layers is evaluated for each circuit device portion, and the yield of the integrated circuit device is obtained from the result of the yield.

Further, in an integrated circuit device composed of repeating unit circuits, an integrated circuit in which circuit constituent elements are arranged is divided into a scale capable of yield evaluation, and wiring layer connections and wiring layers are formed on the divided integrated circuit device portions. The pattern is formed so that the yields of the inter-line leakage and the inter-wiring layer leakage can be measured.

[Action]

In the present invention, the yield reaches an evaluable level, the yield can be evaluated, and which technical element has the problem can be clarified.

〔Example〕

According to the present invention, the portion of the lower layer below the wiring of the memory circuit device or the logic circuit device whose yield is to be evaluated is used as it is, and this is divided into an appropriate scale capable of yield evaluation, and a dedicated wiring layer is formed above it. However, it is possible to evaluate the yield for each technical element that contributes to the yield.

Next, the difference between the features of the present invention and the prior art will be described. A feature of the present invention is that, in a yield evaluation method for an integrated circuit device comprising repeating unit circuits, the integrated circuit device in which circuit constituent elements such as a transistor, a diode, a capacitor, and a resistor are arranged is divided into a predetermined scale. Then
A method for evaluating the yield of the wiring layer connection, wiring line leakage of the wiring layers, and leakage between the wiring layers for each of the divided integrated circuit device parts, and obtaining the yield of the integrated circuit device from the yield result, and a test element therefor Group (TE
G) is to provide. In the prior art, the underlying pattern of the integrated circuit device whose yield is to be evaluated is used as it is, and further, there is no idea of dividing the scale so that the yield can be evaluated even if the yield varies greatly. The yield of the integrated circuit itself is evaluated, or a relatively small TE for each dedicated element is used independently.
We designed the G and mounted it on a single chip for evaluation.

In the embodiments of the present invention, a method for evaluating the yield of a 256 Kbit MOS static random access memory (256KSRAM) and a TEG for evaluation used at that time will be described in detail. Here, it can be considered that the yield of the MOS memory is almost determined by the yields of the following items in the cells occupying most of the whole. That is, junction region: junction leak, gate region: gate insulating film leak, word line: disconnection or short, bit line: disconnection or short.

In the present invention, until the contact hole is formed, the MOS memory is manufactured by the same process, and the process after the contact hole is separately prepared by a pattern in which each item can be evaluated. At this time, the 256 Kbit area is appropriately divided so that the yield can be easily evaluated.
In this embodiment, 256K is divided into three 64K areas and three 16K areas. The rest is the lead-out area up to the pad. This is shown in FIG. In FIG. 1, 10 is a pad, A
1, B1, C1, A2, B2, C2 indicate areas. Each of 64K and 16K areas has the following three types (areas A1 and A2, areas B1 and B2, areas
C1 and C2).

First, the areas A1 and A2 will be described. Fig. 2 (a)
Is made on the basis of aluminum (A1) of the first layer of the memory cell, and it is possible to evaluate the disconnection of the word line 20, the disconnection of the power supply line 21, and the line leakage of A1. FIG. 2 (b) is made based on the second layer aluminum (Al2) of the memory cell, and it becomes possible to evaluate the disconnection of the bit line 22, the disconnection of the ground line 23 and the line leakage of Al2. There is.

Next, the areas B1 and B2 will be described. Fig. 3 (a)
Similarly shows A1 of the memory cell, and the word line
30 breakages can be evaluated, and the A1 electrode is used for aluminum interlayer leak evaluation. FIG. 3 (b) constitutes an Al2 electrode for evaluating aluminum interlayer leakage. FIG. 3 (c) shows the state of A1 and Al2 overlapping on the plane, and FIG. 3 (d) shows the first layer of aluminum (A
1) 31 and the second layer of aluminum (Al2) 32 are shown in the state of overlap in a cross section.

Next, the areas C1 and C2 will be described. Figure 4 (a)
Shows the pattern of A1, which is connected to the gate 40, the p ⁺ junction 41 and the n well 42 as shown in FIG. Fourth
FIG. 3B shows the connection of wirings in the process after the contact hole.

The target 256K SRAM was obtained by measuring the insulation resistance of each of the above TEGs when a DC voltage was applied and evaluating the yield of each.
Yield can be estimated.

Note that the above description is for a 256K SRAM, but a master slice LSI, standard cell type logic L
The same can be applied to an LSI having a relatively regular pattern such as SI.

〔The invention's effect〕

As described above, the present invention has an effect that the yield reaches the evaluable level and the yield can be evaluated by dividing the scale into a scale in which the yield can be evaluated. In addition, by performing the evaluation divided into each technical element, it is possible to clarify which technical element has the problem. Therefore, it is possible to shorten the LSI development period and improve efficiency.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a wiring pattern diagram of 4 bits in areas A1 and A2 of the embodiment of the present invention, and FIG. 3 is an area of the embodiment of the present invention. FIG. 4 is a pattern diagram showing a wiring pattern for 4 bits of the B1 and B2 portions and the degree of wiring overlap, and FIG.
FIG. 5 is a pattern diagram showing a 4-bit wiring pattern of the C2 portion and its connection to the gate electrode and diffusion layer, and FIG. 5 is a pattern diagram showing a conventional wiring connection and contact multistage connection yield evaluation TEG. 10 …… Pad, 20,30 …… Word line, 21 …… Power line, 22
...... bit line, 23 ...... ground wire, 31 ...... first layer aluminum, 32 ...... second layer aluminum, 40 ...... gate electrode,
41 …… n ⁺ diffusion layer, 42 …… n well.

Claims (2)

[Claims] 1. A method for evaluating a yield of an integrated circuit device comprising repeating unit circuits, comprising: a transistor, a diode,
The integrated circuit device in which circuit constituent elements such as capacitors and resistors are arranged is divided into a scale capable of yield evaluation, and wiring layers are connected, line-to-line leakage in the wiring layer, and wiring for each divided integrated circuit device portion. A method for evaluating an integrated circuit device, comprising: evaluating the yield of leakage between layers and determining the yield of the integrated circuit device from the result of the yield. 2. In an integrated circuit device composed of repeating unit circuits, the integrated circuit provided with circuit constituent elements such as transistors, diodes, capacitors, and resistors is divided into scales capable of yield evaluation, and divided. A semiconductor device for evaluating an integrated circuit device, wherein a pattern is formed on the integrated circuit device portion so that a yield of a connection between wiring layers, a leak between lines of the wiring layer, and a leak between wiring layers can be measured.