JPH0474866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to semiconductor integrated circuits, and particularly to a pattern layout that allows easy model development in order to meet the demands of custom ICs. (b) Prior art In general, Japanese Patent Application Laid-Open No. 59-84542 (H01L21/
76), semiconductor integrated circuit technology in which multiple circuit blocks are formed on the same semiconductor substrate is
The structure is as shown in the figure. FIG. 8 is a schematic plan view of the semiconductor chip 101, and a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and have different functions. This circuit block is formed in an N ^- type region 103 on a P ^- type semiconductor substrate 102 as shown in FIG. It is sectioned.
Here, they are shown as block b and block c. The P ⁺ type region 104 for this division has one end in contact with the P ^- type semiconductor substrate 102, and
The other end is ohmicly connected to a ground line 106 through an oxide film 105 on the semiconductor surface. A ground line 106 extends from each block to the ground bonding pad GND at the left end, converging in the center of the integrated circuit. Next, the power supply line V _CC of each block circuit is
As shown in the figure, they are grouped around the outer periphery of the integrated circuit and are individually connected to power supply bonding pads. On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the blocks have different sizes. (c) Problems to be solved by the invention As mentioned above, since the sizes of circuit blocks a to f are different, it is possible to efficiently solve all of these circuit blocks.
In order to fit them into the semiconductor chip 101, the sizes of each circuit block interact with each other, making it difficult to integrate them into the same chip. Also, if you delete circuit block a and insert, for example, another circuit block a' with improved characteristics, or if you try to add circuit block g with a different function to the circuit block configuration shown in FIG. Because the sizes were different, it was necessary to recreate all the patterns. On the other hand, the MOS type capacitor included in a circuit block has a very large area, making it difficult to arrange it in this circuit block. Therefore, in recent years, the lifespan of products has become extremely short, and when trying to incorporate a unique circuit desired by a user into a certain chip, even though the user wants a short delivery time, The problem was that it required a very long lead time to recreate the circuit pattern. Furthermore, since a MOS type capacitor is generally formed within an N type island region surrounded by a P ⁺ type isolation region or an N ⁺ type buried region, a PN junction capacitance occurs. This PN junction capacitance occurs at the junction between the N type island region and the P ⁺ type divided region, or at the junction between the N type island region or the N ⁺ type buried region and the P type semiconductor substrate. On the other hand, since this MOS type capacitor has a very large area, the PN junction area naturally increases, and the capacitance value becomes very large. Therefore, leakage current from this capacitor flows to the semiconductor substrate,
This had the problem of adversely affecting other electronic circuit blocks. (d) Means for Solving the Problems The present invention has been made in view of the above problems, and the upper surface of the semiconductor chip 1 is divided into a large number of mats of substantially the same size along the partition line 4 , and a plurality of mats with different functions are arranged. This problem is solved by accommodating the electronic circuit blocks in one or more integral number of mats, and integrating the capacitors 7 included in the electronic circuit blocks into specific mats. Further, electrodes 26, 27, and 28 are provided in contact with the isolation region 18 around a specific mat where the capacitor 7 is integrated or in the area of the mat, and the leakage current is sucked out by these electrodes to solve the problem. (E) Effect According to the present invention, the upper surface of the semiconductor chip 1 is divided into a large number of mats of substantially the same size by the partition line 4 , and a plurality of electronic circuit blocks having different functions are housed in an integral number of mats. , the capacitor 7 included in the electronic circuit block is integrated on a specific mat among the integer number of mats, and the capacitor 7 is
Since desired circuits are connected in multiple layers, the capacitor layout becomes very easy, and each electronic circuit block can be designed, and the electronic circuit block can be divided into a fixed number of elements to design each mat. Therefore, parallel design can be performed by dividing each electronic circuit block, and the design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic circuit block and for each mat, there is no need to change the design of the entire IC. On the other hand, as shown in Fig. 2A to Fig. 2C, there is a P ⁺
A ground line 27 in contact with the type isolation region 18 and a ground line 26 in contact with the P ⁺ type isolation region 18 are formed with a suction electrode 28 disposed in a comb-like shape, and are connected to the lower layer of the MOS type capacitor 7. This electrode 2
It is sucked out at 6, 27, and 28. Furthermore, since the capacitor is integrated in a specific mat, leakage current can be concentrated around this specific mat. Therefore, leakage current that affects other electronic circuit blocks can be eliminated. (F) Embodiment First, a first embodiment of the present invention will be described in detail with reference to FIG. The upper surface of the semiconductor chip 1 is divided into 10 mats A to J. Each of the mats A to J is separated by a partition line 4 in which a power line 2 and a ground line 3 extend adjacently and in parallel. Regarding the arrangement of the power supply lines 2 and ground lines 3 forming the division lines 4 , the power supply lines 2 shown by solid lines are provided on the left side of each mat A to J, and the ground lines 3 shown by dashed lines are provided on the right side. Therefore, only the division lines of the mats A and J at both ends are formed of either the power supply line 2 or the ground line 3, and the intermediate division line is formed of both. A power supply line 2 and a ground line 3 adjacent to each mat A to J are integrated in each mat and supply power to the circuit blocks. Further, the power supply line 2 and ground line 3 of each division line 4 are connected in a comb-like manner to face each other to a first supply line 5 and a second supply line 6 formed above and below the mat, respectively. The first and second supply lines 5, 6 are led to a power supply pad V _CC and a ground pad GND in pads provided around the pellet. As will become clear later, each power supply line 2, ground line 3, and first and second supply lines 5, 6 are basically realized by one layer of two-layer wiring. Each pine A divided by the above-mentioned division line 4
~J is formed into a shape of substantially the same size, specifically, the width is set so that six NPN transistors can be arranged in a row, and the length is set to a certain number of elements that is easy to design, for example, about It is set so that 100 elements can be laid out. The size of this mat depends on the electronic circuit block that is converted into an IC.
It can be arbitrarily selected depending on the number of elements that are easy to design. The circuit elements integrated in the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are made by the first electrode layer of the two-layer wiring. connected, and exceptionally crossed over at the second layer of electrodes. Also, as will become clear later, the main capacitors 7 included in the electronic circuit blocks of Mats E to Mats J are integrated in Mats E as indicated by the rectangle indicated by the broken line. Next, with reference to FIGS. 3A and 3B, the circuit elements integrated within the mat and the partition lines 4 will be specifically explained. FIG. 3A is an enlarged top view of the vicinity of mat B.
The division line 8 indicated by the dashed line on the left is the division line 4 provided between mat A and mat B in FIG. 1, and the division line 9 indicated by the dashed dot line on the right
is a partition line 4 provided between mat B and mat C in FIG. Between the partition lines 8 and 9 , there is a transistor 1 indicated by a dotted line.
0, a diode 11, a resistor 12 and a capacitor 13 are integrated. Although these elements are shown sparsely in the drawing, they are actually densely integrated. Further, the wiring between the elements in the mat is substantially formed by the first electrode layer 14 shown by the dashed line,
Wiring between mats A and B, and between mats B and C, such as signal lines and feedback lines, are formed of the second electrode layer 15 shown by solid lines. These first and second electrode layers 14 and 15 are connected through contact regions indicated by x marks. FIG. 3B is a sectional view taken along line A-A' in FIG. 3A. An N-type epitaxial layer 17 is laminated on a P-type semiconductor substrate 16, and a P ⁺ type isolation region 18 is formed that reaches the semiconductor substrate 16 from the surface of this epitaxial layer 17, forming a large number of island regions. is formed. In this island region 19, an NPN transistor 10, a diode 11, a resistor 12, a capacitor 13, etc. are formed, and between the collector region 20 of the NPN transistor 10 and the semiconductor substrate 16, or between the island and the substrate 19. An N ⁺ type buried region 21 is formed therein. A silicon oxide film 22 is formed on the surface of the epitaxial layer 17 by, for example, a CVD method.
2, a first electrode layer 14 is formed. Further, an insulating film 23 such as PIX is formed to cover the first electrode layer 14, and a second electrode layer 15 is formed on this insulating film 23. Further, the power supply line 2 and the ground line 3 are provided on the isolation region 18, and the ground line 3 is in ohmic contact with the isolation region 18, thereby stabilizing the substrate potential. Next, the relationship between the electronic circuit block incorporated in this configuration and the mat will be described. Two electronic circuit blocks shown in FIG. 6, for example, a multiplex decoder block 24 for stereo demodulating a stereo signal, and an FM-IF block 25 for amplifying an intermediate frequency signal and then detecting it to obtain an audio signal are incorporated here. This multiplex decoder block 24
The number of elements is approximately 390, and FM-IF block 2
5 is approximately 430 pieces. Therefore, the former is divided into four parts with 100 elements or less as a guide, and each part is integrated into mats A to D, and the functions between each mat are determined by the second electrode layer 15 as described above. is provided to realize an electronic circuit block. Also, the latter
Divide into 5 parts with 100 elements or less as a guide, and
The mats from I to I are integrated, and the functions between the mats are determined by the second electrode layer 15 as described above.
is provided to realize an electronic circuit block. The Matsuto J also integrates optional circuits provided by the user, such as circuits for further improving the performance of this IC. On the other hand, the capacitor 7 incorporated in the FM-IF block 25 is integrated in the mat E. 1st
In the figure, 11 capacitors are formed, indicated by broken lines. The leakage current generated from the area where the capacitor of this mat E is formed is represented by a ground line 2 formed on both sides of the mat E, indicated by a dashed line.
6, 27 and the ground line 26, and a suction electrode 28 arranged in a comb-teeth shape. A partially enlarged view of this mat E is shown in FIG. 2A. The thickest electrodes 29 and 30 shown by the dashed line are
These are the ground lines 26 and 27 formed on both sides of the mat E in FIG. A MOS type capacitor 7 is formed between these two ground lines 29 and 30, and the hatched portion corresponds to the upper layer electrode 31 of the capacitor, which is formed in the first layer. Further, this upper layer electrode 31 is in ohmic contact with a second layer electrode 33 via a contact 32 indicated by an x on the right side, and this electrode 33 is extended to the right side and included in the present electronic circuit block. Connected to circuit elements. Further, the contacts 34 indicated by cross marks on the top and bottom or left and right sides of the upper layer electrode 31 are connected to the P-type diffusion region 35 formed in the lower layer of the upper layer electrode 31 shown in FIG. 2B and the electrode corresponding to the lower layer electrode of the capacitor. The contact portion with 36 is shown. Here, the electrode 36 is hereinafter referred to as a lower layer electrode. Similar to the upper layer electrode 31, this lower layer electrode layer 36 is connected to the second layer electrode 3 through a contact 37.
This second layer electrode 38 is extended to the right and connected to the circuit elements included in the electronic circuit block. Here, the contact 32 of the upper layer electrode 31 is provided near the left side of the ground line 30, and the second layer electrode 33 extends from there in the direction of the mat F.
are provided in a straight line to prevent intersections. Further, since the signal flow in the circuit is from the top to the bottom of the mat F, the capacitors are also provided substantially in the order of the circuit from top to bottom. Next, a cross-sectional view of this IC will be explained. A in Figure 2 A
-A' line and BB' line sectional views are illustrated in FIGS. 2B and 2C. First, there is a P-type semiconductor substrate 16, and an N-type epitaxial layer 17 is laminated on this semiconductor substrate 16. A P-type isolation region 18 reaches the semiconductor substrate 16 from the surface of this epitaxial layer 17.
Each capacitor 7 is formed in an island surrounded by this isolation region 18. There is an N ⁺ type buried layer 40 in the main region of this island 39, a P ⁺ type diffusion region 41 is formed in the upper layer of this buried layer 40, and a P type diffusion region 35 overlaps with this diffusion region 41. is formed. And on this epitaxial layer 17 is an insulating film.
There is a SiO ₂ film 22, and on this SiO ₂ film 22 there are an upper layer electrode 31, a lower layer electrode 36, and a ground line 2.
9, 30 and a suction electrode 28 are formed. The ground lines 29, 30 and the suction electrode 28 are in contact with each other over substantially the entire surface, as shown in the hatched contact area in FIG. 2A. Then, a second layer of insulating film, for example PIX 23, is coated, and electrodes 33 and 38 extending to the mat F are formed. Therefore, a junction capacitor formed around or below this MOS type capacitor 7, for example, a PN junction consisting of the island 39 and the isolation region 18, or the island 39 and the semiconductor substrate 16 or the buried layer 40, is formed with a reverse bias. The leakage current of the junction capacitor is transferred to the ground line 2 through the isolation region 18.
9, 30 or the suction electrode 28. Next, a second embodiment of the present invention will be described in detail with reference to FIG. In this embodiment, the upper surface of the semiconductor chip 42 is divided into two equal parts, a first region 44 and a second region 45 having substantially the same shape, using a dividing region 43 indicated by a two-dot chain line. It is distinctive in that it has a large number of pine trees. As a result, since the number of mats is large, the layout of the semiconductor chip 42 is easier than in the first embodiment. Specifically, 10 mats A to J are formed in the first area 44, and 10 mats K to T are formed in the second area 45.
Ten mats are formed, and the structure of each mat is the same as in the first embodiment, with substantially the same space capable of integrating about 100 elements, and each mat is separated by partition lines 4 . However, the capacitor included in this electronic circuit block is integrated in the mat E in order to intensively absorb leakage current to the substrate. Inside the 20 pine trees above, there is a structure shown in Figure 6.
A 1-chip IC for AM/FM stereo tuner is formed. FIG. 6 is a block diagram illustrating this electronic block circuit, which includes a total of five electronic circuits: FM front end block 46, FM-IF block 25, noise canceller block 47, multiplex decoder block 24, and AM tuner block 48. It is composed of blocks.
Although each circuit block is well known, its function will be briefly explained. First of all, the FM front end block 46 is a channel selection part for FM broadcasting, and is an FM front end block 46 that selects FM broadcasts.
It receives broadcast signals and converts them into 10.7MHz intermediate frequency signals, and the number of elements is approximately 250.
Since there are 1,000,000 pieces, they are accumulated in mats K to M. Next, the FM-IF block 25 amplifies this intermediate frequency signal and then detects it to obtain an audio signal, and since it has approximately 430 elements, it is integrated into mats E to I. Next, the noise canceller block 47 removes pulse noise such as ignition noise.
Since it has 270 elements, it is integrated into N to P mats. Furthermore, the multiplex decoder block 24 is a block for demodulating stereo signals, and has approximately 390 elements, so the Q.
It is accumulated in the pine of ~T. Finally, the AM tuner block 48 is the AM broadcast tuning section, which converts the AM broadcast signal received by the antenna to an intermediate frequency (450KHz), detects it, and obtains audio output, and consists of approximately 350 elements. Therefore, they are accumulated in mats A to D. Furthermore, in FIG. 7A, FIG. 7B, and FIG. 7C,
A diagram in which the AM tuner block 48, front end block 46, FM-IF block 25, and multiplex decoder block 24 are further divided into blocks is shown. First, the local oscillator circuit (OSC) 49 in the AM tuner block 48 in FIG. 5
2 and an intermediate frequency amplifier circuit (IF) 53 are substantially integrated in the mat C, and a detection circuit (DET) 54 is substantially integrated in the mat D, and as shown in _FIG . A~
V _CC is supplied to the first power line 59 of the mat D. Further, the ground pad GND1 is connected to second ground lines 61, 62, and 63 shown by three-dot chain lines on the one end divided region 43 via three octopus-like electrodes 60 provided between the mats A and N. and the respective second ground lines 61, 6
2 and 63 are connected to the first ground line 64 of the mats A to D. Next, the front end block 46, which is composed of the high frequency amplification circuit 65, mixing circuit 66, and local oscillation circuit 67 shown in FIG.
It dislikes interference from the FM-IF block 25, and the local oscillation circuit 67 within this block oscillates itself, generating unnecessary radiation. Therefore, especially
It is separated from the FM-IF block 25, and since the OSC block hates interference the most, it is connected to separate power supplies V _CC3 , V _CC4 ,
GND3 and GND4 are used. That is, the local oscillation circuit 67 is integrated on the mats K to M diagonally with the FM-IF block 25, and the local oscillation circuit 67 is integrated on the mat K, which is the cornermost _one , and the first
A power supply line 68 and a ground line 69 are provided. Further, the other L and M mats are provided with respective first power supply lines and ground lines 70 and 71 through V _CC3 and GND3. On the other hand, the FM-IF block 25, which is composed of an intermediate frequency amplification circuit 72, a detection circuit 73, an S meter 74, etc., is integrated on mats E to I, with the detection circuit 73 on mat I and the S meter 74, etc. on mat I. G
Furthermore, the limiter circuit, mute circuit, etc. in the intermediate frequency amplification circuit 72 are substantially integrated into the E, F, and G mats. Here, as explained in the first embodiment, the capacitor included in the limiter circuit is integrated in the mat E. This mat E is substantially the same as those in FIGS. 2A, 2B, and 2C, but the ground lines 75 and 76 formed around the mat E are different. The ground line 75 goes around the right periphery of the semiconductor chip 42,
Connected to GND2 and in contact with the isolation region below, it absorbs the leakage current around the capacitor of Mat E and the chip. In addition, the ground line 76 shares GND with a limiter circuit other than the capacitor included in the mat F, and the leakage current in the direction from the mat E to the mat F is transferred to the electrode 60.
It flows to GND1 via. Further, the electrode 77 on the left periphery of the chip 42 also sucks out leakage current. Here, a limiter circuit with an extremely high gain of 80 to 100 dB, a detection circuit 73 with a high signal level, the limiter circuit and an S meter 74 with a high signal level are shown.
generates oscillation due to feedback, and the characteristics of the detection circuit 73 and S meter 74 deteriorate due to mutual interference.
The first power line 78 of mats F and G is connected to a third power line 57 shown by a three-dot chain line, and the first power line 79 of mats H and I is connected to one third power line 57. 56. Matsuto J again
is one in which an optional circuit from the user is integrated, and this power supply line 80 is also connected to one third power supply line 55. Also, the first point indicated by the dashed line on the mats E to J
The ground line is connected in the same way as described above to second ground lines 61, 62, and 63 which extend from the ground pad GND1 in a cylindrical shape and are connected at one end. Subsequently, the DC amplifier circuit 81, decoder circuit 82, and ramp driver circuit 83 of the multiplex decoder block 24 in FIG. 86, a frequency dividing circuit 87, etc. are substantially integrated into the mats S and T. In addition, three electrodes 88, 89, and 90 extending in an octopus-like shape from the power pad V _CC2 pass between the AM tuner block 48 and the FM-IF block 25, and connect to the second power line on the divided area 43. One end is connected to 91, 92, and 93. Then, one wire goes to mats Q and R, one goes to mats S and T, and one wire becomes noise canceller block 47 N.
It extends to the pine of ~P. On the other hand, the ground pad GND2 is 3 in the shape of an octopus foot.
Connected to the third ground lines 94, 95, 96 of the book, and connected to the mats N to P, Q, and R as before.
It extends to the pine, S, and T pine. As described above, similarly to the first embodiment, the mats A to J and K to T are divided by the division lines 4 that are composed of the first power supply line and the first ground line. In addition, since the first power supply line and the first ground line are formed in a substantially comb-like shape, the space between the mats and the surrounding space can be effectively used, and the pads V _CC1 and GND2 around the chip 42 can be effectively used. can be connected over the shortest distance. Next, countermeasures against interference between the FM front end 46 and the FM-IF block 25 will be described. Previously, individual
This was a problem with the set board because each IC was used separately, but this time, because of the single chip, this interference became an even more problem, but it was resolved by the following measures. First, as mentioned above, since the FM front end block 46 handles signals with an extremely small level of several μV, it dislikes interference from other circuit blocks, especially the FM-IF block 25, and also avoids interference from the local oscillator configured within this block. The circuit 67 oscillates itself;
In order to generate unnecessary radiation, it is necessary to separate it from other blocks or provide a separate power supply. For these reasons, first, the FM front end block and FM-IF block were installed diagonally.
Also, the local oscillation circuit in this block is
They were accumulated and separated. Next, by widening the partition lines between the AM tuner block 48 and the FM-IF block 25, the FM front end block 46 and the noise canceller block 47, that is, between the mats D and E, and between the mats M and N, the FM The front end block 46 is kept away from other blocks, especially the FM-IF block 25.
Also, between the mat E of the mat D and the mat M and the mat N, a second area 45 is provided from the power supply pad V _CC2 .
Electrodes 88, 89, 90 extending from the ground pad GND1 to the first region 44 are provided, and second power lines 91, 92, 93 and a second power supply line are provided on the divided region 43. Ground lines 61, 62, and 63 are provided. Therefore, the FM front end block 46 is connected to the adjacent FM-IF.
block 25, AM tuner block 48 and noise canceller block 47,
In particular, the power lines 88, 89, and 90 prevent unnecessary radiation, and the ground line 60, which is in contact with the isolation region, can suck out the substrate current and prevent interference. Also, since the local oscillation circuit 67 in this FM front end block 25 dislikes interference, a power supply pad V _CC4 and a ground pad GND4 are provided separately.
The outer circuit is connected to the power supply pad V _CC3 and the ground pad.
It is supplied by GND3. Furthermore, the FM-IF block 25
It has a limiter circuit for removing the AM section, and this circuit is integrated with mats E and F.
As mentioned above, the capacitor in this limiter circuit causes leakage to the board, and this leakage current flows to the FM front end, causing malfunction. Therefore, the capacitors are grouped together in the mat E, and the first ground line 75 of the division line 4 on both sides of this line E,
I'm sucking it out intensively at 76. Furthermore, this first
The ground line 75 of the FM-IF block 2
5. It is extended to the outer periphery of the multiplex decoder block 24 and the noise canceler block 47 to absorb leakage current generated therefrom. Also, due to wiring reasons, the third power supply line 55, 5
6, 57, 58, the second power lines 91, 92, 93 and the second ground lines 61, 62, 63, etc. on the divided area 43 are connected to the second layer shown by the dotted line through the through holes shown by the black circles. There is crossover through the eye electrode layer. In particular, since the AM tuner block 48 does not operate simultaneously with other block circuits, the AM tuner block 48 and the FM-
The IF block 25 shares one pad V _CC1 , so there is a crossover. The same applies to the ground pad GND1. FIG. 5 specifically shows the configuration of the electrodes in order to explain that the FM front end block 46 and the FM-IF block 25 are separated from each other and that they cross over, as described above. The area marked with an x is the through hole shown with a black circle. Finally, let's take a look at an example of the features of the present invention. for example
If AM tuner block 48 is not required, A
The four mats that will become the multiplex decoder block 24 are integrated as they are on the mats ~D, and the remaining mats Q and R are replaced with mats I, for example.
and J are integrated. Therefore, since the mats for I, J, S, and T are redundant, by deleting these mats, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered. Also, when partially improving the FM-IF block 25,
For example, it is only necessary to take out and improve only the mat F, which is the improved part, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all mats can be used as is and only the number of mats needed for this block can be added, and mat J is used here as the mat for this option. In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy. (G) Effects of the Invention As is clear from the above explanation, firstly, the top surface of the semiconductor chip 1 is divided into a large number of mats of substantially the same size along the partition line 4 , and a plurality of electronic circuit blocks with different functions are divided into integer numbers. If each electronic circuit block is housed in a separate mat, each electronic circuit block can be designed in parallel.
Design period can be significantly shortened. Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed. In addition, circuit changes such as deletions, additions, and modifications can be designed for each electronic circuit block or each block, so changes only need to be made for each block or each mat.
No need to change the entire design. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, when changing the circuit afterwards, only the mat to be changed needs to be modified, and the other mats can be used as they are, resulting in extremely high reliability. Further, by integrating the capacitors included in the electronic circuit block in a specific mat among the mats forming the electronic circuit block, the design becomes easy. This is because the integration of capacitors into a particular mat is not constrained by the shapes of transistors, diodes, and resistors. Moreover, since the other mats do not include capacitors, there is no interaction with the capacitors, and the design of these mats becomes easier. Second, if the mat in which the capacitors are integrated is surrounded by a separation region, the leakage current of the junction capacitance flowing out from this mat portion can be sucked out by the separation region around the mat. Thirdly, by bringing this isolation region into contact with the ground line over almost the entire surface, all leakage current generated from the capacitor can be sucked out via the ground line without flowing to other mats. Fourth, by surrounding the capacitor with a separation area, leakage current can be sucked out for each capacitor, and by surrounding the area around the mat and the area around the capacitor,
Can suck out heavy weights. Fifth, by providing the ground line and the suction electrode in a comb-teeth shape, an integer number of capacitors can be installed between the comb-teeth, and the leakage current of the capacitor can be sucked out for each integer number of capacitors. I can do it. Further, as shown in FIG. 4, by forming the ground line in a comb-like shape with the left ground line, leakage current to the left can be intensively sucked out, and in particular, it is possible to prevent the leakage current from returning to the front end block. Sixth, since the upper and lower electrodes of a capacitor on a specific mat are basically formed on the first layer, the second layer can be used for wiring with other mats beyond the division line 4 . , it is possible to distinguish between the wiring of the capacitor and the wiring of other elements, making the design extremely easy. Seventh, upper layer electrode 31 and electrode 33 of the capacitor
By arranging the contact 32 with the mat on the right side of the mat, the second layer electrode 33 can be provided in a straight line on the mat on the right, and the layout of the second layer electrode on the mat on the right can be made extremely easy. Eighth, by providing the capacitors from above or below to below or above a specific mat in accordance with the circuit order of the electronic circuit block, the second layer electrodes 33 and 38 extending to the adjacent mat on the right can be Pattern layout can be facilitated. Ninth, by providing a specific mat with integrated capacitors on the mat at one end of the area constituting the electronic circuit block, the connecting electrode 3 with other mats can be connected.
3 and 38 can be extended in only one direction, facilitating pattern layout.

[Brief explanation of the drawing]

FIG. 1 is a top view showing a first embodiment of the semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a specific mat in which capacitors are integrated in FIG.
Figure 2B is a sectional view taken along the line A-A' in Figure 2, Figure 2C is a sectional view taken along the line B-B' in Figure 2A, and Figure 3A.
3B is a sectional view taken along line A-A' in FIG. 3A, and FIG. 4 is a top view showing a second embodiment of the semiconductor integrated circuit of the present invention. figure,
5 is a top view showing the actual electrode pattern of FIG. 4, FIG. 6 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention, FIG. 7A is a diagram illustrating an AM tuner block, and FIG. Figure 7B is a diagram explaining the FM front end block and FM-IF block, Figure 7C is a diagram explaining the multiplex decoder block, Figure 8 is a top view of a conventional semiconductor integrated circuit, and Figure 9 is a diagram explaining the multiplex decoder block. 9 is a sectional view between block b and block c in FIG. 8. FIG. 1, 42...Semiconductor chip, 2...Power line, 3
...Ground line, 4 ...Division line, 5...First supply line, 6...Second supply line, 7...Capacitor, 43...Divided area, 44...First area, 45
...Second region, 55, 56, 57, 58... Third power line, 61, 62, 63... Second ground line, 91, 92, 93... Second power line,
94, 95, 96...Third ground line.

Claims (1)

[Claims] 1. A semiconductor chip is divided into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. and an electronic circuit constituted by a plurality of electronic circuit blocks having different functions that are incorporated in an integral number of the mats of the semiconductor chips, and a capacitor included in the electronic circuit block is connected to the electronic circuit block. A semiconductor integrated circuit characterized by being integrated on a specific mat to be formed. 2. The semiconductor integrated circuit according to claim 1, wherein the mat in which the capacitors are integrated is surrounded by an isolation region formed within the semiconductor substrate. 3. The semiconductor integrated circuit according to claim 1, wherein the extraction electrode arranged in a comb-like shape with respect to the ground line is provided between vertically adjacent capacitors, and is in substantially entire surface contact with the isolation region provided between the capacitors. . 4 The wiring between the capacitor and the elements formed on the mat is substantially formed in the second layer, and the upper layer electrode of the first layer constituting the capacitor is in contact with the mat where semiconductor elements other than this capacitor are formed. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit substantially contacts the second layer wiring near the side. 5. The semiconductor integrated circuit according to claim 1, wherein the mat in which the capacitors are integrated is provided on the mat at one end of the area constituting the electronic circuit block.