JPH0648708B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a pattern layout that allows easy model deployment so as to meet the demands of custom ICs. It is a thing.
Furthermore, the present invention relates to a semiconductor integrated circuit that effectively utilizes a plurality of power supply pads.

(B) Conventional Technology In general, JP-A-59-84542 (H01L21)
/ 76), a semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate has a configuration shown in FIG.

FIG. 6 is a schematic plan view of the semiconductor chip (101).
Reference characters f to f denote circuit blocks. These circuit blocks have different frequencies and signal levels to be handled, and also have different functions.

This circuit block consists of a P ^- type semiconductor substrate (1
The circuit block is formed in the upper N-type region (103) and is partitioned by the high-concentration P ⁺ -type region (104) adjacent to the periphery of each circuit block. Here, the blocks b and c are shown.

The P ⁺ type region (104) for this partition has one end in contact with the P ⁻ type semiconductor substrate (102) and the other end ohmic-connected to the ground line (106) through the oxide film (105) on the semiconductor surface. To be done.

The ground line (106) is gathered from each block in the central portion of the integrated circuit and extends to one or more ground bonding pads GND at the left end.

Next, the power supply line (V _CC ) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to one or a plurality of power supply bonding pads, as shown in FIG.

(C) Problems to be Solved by the Invention Since the ground line and the power supply line extend to each block through the pad, the number of the ground line and the power supply line increases depending on the number of blocks, and the pad is It had the problem of getting bigger.

On the other hand, when the operations of the blocks a to f are distinguished,
It is divided into two types: blocks that always operate and blocks that do not work at the same time. The blocks that do not work at the same time are also provided with the ground line and the power supply line, respectively. For example, assuming that the block c and the block f do not work at the same time, if the block c is operating, the ground line (107) and the power supply line (108) are useless, and the block f
Is operating, the ground line (109) and power line (11
0) is wasted. Therefore, the inside of the chip is not effectively used.

Further, since the circuit blocks a to f have different functions, the number of elements existing in the block is different, and the block sizes are different from each other. Therefore, all of the circuit blocks can be efficiently used and the semiconductor chip (101 ), The size of each circuit block interacts with each other, which makes integration on the same chip difficult.

Further, if the circuit block a is deleted and another circuit block a'having improved characteristics is inserted or a circuit block g having another function is added to the circuit block configuration of FIG. It was necessary to recreate all the patterns because the size of was different.

Therefore, in recent years, when the life of the product has become extremely short, if the user wants to incorporate a unique circuit desired by a user into a certain chip, the user desires a short delivery time, but the circuit is short. It had a problem that it needed a very long delivery time to recreate the pattern.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a block that does not work at the same time uses one power supply and ground pad, and uses a power supply line and a ground line extending from this pad. Solved by sharing a part, and in the division line ( 5 ),
By dividing the upper surface of the semiconductor chip (1) into a large number of mats having substantially the same size and accommodating a plurality of electronic circuit blocks having different functions in one or more integer number of mats,
It solves the conventional problems.

(E) Operation According to the present invention, for example, a power supply pad and a ground pad are provided for each of the first and second electronic circuit blocks, and the power supply line and the ground line are extended from the respective pads. Since both pads and lines can be shared considering that they do not work at the same time, one power supply pad and ground pad are used, and at least part of the power supply line and ground line extending from this is shared effectively be utilized, also the semiconductor chip (1) by partition lines (5) top surface substantially divided into a number of mat of the same size, to accommodate different electronic circuit blocks of a plurality of functions into an integer number of mat This makes it possible to design for each electronic circuit block and divide the electronic circuit block with a fixed number of elements to design for each mat. Therefore, it is possible to divide each electronic circuit block for parallel design, and it is possible to significantly reduce the design period. Further, the circuit can be changed for each electronic circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

(F) Embodiment First, the first embodiment of the present invention will be described in detail with reference to FIG.

Using the divided area (2) indicated by the chain double-dashed line on the upper surface of the semiconductor chip (1), the first and second areas have substantially the same shape.
It is divided into (3) and (4), and the respective areas (3) and (4) are A to J,
It is divided into mats K to T. Between each mat of A to J and K to T, a division line in which a power line indicated by a solid line and a ground line indicated by a dashed line are adjacently extended in parallel.
It is divided by ( 5 ).

Regarding the arrangement of the power supply line and the ground line forming the division line ( 5 ), the power supply line indicated by the solid line is provided on the left side of each of the mats A to J and K to T, and the ground line indicated by the alternate long and short dash line is provided on the right side. Therefore, only the partition line ( 5 ) at both ends is formed on one of the power supply line and the ground line, and the intermediate partition line is configured by both. Each mat A ~
The power supply line and the ground line adjacent to J and K to T are integrated on each mat to supply power to the circuit block.

The power supply line and the ground line of each partition line ( 5 ) are the third power supply line (6) and the second power supply line (7) indicated by the three-dot chain line, and the third ground line (8) and the second power supply line. The ground lines (9) are connected to each other in a comb-like shape so as to face each other.
And second power lines (6), (7) and third and second
Ground lines (8) and (9) are led to the power supply pads V _CC1 and V _CC2 and the ground pads GND1 and GND2 among the pads provided around the pellet.

As will become apparent later, the mats K to M have
Separate from the pads, V _CC3, V _CC4, GND3, using GND4, and each power supply line, ground line, and the second and third power supply line (7), (6), second and The three ground lines (9) and (8) are basically realized by the first layer wiring of the two layer wirings.

The mats A to J divided by the division line ( 5 ) described above
K to T are formed in a shape of substantially the same size, and specifically, the width is set so that six NPN transistors are arranged, and the length is a fixed number of elements which is easy to design, for example, It is set so that about 100 elements can be laid out. The size of this mat can be arbitrarily selected according to the number of elements that can be easily designed by an electronic circuit block to be integrated into an IC.

The circuit elements integrated in the mat are composed of transistors, diodes, resistors and capacitors, and are separated by normal PN separation, and the wiring of each element is connected by the first electrode layer of the two-layer wiring, with the exception of The electrodes of the second layer are crossed over.

Next, with reference to FIGS. 2A and 2B, the circuit elements integrated in the mat and the partition line ( 5 ) will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of the mat B. The partition line ( 6 ) shown by the dashed line on the left is the partition line ( 5 ) provided between the mat A and the mat B, and the partition line ( 7 ) shown by the dashed line on the right is the mat B and the mat. It is a division line ( 5 ) provided between C. And this division line
A transistor (8), a diode (9), a resistor (10) and a capacitor (11) shown by a dotted line are integrated between ( 6 ) and ( 7 ). In the drawing these elements are rough,
In fact, they are highly integrated. The wiring between the elements in the mat is substantially formed of the first electrode layer (14) indicated by the alternate long and short dash line, and the wiring between the mats of the mat A and the mat B and the mat B and the mat C, for example, the signal Lines and feedback lines are formed by the second electrode layer (15) shown by solid lines. The first and second electrode layers (14) and (15) are connected to each other by the contact regions shown by "x".

2B is a sectional view taken along the line AA ′ in FIG. 2A. N type epitaxial layer on P type semiconductor substrate (14)
(15) are stacked, and the P ⁺ -type isolation region (16) reaching the semiconductor substrate (14) from the surface of the epitaxial layer (15)
Are formed, and a large number of island regions are formed.
In this island region (17) are NPN transistors
(8), diode (9), resistor (10), capacitor (11), etc. are made, and N is provided between the collector region (18) of the NPN transistor (8) and the semiconductor substrate (14). ^{A +} type buried region (19) is formed. The epitaxial layer (15)
A silicon oxide film (20) is formed on the surface of, for example, by the CVD method, and a first electrode layer (12) is formed on the silicon oxide film (20). An insulating film (21) such as PIX is formed so as to cover the first electrode layer (12), and a second electrode layer (13) is formed on the insulating film (21). Has been done. The power supply line (22) and the ground line (23) are provided on the isolation region (16), and the ground line (23) is in ohmic contact with the isolation region (16) to stabilize the substrate potential. I'm thinking.

More specifically, 10 mats A to J are formed in the first area (3), and 10 mats K to T are formed in the second area (4). Substantially the same space where about 100 elements can be integrated is provided, and each mat is divided by a division line ( 5 ).

AM / FM shown in Fig. 4 is contained in the 20 mats.
A one-chip IC for a stereo tuner is formed. Fourth
The figure is a block diagram for explaining this electronic block circuit. The FM front end block (24), FM-IF block (25), noise canceller block (26), multiplex decoder block (27), AM tuner block (28) ), A total of five electronic circuit blocks. Although each circuit block is well known, its function will be briefly described.

First, the FM front end block (24) is a channel selection part of FM broadcasting, receives an FM broadcasting signal of several tens of MHz to several hundreds of MHz, and frequency-converts it into an intermediate frequency signal of 10.7 MHz. Since it has about 250 pieces, K ~ M
Are collected on the mat. Next, the FM-IF block (2
In 5), the intermediate frequency signal is amplified and then detected to obtain an audio signal. Since it has about 430 elements, it is integrated in the mats E to I. The noise canceller block (26) is for removing pulse noise such as ignition noise. Since it has about 270 elements, it is integrated in the N to P mats. Further, the multiplex decoder block (27) is a block for stereo demodulating a stereo signal, and since it has about 390 elements, it is integrated in a mat of Q to T.
Lastly, the AM tuner block (28) is a channel selection part for AM broadcasting, and converts the AM broadcasting signal received by the antenna to an intermediate frequency (450KHz) and detects it to obtain an audio output. About 350 Since it has the element of
Collected on D mat.

Further, in FIGS. 5A, 5B and 5C, AM respectively.
Tuner block (28), front end block (24)
And a block diagram of the FM-IF block (25) and the multiplex decoder block (27).

First, the local oscillator circuit (OSC) (29) in the AM tuner block (28) of FIG.
X) (30) on mat B, automatic gain control circuit (AGC) (3
1), the high frequency amplifier circuit (RF) (32) and the intermediate frequency amplifier circuit (IF) (33) are on the mat C, and the detection circuit (DET) (34)
_Are substantially integrated on the mat D, and the third power supply lines (35), (36), (37) shown by the three-dot chain line in FIG. ), (38) through A to D
Supplies V _cc to the first power supply line (39) of the mat. Further, the ground pad GND1 has a second ground line (4) indicated by a three-dot chain line on one end divided region (2) through three octopus-shaped electrodes (40) provided between the mat M and the mat N.
1), (42), (43), and the respective second ground lines (41), (42), (43) are connected to the first ground line (44) of the mats A to D. ing.

Next, since the front end block (24) composed of the high frequency amplification circuit (45), the mixing circuit (46) and the local oscillation circuit (47) of FIG. 5B handles a signal of an extremely small level of several μV, I hate interference from other circuit blocks, especially FM-IF block (25), and the local oscillator circuit in this block
(47) oscillates itself, generating unnecessary radiation. Therefore is particularly separated from the FM-IF block (25), another power supply V _cc3 for OSC block dislike the most interference, V _cc4, GND3, GND
4 is used.

That is, K ~ which is diagonal to the FM-IF block (25)
Integrated on M mat, integrated local oscillator circuit (47) in the top corner mat K, another pad V _CC4 on both sides
A first power supply line (48) and a ground line (49) are provided through and GND4. The other L and M mats are provided with respective first power supply lines and ground lines (50) and (51) through V _CC3 and GND ₃ .

On the other hand, the FM-IF block (25) including the intermediate frequency amplification circuit (52), the detection circuit (53), the S meter (54), etc.
~ Integrated on the mat I, the detection circuit (53) on the mat I,
The S meter (54) etc. is on the mat G, and further the intermediate frequency amplifier circuit
The limiter circuit and mute circuit in (52) are E, F
And G are practically integrated on the mat.

Here, the limiter circuit having a very high gain of 80 to 100 dB and the detection circuit (53) having a large signal level, and the limiter circuit and the S meter (54) having a large signal level generate oscillation due to feedback, and the detection circuit (53) and S Since the characteristic of the meter (54) deteriorates due to mutual interference, the first power supply line (55) of the mats E, F, G is the third power supply line indicated by a three-dot chain line.
At (37), the first power supply line (56) of the mats H and I is connected to one third power supply line (36). The mat J has an optional circuit from a user integrated therein, and the first power supply line (57) is also connected to one third power supply line (35).

The first ground line (58) shown by the alternate long and short dash line on the mats E to J extends from the ground pad GND1 in a octopus-like shape and is connected at one end to the second ground lines (41), (4).
2) and (43) are connected in the same manner as above.

Subsequently, the DC amplifier circuit (59), the decoder circuit (60) and the lamp driver circuit (61) of the multiplex decoder block (27) of FIG. 5C are arranged on the mat Q and the mat R, and the phase comparison circuit (62). , The low pass filter circuit (63), the voltage controlled oscillator (64), the frequency dividing circuit (65), etc. are substantially integrated in the mat S and the mat T. Further, the three electrodes (66), (67), (68) extended from the power supply pad V _{CC2 in the} shape of octopus pass between the AM tuner block (28) and the FM-IF block (25), Second power supply lines (69), (7) on the divided area (2)
One end is connected to 0) and (71). And one is mat Q and R
One extends to the mats S and T, and one extends to the mats N to P which are the noise canceller block (26).

On the other hand, the ground pad GND2 is connected to the three third ground lines (72), (73), (74) in an octopus-like shape, and the mats of N to P, the mats of Q and R, Extends to S and T mats.

In addition, pad V is used to prevent mutual interference between blocks.
_CC1 , V _CC2 and pads GND1, GND2 are used separately, V _CC1 , V
_CC2 is connected to lead (75), pads GND1 and GND2 are leads
It is connected to (76). This prevents the variation of the pad V _CC1 from being directly transmitted to the pad V _CC2 , and lowers the impedance of the metal thin wire by using two metal thin wires. Therefore, the pulse noise or the like that has entered the leads is not amplified through the impedance, and the voltage fluctuation can be prevented.

As described above, A to J, K are divided by the partition line ( 5 ) composed of the first power supply line and the first ground line.
~ T mats are sectioned. Further, since the first power supply line and the first ground line are formed substantially in a comb shape, the space between the mats and the peripheral space can be effectively utilized, and the pad V _CC1 around the chip (1) can be effectively used. , GND1, GND
2 can be connected at the shortest distance.

Next, FM front end (24) and FM-IF block (25)
This section describes measures against interference. In the past, it was a problem on the set board because each individual IC was used, but this time it was 1
This interference caused a problem due to the chip formation, but it is solved by the following measures.

First, as mentioned above, the FM front end block (24)
Handles a signal of a very small level such as several μV, so it dislikes interference from other circuit blocks, especially the FM-IF block (25), and the local oscillator circuit constructed in this block.
Since (47) oscillates itself and generates unnecessary radiation, it is necessary to separate it from other blocks or provide another power supply.

For these reasons, first, the FM front end block and the FM-IF block are provided on a diagonal line, and the local oscillation circuits in this block are integrated on the mat K and separated from each other. Next, between the AM tuner block (28) and the FM-IF block (25), between the FM front end block (24) and the noise canceller block (26), that is, the division line of mat D and mat E, mat M and mat N. The wider width keeps the FM front end block (24) away from other blocks, especially the FM-IF block (25). Further, between the mat D and the mat E and between the mat M and the mat N,
An electrode (6) extending from the power supply pad V _CC2 to the second region (4)
6), (67), (68) and the first area from the ground pad GND1
An electrode (40) extending to (3) is provided, and second power supply lines (69), (70), (71) and a second ground line (41) are further provided on the divided region (2). (42) and (43) are provided. Therefore, the FM front-end block (24) is separated from the adjacent FM-IF block (25), AM tuner block (28) and noise canceller block (26), especially the power line (6
6), (67), (68) prevent unnecessary radiation and ground line (4
Since at least one of (0) is in contact with the isolation region (16), the substrate current can be drawn out and interference is prevented.

The local oscillator circuit (47) in the FM front end block (24), since hate interference, provided separately the power pads V _CC4 and ground pad GND4, circuit outside the power supply pad V _CC3
And ground pad GND3.

Further, the FM-IF block (25) has a limiter circuit for removing the AM part of the FM signal, and this circuit is integrated by the mat E and the mat F. The capacitor in the limiter circuit leaks to the substrate, and this leak current flows to the FM front end, causing a malfunction. Therefore, the capacitors are put together on the mat E, and are sucked out intensively by the first ground line (77) of the partition line ( 5 ) on the left side of the mat E. Furthermore, this first ground line (77)
Is an FM-IF block (25), a multiplex decoder block (27) and a noise canceller block (2
It extends to the outer periphery of the region where 6) is formed, and also leaks the leak current generated from them. Similarly chips (1)
A ground line (78) is also provided around the left half of the.
Also, because of wiring, the third power line (35), (36), (37),
(38), the second power line (69), (70) on the divided area (2),
(71) and the second ground lines (41), (42), (43), etc. are indicated by dotted lines 2 through the through holes indicated by black circles.
Crossover occurs through the electrode layer (79) of the first layer. Especially since the AM tuner block (28) does not work at the same time as the external block circuit, the AM tuner block (28) and F
The M-IF block (25) shares one pad V _CC1 and therefore crosses over. The same applies to the ground pad GND1.

The above configuration is shown in FIG. The one indicated by the chain line is 1
The electrode formed in the second layer, which is shown by the solid line, is the second layer electrode. The area indicated by X is a through hole. Since the two blocks do not work at the same time, they are shared, and in terms of pattern, since the electrodes from the pads V _CC1 and GND1 to the through holes are shared, the area occupied by the electrodes can be reduced.

Finally, an example of the characteristic points of the present invention will be described. For example, if the AM tuner block (28) is not needed, it becomes a multiplex decoder block (27) in the mats A to D. 4
One mat is integrated as it is, and mats I and J, for example, are integrated on the remaining mat Q and mat R. Therefore I,
Since the mats of J, S, and T are redundant, if the mat is deleted, the mats can be neatly housed in a rectangular chip. Here, the wiring of the first layer in the mat is used as it is, and only the wiring between the mats and the wiring between the blocks may be considered.

Further, when the FM-IF block (25) is partially improved, for example, only the mat F which is an improved part may be taken out and improved, and the other mats E, G, H can be used as they are. When adding another block which is an option for the user, all the mats are used as they are, and the required number of mats may be added to this block. Here, the mat J is used as this option mat.

That is, since mats having the same size are formed in a matrix, replacement, addition, and deletion are very easy.

(G) Effects of the Invention As is apparent from the above description, firstly, the power supplies of a plurality of electronic circuit blocks that do not work at the same time are composed of a set of V _CC1 and GND1.
Since the pad is shared, a part of the electrode extending from the pad to each mat can be shared. Therefore, the electrode occupancy of the chip (1) can be reduced, which can contribute to the downsizing of the chip.

Secondly, if the power and ground pads of the AM tuner block (28) and the FM-IF block (25) are set to V _CC1 and GND1, the electrode occupancy rate in the IC of the AM / FM stereo tuner circuit will be the same as above. Can be reduced and the chip can be miniaturized.

_Thirdly , when the pads V _CC1 and V _CC1 and the lead (75) are connected to each other by a thin metal wire, the impedance of the thin metal wire is lowered because it is connected in parallel. Therefore, the pulse noise or the like that has entered the lead (75) enters through the thin metal wire having a low impedance, and this noise is not greatly amplified. Therefore, voltage fluctuation can be prevented. Similarly, the pads GND1 and GND2 and the lead (76) can also prevent voltage fluctuations.

Fourth, AM tuner block from power supply pad V _CC1
The plurality of power supply lines (35), (36), (37), (38) extending to the mats A to D on which (28) is formed are formed on the second layer at one end. This is because the power lines (66), (67) and (68) are crossed over. As a result, the AM tuner block 28 and the FM-IF block 25 can be commonly used. Also, the ground lines (41), (42), and (43) extending from the ground pad GND1 can also be commonly used.

Fifthly, if the upper surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size by the division line ( 5 ) and a plurality of electronic circuit blocks having different functions are housed in an integer number of mats, each electronic circuit block is It is possible to design in parallel with, and the design period can be shortened significantly. Further, since the electronic circuit block is divided into a certain number of elements and the design for each mat can be performed, the parallel design for each mat can also be performed. Further, since circuit changes such as deletion, addition and correction can be designed for each electronic circuit block or each block, only the change for each block or each mat is sufficient.
There is no need to change the design of the entire C. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, other mats can be used as they are, and the reliability can be improved very much by modifying only the mat to be changed when the circuit is changed thereafter. Moreover, among the plurality of electronic circuit blocks, the power source of the electronic circuit block that does not work simultaneously is shared by one power source and the ground pad, so that a part of the electrodes extending from the pad to each mat can be shared. Therefore, the electrode occupation rate of the chip can be reduced.

Sixth, in the IC of the AM / FM stereo tuner circuit that adopts the mat division and can significantly reduce the design period,
AM tuner block (28) and FM-IF block (25)
Since the power source and the ground pad of 1 are shared by one set of V _CC1 and GND 1, the area occupied by the electrodes can be reduced.

Seventh, in the IC adopting the mat division, the two power supply pads V _CC1 and V _CC2 are connected at one end of each metal thin wire, and the other end is connected to one lead, thereby connecting the metal thin wires in parallel. be able to. Therefore, the pulse noise or the like that has entered the lead is not significantly amplified due to its low impedance, and fluctuations in the power supply voltage can be prevented. The same applies to the ground pad.

Eighth, in the IC adopting the mat division, a plurality of power supply lines extending from the power supply pads to the electronic circuit blocks (mats A to D) are formed in the second layer at one end. This is the other electronic circuit block (mat N to P, mat Q to
This is to cross over the power supply line extending to T). Therefore, the electronic circuit blocks (mats A to D) and the electronic circuit blocks (mats E to I and mat J) can be commonly used. The same applies to the ground line side.

[Brief description of drawings]

FIG. 1 is a top view showing an embodiment of a semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a mat area of the semiconductor integrated circuit of the present invention, and FIG. 2B is A-A in FIG. 2A. FIG. 3 is a top view showing an electrode pattern of the semiconductor integrated circuit of the present invention, FIG. 4 is an electronic circuit block diagram incorporated in the semiconductor integrated circuit of the present invention, and FIG. 5A is an AM tuner block. 5B is a diagram for explaining the FM front end block and the FM-IF block, FIG.
FIG. C is a view for explaining a multiplex decoder block, FIG. 6 is a top view of a conventional semiconductor integrated circuit, and FIG. 7 is a sectional view between a block b and a block c in FIG. (1) …… Semiconductor chip, (2) …… Divided area, (3) …… First
Area, (4) …… second area, ( 5 ) …… compartment line, (3
5), (36), (37), (38) …… Third power supply line, (41), (4
2), (43) …… Second ground line, (69), (70), (71)
...... Second power line, (72), (73), (74) …… Third ground line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04B 1/08 E 7240-5K 7377-4M H01L 21/82 M

Claims (4)

[Claims] 1. An area in which a linear electronic circuit including a plurality of linear electronic circuit blocks is formed on one semiconductor chip, a semiconductor element forming the linear electronic circuit block formed in this area, and the semiconductor chip. A linear semiconductor integrated circuit having at least a plurality of power supply pads and a plurality of ground pads provided around the first electronic circuit block, wherein the electronic circuit includes first and second electronic circuit blocks that do not simultaneously operate; And a third electronic circuit block that operates whenever one electronic circuit block operates, wherein the first and second electronic circuit blocks share the first power supply pad and the first GND pad. Power is supplied, and the third electronic circuit block is configured to supply power using a second power supply pad and a second ground pad. Linear semiconductor integrated circuit. 2. A semiconductor element disposition region (mat) formed in the semiconductor layer, which is positioned in the semiconductor layer of the semiconductor chip and has a plurality of shapes of substantially the same size, and a surrounding area of the semiconductor chip. The arrangement area (mat) is a semiconductor element of a linear electronic circuit including a plurality of electronic circuit blocks each having a plurality of power supply pads and a plurality of ground pads and having circuit sizes substantially different from each other. A linear semiconductor integrated circuit formed in the electronic circuit block, wherein the electronic circuit blocks classified according to the functions include first and second electronic circuit blocks that do not operate simultaneously, and
A third electronic circuit block that operates whenever one electronic circuit block operates, and all semiconductor elements of the electronic circuit block include all semiconductor elements of the electronic circuit block in units of the arrangement area (mat). Substantially formed in a plurality of arrangement regions (mats) obtained by dividing the number of elements, the first and second electronic circuit blocks share the first power supply pad and the first GND pad. To supply power, and the third electronic circuit block supplies power using a second power pad and a second ground pad. 3. The electronic circuit is an AM / FM stereo tuner circuit, the first and second electronic circuit blocks are an AM tuner block and an FM-IF block, and the third electronic circuit block is 3. The semiconductor integrated circuit according to claim 1, which is a multiplex decoder block. 4. The first and second power supply pads are arranged adjacent to each other, and the first and second power supply pads are connected to a lead for one power supply with a thin metal wire, and the first and second power supply pads are connected. The semiconductor integrated circuit according to claim 1, 2, or 3, wherein the ground pad is connected to one ground lead with a thin metal wire.