JPH0744414B2 - Automatic gain adjustment circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an automatic gain adjustment (hereinafter referred to as AGC) circuit,
Particularly, the present invention relates to an average value AGC circuit using a field effect transistor for keeping the output of a general-purpose amplifier constant against cable loss and fluctuation in medium-range broadband transmission of about several kilometers.

2. Description of the Related Art A conventional average value AGC circuit is configured to maintain a constant output of the amplifier by connecting a field effect transistor to the output of the general-purpose amplifier and controlling the resistance value of the transistor according to an input signal. There is.

The principle of this automatic gain adjustment circuit will be briefly described with reference to FIGS. 3 and 4. When the waveform as shown in FIG. 4 (A) is input to the general-purpose amplifier 1 of FIG. 3, the general-purpose amplifier output voltage becomes as shown in (B). In FIG. 4 (B), the base voltage V _B is the general-purpose amplifier 1 when there is no input to the general-purpose amplifier 1.
Is an output voltage, that is, a bias voltage value, and an average output voltage Vo is an average voltage (DC voltage) when a signal is input.

Here, when the input signal increases as shown in FIG. 4 (C),
The output voltage of the amplifier 1 changes from FIG. 4 (B) to FIG. 2 (D). Therefore, at this time, the variable resistor 2 (resistance value of the field effect transistor) is operated so that the average voltage Vo 'shown in FIG. 4 (D) approaches (compresses) the average voltage Vo' of FIG. 4 (B). As a result, the output voltage can be kept constant.

That is, when the input signal increases, the value of the variable resistor 2 is reduced to keep the DC voltage constant, so that the AC signal can be kept constant. On the contrary, when the input signal decreases, the output voltage (both DC and AC signals) can be kept constant by increasing the value of the variable resistor 2. The AC voltage (signal voltage) can also be kept constant by keeping the DC voltage (average voltage) constant.

Even if the operating point is set to the best point, the conventional average value AGC circuit is compressed in the positive direction (or the negative direction) of the input level, but is not so compressed in the reverse direction. Of the transistor shown in FIG.
Even if the best point on V _SG vs. R _DS characteristic curve 3 is set, if the source-gate voltage V _SG increases by 1 V, the drain
The resistance between sources R _DS is tens of ohms and the resistance is small, while when V _SG is lowered by 1V, the resistance of R _DS is tens of kilohms and the resistance is large and the automatic gain adjustment operation range is narrow and the compression is performed only partially. It will be. Therefore, there is a drawback in that the setting of automatic gain adjustment depends on the input signal level and is not uniformly compressed and expanded with respect to the signal level. This is due to variations in the field effect transistor element and uneven R _DS in the narrow operation range of the field effect transistor.

OBJECT OF THE INVENTION It is an object of the present invention to provide an average value automatic gain adjustment circuit using a field effect transistor in which the automatic gain range can be widened and the compression range can be easily changed by increasing the compression rate. That is.

The automatic gain adjustment circuit according to the present invention is an average value automatic gain adjustment circuit that keeps the amplified output constant according to the input signal, and the conductive channels of the two are serially connected to the signal line of the amplified output. A pair of field effect transistors of opposite conductivity type connected and inserted; and a control voltage generating means for extracting a direct current component from the amplification input to generate a pair of control voltages according to the direct current component, One pair of control voltage
The gate voltage corresponding to the pair of field effect transistors is used.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which an amplification input is amplified by a general-purpose amplifier 1. The transistor 4 provided at the output of the amplifier 1 is for current / voltage conversion, and in the output line of the transistor 4, a pair of FETs (field effect transistors) 5 and 6 of opposite conductivity type are mutually conductive. The channels are inserted in series.

On the other hand, the input of the amplifier 9 is connected to the input of the general-purpose amplifier 1 by the resistor 7,
It is connected through a capacitor 8 so that only the DC component is extracted from the bias of the amplifier 1 and a reference potential is given to the two FETs 5 and 6. Here, the reference potential A'is set by the emitter of the transistor 4 at the output of the general-purpose amplifier 1, and the emitter is connected to the inverting input side of the amplifier 12. The variable resistor 11 is connected to the emitter of the transistor 4 at the output of the amplifier 9, and the intermediate terminal of the variable resistor 11 is connected to the non-inverting input side of the amplifier 12. By adjusting the resistance value of the variable resistor 11,
The potential on the output side of the variable resistor 11 can be changed, and this becomes the set potential for the amplifier 12. In addition, the amplifier
The inverting input side of the amplifier 13 is connected to the output of 12.

The amplifier 12 outputs an amplified voltage of (−reference potential A ′ + set potential), and the output is input to the gate of the FET 5. On the other hand, the amplifier 13 outputs a voltage of (reference potential A'-set potential), and the output is input to the gate of the FET 6. It is possible to change the operating range by moving the set potential with the variable resistor 11.

If the input signal of the general-purpose amplifier 1 decreases, the amplifier 9
Since the reference potential of is decreased and the drain-source resistance R _DS of the FETs 5 and 6 is increased, the DC potential of the output OUT is kept constant and the AC signal is kept constant.

On the other hand, when the input signal increases, the reference potential of the amplifier 9 rises, which in turn decreases the drain-source resistance R _DS of the FETs 5 and 6, so that the DC potential of the output OUT is kept constant and the AC signal remains unchanged. Is kept constant.

This will be explained in more detail with reference to FIGS. 1 and 2. 2. FIG. 2 is a graph showing the relationship between the source-gate voltage V _GS and the drain-source resistance R _DS of the FETs 5 and 6 in the automatic gain adjustment circuit of the present invention.

First, the phase of each part will be described before the description of the operation. In FIG. 1, when the input potential of IN increases from the standard value, the output potential of the amplifier 9 operates in the increasing direction and is applied to the non-inverting input terminal of the amplifier 12 and the inverting input terminal of the amplifier 12. The output of the amplifier 1 is guided to. Amplifier
The output of 12 decreases without being inverted because the potential fluctuation from the output of the amplifier 1 is small. At this time, the output potential of the amplifier 13 increases because the output of the amplifier 12 is applied to the inverting input terminal. In FIG. 2, the characteristic indicated by the solid line will be referred to for explanation below, but the actual characteristic becomes a curve as indicated by the dotted line.

If the input potential of IN increases above the standard value, the amplifier 12
Output potential of FET5 operates in the decreasing direction, and V _GS of FET5 is m → m '
Direction, increasing R _DS of FET5 (FET5 changes from Q → P
Toward), and increase the potential between the source and drain.
At this time, the output potential of the amplifier 13 increases and the V _{GS of} the FET 6 also increases, so that it moves from n to n ″ and the R _DS of the FET 6 decreases. As a result, the increase rate of the R _DS of the FET 5 is Since the rate of decrease of R _DS of is exceeded, the potential of OUT can be made almost constant.

On the other hand, when the input potential of IN decreases from the point of increasing from the standard value toward the standard value, the output potential of the amplifier 12 operates in the increasing direction, and V _GS of the FET5 moves in the m '→ m direction. Then, the R _DS of the FET5 is decreased (the FET5 goes from P → Q) and the potential between the source and the drain is decreased. At this time, the output potential of the amplifier 13 decreases and the V _{GS of} the FET 6 also decreases, so that it moves from n ″ to n, and the R _DS of the FET 6 increases. As a result, the R _DS decrease rate of the FET 5 decreases to the R _{DS of the} FET 6. Since it exceeds the rate of increase, the OUT potential can be made almost constant.

Next, a case where the input potential of IN decreases below the standard value will be described. The output potential of amplifier 12 operates in the increasing direction, and V of FET5
_GS moves in the direction of m → m ″ and decreases the R _DS of FET5 (F
ET5 decreases the potential between the source and drain, going from Q to P). At this time, the output potential of the amplifier 13 decreases, and the V _{GS of} the FET 6 also decreases, so that it moves from n → n ′ to the FET
R _DS of 6 increases. The rate of change of the R _DS is, R _DS reduction rate of FET5 is
Since it is smaller than the increase rate of R _{DS of} FET6, V _GS of FET6 will increase. However, in practice, because of the operation zone of the potential of FET5,6 and point A 'low potential, a decrease in growth rate and IN of FET6 of R _DS than the decrease rate of the R _DS of FET 5, OUT
Since the potential of the output of the amplifier 1 decreases less when the output of the amplifier 1 decreases, the gain is corrected.

When the input potential of IN increases from the point where it decreases from the standard value toward the standard value, the output potential of the amplifier 12 operates in the decreasing direction, V _GS of FET5 moves in the direction of m ″ → m, and FET5 R _DS
(FET5 goes from R to Q) to increase the potential between the source and drain. At this time, the output potential of the amplifier 13 increases and the V _{GS of} the FET 6 also increases, so Q '→ P'
, The R _DS of FET6 decreases. The increase rate of R _DS of FET5 is
Since FET6 smaller than the decrease rate of the R _DS, but decreases V _GS of FET6, in fact, the potential of FET5,6 and point A ', for operation range at low potential, an increase in R _DS of FET5 R _DS towards the rate is FET6
Since it is larger than the decrease rate of, the gain is corrected.

Fig. 5 shows the case where one FET is used (solid line 3), as in the present invention.
Source-gate voltage V _SG − for two FETs (dotted line 14)
6 is a graph showing a drain-source resistance R _DS characteristic. As is clear from the figure, connecting two FETs expands the control range of the FET whose compression ratio is increased, that is, the AGC range. Further, for example, when the point D is the operating point, the compression is almost the same in either the increasing or decreasing direction of the input level, and the variable resistor 11 can change the compression range.

EFFECTS OF THE INVENTION According to the present invention, since two field effect transistors are connected in cascade to the general-purpose amplified output as variable elements, the compression rate can be increased, and at the same time the compression rate varies depending on the direction of the input level. The conventional defects can be eliminated. Also, since the AGC operating range can be easily changed by the variable resistor 11, variations in the field effect transistor element and R
_This has the effect of absorbing the unevenness of _SD .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an average value AGC circuit according to the present invention, and FIG. 2 is a FET5 in an automatic gain adjustment circuit of the present invention.
And 6 are graphs showing the relationship between the source-gate voltage V _GS and the drain-source resistance R _DS , FIG. 3 is a circuit diagram for explaining the principle of the basic average value AGC circuit, and FIG. 4 is FIG. 3 is a waveform diagram showing the input / output of the average value AGC circuit of FIG. 3, and FIG. 5 is a graph showing the source-gate voltage V _SG -drain-source resistance R _DS characteristics of the FET of the conventional example and the present invention. Further, FIG. 6 is an operation diagram conceptually showing this characteristic in order to facilitate the explanation of FIG. Explanation of main part code 1 …… General purpose amplifier 5,6 …… FET 9,12,13 …… Amplifier

Claims (1)

[Claims] 1. A first amplifier that receives an input signal from an input side, amplifies the input signal and outputs an amplified signal, and a base connection to the output of the amplifier, which converts the amplified signal into a voltage signal. A first transistor that outputs a first reference voltage; a second amplifier that is connected to the input side of the first amplifier and that outputs only a DC component from the bias of the first amplifier; A second transistor whose base is connected to the output side of the second amplifier and which is connected to a second transistor for converting the DC component into a voltage and an emitter of the second transistor, and which changes the emitter potential to set a set potential. A resistor; a third amplifier connected to the variable resistor on an input side for amplifying the set potential to output a first amplified voltage; and an output side of the third amplifier having an input side connected to the third amplifier. 1 amplification power Amplifies the fourth outputting a second amplified voltage
And the drain of the first transistor is connected to the emitter of the first transistor, and the output side of the third amplifier is connected to the gate of P.
A channel type field effect transistor, and a source of the P channel type field effect transistor,
The source is connected, the output side of the fourth amplifier is connected to the gate, and a DC signal is output from the drain to the outside.
An automatic gain adjustment circuit comprising: a channel type field effect transistor.