JPH077821B2 - Complementary MOS integrated circuit - Google Patents
Complementary MOS integrated circuitInfo
- Publication number
- JPH077821B2 JPH077821B2 JP61173062A JP17306286A JPH077821B2 JP H077821 B2 JPH077821 B2 JP H077821B2 JP 61173062 A JP61173062 A JP 61173062A JP 17306286 A JP17306286 A JP 17306286A JP H077821 B2 JPH077821 B2 JP H077821B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- effect transistor
- conductivity type
- field effect
- transistor formed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000000295 complement effect Effects 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000007257 malfunction Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型MOS集積回路（以下、CMOS・ICと略す
る）に関する。The present invention relates to a complementary MOS integrated circuit (hereinafter abbreviated as CMOS / IC).
従来、この種のCMOS・ICは、低消費電力で動作すること
が特徴の一つであり、電卓，時計，液晶テレビ等の小容
量バッテリを電源とするものに多く利用されている。そ
の中にあってブザー，ランプなどの重負荷を駆動する場
合、バッテリの内部抵抗の電圧降下によりバッテリ電圧
が変動し、CMOS・ICの誤動作を誘発することがしばしば
あった。また、バッテリ駆動の利点より持ち運び簡単な
ハンディ型として広く利用されているため、人体などに
よる静電気誘導雑音の影響を受ける機会も多くなてお
り、これが入力端子からCMOS・IC内部に入力され、保護
回路を介して放電電流が流れ、CMOS・IC内部の入力回路
の電源を変動させ、誤動作させるケースもしばしばあっ
た。Conventionally, this type of CMOS IC has one of the characteristics that it operates with low power consumption, and it is widely used for small-capacity batteries such as calculators, watches, and liquid crystal televisions. When driving a heavy load such as a buzzer or a lamp, the battery voltage fluctuates due to the voltage drop of the internal resistance of the battery, often causing malfunction of the CMOS / IC. In addition, since it is widely used as a handy type that is easy to carry and has the advantage of being battery-powered, there are many opportunities to be affected by static electricity-induced noise due to the human body, etc. In many cases, a discharge current flowed through the circuit, which fluctuated the power supply of the input circuit inside the CMOS / IC and caused a malfunction.
上述した従来のCMOS・ICは、出力回路に供給する電源
線、制御回路に供給する電源線など多くの電源線で各素
子に電源が供給されており、前述の外部からの雑音入力
や電源変動があった時に入力回路を構成する素子と制御
回路を構成する素子との間は必ずしも時間的に同時変化
することはなく、この時間差と変動電圧差より論理信号
として認識され、制御回路を誤動作せしめるという欠点
がある。In the conventional CMOS / IC described above, power is supplied to each element by many power supply lines, such as the power supply line supplied to the output circuit and the power supply line supplied to the control circuit. When there is, the elements forming the input circuit and the elements forming the control circuit do not always change simultaneously in time, and are recognized as a logic signal from this time difference and the fluctuation voltage difference, which causes the control circuit to malfunction. There is a drawback that.
本発明によるCMOS・ICは、第１の論理電位が供給される
一導電型のサブストレートと、このサブストレートに互
いに離間に設けられ第２の論理電位がそれぞれ供給され
る他の導電型の第１および第２のウェルと、前記サブス
トレートの一部に形成された電界効果型トランジスタお
よび前記第１のウェルに形成された電界効果型トランジ
スタで構成された入力回路と、前記サブストレートの他
の一部に形成された電界効果型トランジスタおよび前記
第２のウェルに形成された電界効果型トランジスタで構
成された制御回路と、前記入力回路と前記制御回路との
間に設けられ前記サブストレートのさらに他の一部に形
成された抵抗およびコンデンサで構成されたローパスフ
ィルタとを有してなる。The CMOS IC according to the present invention includes a substrate of one conductivity type to which a first logic potential is supplied and a second substrate of another conductivity type which is provided on the substrate and is spaced apart from each other and to which a second logic potential is supplied. An input circuit including first and second wells, a field effect transistor formed in a part of the substrate and a field effect transistor formed in the first well, and another of the substrate A control circuit including a field-effect transistor formed in a part and a field-effect transistor formed in the second well, and a substrate further provided between the input circuit and the control circuit. It has a low-pass filter composed of a resistor and a capacitor formed in another part.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のCMOS・ICの一実施例の回路配置図であ
る。第１の論理電位１に接続された一導電型サブストレ
ート２と第２の論理電位３に接続された他の導電型ウェ
ル５の上に構成される入力回路ブロック７は一導電型サ
ブストレート２上に構成され抵抗とコンデンサでなるロ
ーパスフィルタ８に接続され、ローパスフィルタ８は一
導電型サブストレート１と他方の第２の論理電位４に接
続される他の導電型ウェル６の上に構成された制御回路
ブロック９に接続されている。FIG. 1 is a circuit layout diagram of an embodiment of the CMOS IC of the present invention. The input circuit block 7 formed on the one conductivity type substrate 2 connected to the first logic potential 1 and the other conductivity type well 5 connected to the second logic potential 3 is the one conductivity type substrate 2 It is connected to the low-pass filter 8 which is constructed above and is composed of a resistor and a capacitor, and the low-pass filter 8 is constructed on the one conductivity type substrate 1 and the other conductivity type well 6 which is connected to the other second logic potential 4. Connected to the control circuit block 9.
以上のように接続された本実施例において、重負荷や静
電気誘導雑音の影響で電源が変動し、第２の論理電位３
と４の間に時間差や変動電圧差により擬似的な論理信号
が発生しても、抵抗とコンデンサによりなるローパスフ
ィルタ８により減衰され制御回路ブロック９には伝播さ
れれない。In the present embodiment connected as described above, the power source fluctuates due to the influence of heavy load and static electricity induced noise, and the second logic potential 3
Even if a pseudo logic signal is generated between time points 4 and 4 due to a time difference or a fluctuation voltage difference, it is attenuated by the low-pass filter 8 including a resistor and a capacitor and is not propagated to the control circuit block 9.
以上説明したように本発明は、入力回路と制御回路の信
号インターフェース経路に抵抗とコンデンサより構成さ
れるローパスフィルタを設け、電源変動時の擬似的な論
理信号を減衰させることにより、誤動作の発生確率を大
幅に低減できる効果がある。As described above, the present invention provides a low-pass filter composed of a resistor and a capacitor in the signal interface path of the input circuit and the control circuit, and attenuates a pseudo logical signal when the power supply fluctuates, so that the probability of malfunction occurs. The effect is that it can be significantly reduced.
第１図は本発明のCMOS・ICの一実施例の回路配置図であ
る。 １……第１の論理電位、２……一導電型基板、3,4……
第２の論理電位、5,6……他の導電型ウェル、７……入
力回路ブロック、８……ローパスフィルタ、９……制御
回路ブロック。FIG. 1 is a circuit layout diagram of an embodiment of the CMOS IC of the present invention. 1 ... first logic potential, 2 ... one conductivity type substrate, 3,4 ...
Second logic potential, 5, 6 ... Other conductivity type well, 7 ... Input circuit block, 8 ... Low-pass filter, 9 ... Control circuit block.
Claims (1)
ブストレートと、このサブストレートに互いに離間に設
けられ第２の論理電位がそれぞれ供給される他の導電型
の第１および第２のウェルと、前記サブストレートの一
部に形成された電界効果型トランジスタおよび前記第１
のウェルに形成された電界効果型トランジスタで構成さ
れた入力回路と、前記サブストレートの他の一部に形成
された電界効果型トランジスタおよび前記第２のウェル
に形成された電界効果型トランジスタで構成された制御
回路と、前記入力回路と前記制御回路との間に設けられ
前記サブストレートのさらに他の一部に形成された抵抗
およびコンデンサで構成されたローパスフィルタとを有
する相補型MOS集積回路。1. A substrate of one conductivity type to which a first logic potential is supplied, and first and second substrates of another conductivity type which are provided on the substrate and are spaced apart from each other and to which a second logic potential is supplied respectively. Second well, a field effect transistor formed in a part of the substrate, and the first
, An input circuit formed of a field effect transistor formed in the well, a field effect transistor formed in another part of the substrate, and a field effect transistor formed in the second well. Complementary MOS integrated circuit having a controlled circuit and a low-pass filter including a resistor and a capacitor provided between the input circuit and the control circuit and formed in yet another part of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173062A JPH077821B2 (en) | 1986-07-22 | 1986-07-22 | Complementary MOS integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173062A JPH077821B2 (en) | 1986-07-22 | 1986-07-22 | Complementary MOS integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6328059A JPS6328059A (en) | 1988-02-05 |
| JPH077821B2 true JPH077821B2 (en) | 1995-01-30 |
Family
ID=15953506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61173062A Expired - Fee Related JPH077821B2 (en) | 1986-07-22 | 1986-07-22 | Complementary MOS integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077821B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4027438B2 (en) * | 1995-05-25 | 2007-12-26 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6261415A (en) * | 1985-09-11 | 1987-03-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1986
- 1986-07-22 JP JP61173062A patent/JPH077821B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6328059A (en) | 1988-02-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |