JPH0792855B2 - Discriminator of currency counter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter for bills, coins and the like, and to a discriminator for a coin counter, which is suitable for discriminating the reading of the counter.

“Prior Art” Generally, in a money counter, not only the money is simply counted, but also its image pattern is read to perform a true / false determination process.

FIG. 5 is a block diagram showing a configuration of a discriminating apparatus according to the first conventional example of the above-mentioned currency counter. In this figure,
This discrimination device is a sensor 2, an amplifier 3, an A / D converter 4, a CPU
(Central processing unit) 5, DMA (Direct Memory Access) controller 8 and two memories 9 and 10. In this discriminating device, one memory 9 is dedicated to writing sampling data SD and the other memory 10
Is dedicated to the discrimination process.

In the configuration described above, first, the image pattern of the first counting object is detected by the sensor 2,
The analog signal from is amplified by the amplifier 3. Then, the analog signal from the amplifier 3 is converted into sampling data SD ₁ of a digital signal by the A / D converter 4. This sampling data SD ₁ is written in the memory 9 by the CPU 5. When the writing of the sampling data SD ₁ is completed, the sampling data SD ₁ written in the memory 9 is transferred to the memory 10 for determination processing by the CPU 5 or the DMA controller 8. When the transfer of the sampling data SD ₁ is completed, the CPU 5 performs a determination process based on the sampling data SD ₁ . Further, during execution of the determination process, the sampling data SD _{2 of the second} counting object is written in the memory 9 in parallel with the interrupt process of the CPU 5. When the determination process for the sampling data SD ₁ is completed, the sampling data SD is transferred from the memory 9 to the memory 10 by DMA transfer or the like.
₂ is transferred. When the transfer of the sampling data SD ₂ is completed, the CPU again based on this sampling data SD ₂
The discrimination process is performed by 5. After that, the new sampling data SD ₃ , SD _4, ... Supplied from the A / D converter 4 are temporarily stored in the memory 9 for each object to be counted, and then transferred to the memory 10 at a predetermined timing. Then, the CPU 5 performs a discrimination process based on the sampling data SD ₃ , SD _4, ... Transferred to the memory 10.

Next, the discrimination device according to the second conventional example will be described.
The structure of this discriminating device is the same as that of the first conventional example shown in FIG. However, in this discriminator, the writing of the sampling data SD ₁ , SD _2, ...
Alternating with each other. First, similarly to the first conventional example, the image pattern of the counting object sequentially supplied is detected by the sensor 2, the analog signal from the sensor 2 is amplified by the amplifier 3, and then by the A / D converter 4. Converted to digital signal sampling data SD ₁ , SD _2, .... The sampling data SD ₁ , SD _2, ... Are alternately written to the memory 9 and the memory 10 by the DMA controller 8 for each counting object. The discrimination process by CPU5 is
The data is sequentially written to the memory on the opposite side to the memory to which the DMA controller 8 is writing, that is, the memory to which the sampling data SD ₁ , SD _2, ... Has already been written.

[Problems to be Solved by the Invention] By the way, in the discriminating apparatus according to the first conventional example shown in FIG. 5, from the memory 9 dedicated to writing to the memory dedicated to discriminating processing.
Need to transfer sampling data to 10. As a result, there arises a problem that the transfer time of the sampling data puts pressure on the determination processing time, making it impossible to perform highly accurate determination processing requiring a relatively long processing time.

In the discriminating apparatus according to the second conventional example, the discriminating process is alternately performed on the two memories as described above. In addition, in general, a large number of instructions related to memory access are described in a program for discrimination processing, and the addresses of the memory to be accessed are described by physical addresses in these instructions. Therefore, if the memory that is the target of the discrimination process is changed, the physical address of the memory changes, and the memory address to be accessed by the above instruction and the physical address of the memory do not match. Therefore, it is necessary to calculate the memory address to be accessed by the above-mentioned instruction during the discrimination processing to obtain the physical address of the memory in which the sampling data is stored. As a result, there arises a problem that the time required for this address calculation puts pressure on the discrimination processing time, making it impossible to perform highly accurate discrimination processing for a relatively long processing time.

The present invention has been made in view of the above problems, and can reduce the pressure on the discrimination processing time, and can discriminate a currency counter that can perform highly precise discrimination processing with a relatively long processing time. The purpose is to provide a vessel.

"Means for Solving the Problem" In order to solve such a problem, the present invention has a plurality of storage areas, each storage area corresponding to the same logical space, and a counting object. The central part which writes the sampling data of 1 to the logical space, performs the discrimination processing of the counting object based on the sampling data read from the logical space, and outputs the control signal indicating any one of the storage areas. The processing unit and the address converter for converting the address of the logical space output by the central processing unit into the physical address of the storage area corresponding to the control signal are provided, and sampling data in the storage area does not conflict. The control signal is generated as described above.

"Operation" The sampling data of the counting object is written in the logical space, and the central processing unit performs the discrimination processing of the counting object based on the sampling data read from the logical space. In this case, the address converter converts the address of the logical space output by the central processing unit into the physical address of the storage area for the control signal output by the central processing unit.

[Examples] Next, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, parts corresponding to those of the conventional example shown in FIG.

In the figure, 11 is an A / D controller, and an A / D converter 4
The sampling start timing, sampling time, etc. are controlled. Also, the controller 11 sends an interrupt request to the CPU 5,
The CPU 5 supplies the controller 11 with a control signal or the like for notifying the operating condition.

12 is an address translator, which is connected to the common address bus AB ₁ . Further, the control signal EXTA ₁₁ is supplied from the CPU 5 to the address converter 12. In the address converter 12, the address data AD ₁ from the CPU 5 is converted into address data AD ₂ based on the control signal EXTA ₁₁ . The address data AD ₂ is supplied to the memories 9 and 10 via the address bus AB ₂ .

Next, the address data from the address converter 12 described above
The conversion to AD ₂ will be described. FIG. 2 is a block diagram showing the configuration of the address converter 12 according to the embodiment of the present invention. In this figure, A _{11 to} A ₁₅ are common address buses
AB ₁ and EXTA ₁₁ are control signals from the CPU 5 described above. Also, right A _'11 ~A' ₁₅ illustrated is an address bus AB ₂ which address data AD ₂ to be converted by the address converter 12 is outputted. Also the memory in this case
As shown in Fig. 3, 9 and 10 are physical addresses 8000, respectively.
It is set to H ~ 87FFH, 8800H ~ 8FFFH.

In this case, in the address converter 12, the circuit is configured so that the following logical expression is realized.

_{A '15 = A 15 ...... (} 1) A' 14 = A 14 ...... (2) A '13 = A 13 ...... (3) A' 12 = A 12 ...... (4) This allows the addressing by CPU5 to be 8000H to 87FFH.
, The control signal EXTA ₁₁ = L, the physical address
When the memory 9 provided at 8000H to 87FFH is accessed and the control signal EXTA ₁₁ = H, the physical addresses 8800H to 8FFFH are set.
The memory 10 provided in the memory is accessed.

Next, the operation of this embodiment having the above configuration will be described. Here, FIG. 4 is a timing chart for explaining the operation of this embodiment.

First, at time t ₁ shown in FIG. 4, the image pattern of the first counting object is detected by the sensor 2, the analog signal from this sensor 2 is amplified by the amplifier 3, and the A / D converter 4 Sampling data S of digital signal
Converted to D ₁ . This sampling data SD ₁ is detected by the controller 11. And the controller 11
Immediately issues an interrupt request to CPU5. When CPU5 receives an interrupt request, the address data AD ₁ 8000H~87FFH, control signal E
XTA ₁₁ = L. The address translator 12 uses the physical address 800 based on the address data AD ₁ and the control signal EXTA _11.
Access the memory 9 from 0H to 87FFH. Therefore, the CPU
5 writes the sampling data SD ₁ from the A / D converter 4 in the memory 9 at physical addresses 8000H to 87FFH (logical addresses 8000H to 87FFH). When the writing of the sampling data SD ₁ is completed, the CPU 5 sets the address data AD ₁ to 8000H to 87FF.
H and control signal EXTA ₁₁ = L. The address converter 12 is
The memory 9 having physical addresses 8000H to 87FFH is accessed based on the address data AD ₁ and the control signal EXTA ₁₁ . Therefore, the CPU 5 performs the determination process based on the sampling data SD ₁ written in the memory 9 at the physical addresses 8000H to 87FFH from time t ₂ .

Next, when the second counting object is detected by the sensor 2 at the time t ₃ , the controller 11 detects
Issues an interrupt request to CPU5. When CPU5 receives the interrupt request,
While intermittently executing the determination process for the sampling data SD ₁ , the sampling data SD ₂ of the _second counting object is set to the physical addresses 8800H to 8FFFH at times t _{3 to} t ₄ .
Write to memory 10 (logical address 8000H to 87FFH).

In this case, the CPU 5 sets the address data AD ₁ to 8000H to 87FFH and uses the control signal when performing the discrimination process for the memory 9.
EXTA ₁₁ = L, sampling data for memory 10
When writing SD ₂ , the control signal EXTA ₁₁ = H.

Then, at time t ₅ , when the determination process for the memory 9 is completed, the CPU 5 sets the control signal EXTA ₁₁ = H,
Based on the sampling data SD ₂ written in 10, the discrimination processing is performed from the same time t ₅ . During the determination process, at time t _6, when the object to be counted third sheet is detected by the sensor 2, as in the 1,2 th, the controller 11 performs an interrupt request to the CPU 5. When the CPU 5 receives the interrupt request, it intermittently executes the determination process for the sampling data SD ₂ ,
At times t _{6 to} t ₇ , the sampling data SD ₃ of the _third counting object is written in the memory 9.

In this case, the CPU 5 sets the address data AD ₁ to 8000H to 87FFH and sets the control signal when performing the determination process on the memory 10.
EXTA ₁₁ = H, sampling data for memory 9
When writing SD ₃ , the control signal EXTA ₁₁ = L.

When the determination process with respect to the memory 10 is completed at time t _8, CPU 5 as a control signal EXTA ₁₁ = L, the memory 9
Based on the sampling data SD ₃ written in
_The discrimination process is performed from ₈ . Thereafter, in the same manner as described above, the writing of the sampling data SD ₄ , SD _5, ... By the CPU 5 and the determination processing are alternately performed on the memories 9 and 10. As described above, this embodiment does not require transfer of the sampling data SD ₁ , SD _2, ... And also does not require address calculation during the discrimination processing.

Although the memory in the above embodiment is a work area for two blocks, by changing the number of control signals EXTA ₁₁ and the logical expression for address conversion as necessary,
The number of work areas (the number of memories) may be increased. Also,
An MMU (memory address unit) may be used as the address converter 12 described above.

[Advantages of the Invention] As described above, according to the present invention, an address converter converts an address of a logical space output by a central processing unit into a physical address of a storage area for a control signal output by the central processing unit. As a result, it is possible to reduce the pressure on the discrimination processing time, and it is possible to obtain the advantage that high-precision discrimination processing with a relatively long processing time can be executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of an address converter according to this embodiment, and FIG. 3 is a diagram showing an address arrangement of a memory according to this embodiment. FIG. 4 is a memory layout diagram for doing so, and FIG. 4 is a timing chart for explaining the operation of this embodiment.
FIG. 5 is a block diagram showing a configuration of a conventional discriminating device for a currency counter. 5 ... CPU (central processing unit), 9, 10 ... memory (storage means), 12 ... address converter.

Claims (1)

[Claims] 1. A storage means having a plurality of storage areas, each storage area corresponding to the same logical space, and sampling data of an object to be counted is written into the logical space and read from the logical space. The central processing unit that performs the discrimination processing of the counting object based on the sampled data and outputs the control signal indicating any one of the storage areas, and the address of the logical space output by the central processing unit Discrimination of a money counter, comprising: an address converter for converting a physical address of a storage area corresponding to a control signal, and creating the control signal so that sampling data in the storage area does not conflict. apparatus.