JPH079758B2 - Sense circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a sense circuit for detecting a storage state of a memory cell in a semiconductor memory device including memory cells such as a ROM, a PROM, and an EPROM.

(Prior Art) As an example of a sense circuit of such a memory, the one shown in FIG. 6 is known. M1 is one of a plurality of memory cells connected to the sense point D1, and its gate electrode is connected to the word line W1. The word line W1 is connected to the decoder via the buffer circuit, and selected by the signal decoded by the decoder via the buffer circuit. A P-type MOS transistor (MOS transistor is simply referred to as a transistor hereinafter) Q1a is connected to each sense point D1 via an N-type transistor Q2a in order to supply a current to the memory cell at the time of reading. The gate electrode of the transistor Q1a is set to the ground potential during operation. A circuit C1 including a P-type transistor Q3 and an N-type transistor Q4 is a circuit for detecting the voltage level of the sense point D1, and the gate electrode of the transistor Q4 is connected to the sense point D1. A node N1 between the transistor Q3 and the transistor Q4 is connected to the gate electrode of the transistor Q2a. Thereby, the ON state or the OFF state of the memory cell M1 is detected by the bit line voltage detection circuit C1 as a voltage change of the sense point D1, the impedance of the transistor Q2a is controlled, and the voltage level of the node N2a of the transistor Q1a and the transistor Q2a becomes It appears as a difference. The circuit composed of the P-type transistor Q5 and the N-type transistor Q6 supplies current to the sense point D1 together with the transistor Q1 when the memory cell M1 is on,
This is a circuit for controlling the voltage drop at the sense point D1 to shorten the access time.

Another known sense circuit such as a ROM is the sense circuit shown in FIG. 6 is different from the sense circuit in FIG. 6 in that the current supply circuit including the transistors Q5 and Q6 is controlled by the bit line voltage detection circuit C1 in the circuit in FIG. In the sense circuit, the current supply circuit consisting of the transistors Q5a and Q6a. Bit line voltage detection circuit C1a provided separately
The configuration relating to the memory cell M1 and the transistor Q1a for supplying a current to the memory cell is the same in both circuits.

In such a sense circuit, the current driving power Il of the transistor Q1a that supplies a current to the memory cell is usually a current (on current) I on when the memory cell M1 is on and a current (off current) I off when the memory cell M1 is on. Is set between. That is, I off <Il <I on. At this time, the sense margin for detecting the on-state of the memory cell M1 is (I on-Il), and the sense margin for detecting the off-state is (Il-I off).

However, in such a sense circuit, the change of Il
Changes in I on do not compensate each other. As a result, the following problems occur.

(1) Even if the channel length or threshold value of the memory cell transistor fluctuates due to manufacturing process fluctuations and Ion fluctuates, Il is a transistor Q1a that supplies current to the memory cell.
Is constant and is constant, and therefore the on-side sense margin (I on-Il) varies. That is, for example, Il is the 8th
If it was set as shown in the figure, the on-current (I
on), the on-side sense margin decreases,
As shown in the figure, the on-side access time for on-state detection becomes longer.

(2) Since the change in Il is small with respect to the change in I on due to the change in current voltage (V cc), the on-side sense margin also changes in this case.

(3) When the manufacturing process changes, the transconductance, the threshold value, or the channel length of the transistor Q1a that supplies the current to the memory cell changes contrary to (1), and Il changes, and Ion is constant. However, the on-side sense margin also fluctuates.

(Object) The present invention has a wide sensing range even when Ion of a memory cell transistor, a transistor constant of a transistor that supplies a current to a memory cell, a process parameter, or a power supply voltage changes due to a change in a manufacturing process. An object of the present invention is to provide a sense circuit such as a read-only memory that can maintain a margin.

(Structure) According to the present invention, referring to FIG. 1 or FIG. 5 showing an embodiment, a current is supplied from a P-type MOS transistor Q1 to a memory cell M1 to turn on or off the memory cell M1. A sense circuit for detecting the storage state of the memory M1 by detecting, and is provided with at least one reference cell M11 capable of flowing a current having the same magnitude as the ON current of the memory cell M1. A read voltage is applied to the gate electrode of the reference cell M11, and a load circuit for supplying a current to the reference cell M11 is provided. The load circuit has a size W / L (W is a channel width, L is a channel width). Channel length) is at least 1 larger than the P-type MOS transistor Q1 that supplies current to the memory cell
Second P-type MOS transistors or at least two P-type MOS transistors (Q11, Q12) whose size W / L is the same as P-type MOS transistor Q1 which supplies current to the memory cell
A second parallel circuit of a load circuit of the reference cell M11, the parallel circuit including a P-type MOS transistor group including
Type MOS transistors or P-type MOS transistors (Q11, Q12) included in the P-type MOS transistor group have drain electrodes of the second P-type MOS transistor or the P-type MOS transistor (Q11 included in the P-type MOS transistor group, respectively). , Q12)
P-type MOS that supplies current to the gate electrode and memory cell of
This is characterized in that the gate electrode of the transistor Q1 is connected.

Examples of the present invention will be specifically described below.

FIG. 1 shows an embodiment of the present invention.

B1 is a bit line, a plurality of memory cells are connected to each bit line B1, and M1 represents one of them.
There are multiple bit lines, which are selected by the multiplexer composed of transistors Q7 and Q8 and
It is connected to D1.

A P-type transistor Q1 that supplies a current to the memory cell is connected to the sense point D1 via an N-type transistor Q2. C1 is a bit line voltage detection circuit, which is composed of an inverter circuit that uses a P-type transistor Q3 whose gate electrode is grounded as a load. The gate electrode of the transistor Q4 of the inverter circuit is connected to the sense point D1 and selected through a multiplexer. The voltage of the selected bit line B1 is detected. A node N1 which is an output terminal of the bit line voltage detection circuit C1 is connected to the gate electrode of the transistor Q2.

M11 is a reference cell provided for at least one memory cell that mainly stores information. The reference M11 has the same size as the memory cell M1 and has a memory cell M1.
It is composed of a transistor capable of passing the same amount of current as the ON current of 1, and its gate electrode is connected to the terminal of the power supply voltage V cc used for reading.

In order to supply a current to the reference M11, a load circuit including a parallel circuit of two P-type transistors Q11 and Q12 having the same size as the transistor Q1 that supplies a current to the memory cell is provided. The drain electrode node N3 is connected to the gate electrodes of the transistors Q11 and Q12, and the node N3 is connected to the gate electrode of the transistor Q1 which supplies a current to the memory cell.

Between the node N3 of the reference side load circuit and the reference cell M11, a transistor Q21 having the same size as the memory cell side transistor Q2, and a transistor Q71, Q81 having the same size as the memory cell side multiplexer transistors Q7, Q8 are provided. The gate electrodes of the transistors Q71 and Q81 are connected to the terminal of the power supply voltage V cc. C11 is a reference side bit line voltage detection circuit equivalent to the bit line voltage detection circuit C1 on the memory cell side, and is provided with transistors Q31 and Q41 of the same size as the transistors Q3 and Q4 forming the bit line voltage detection circuit C1. It is composed of an inverter circuit. The gate electrode of the transistor Q31 of the bit line voltage detection circuit C11 is grounded, and the transistor Q41
Is connected to the reference-side sense point D11, and the node N4 which is an output terminal of the bit line voltage detection circuit C11 is connected to the gate electrode of the transistor Q21.

Next, the operation of this embodiment will be described.

Transistors Q11, Q12 constituting the load circuit of the reference cell M11 supplies the load current Il ₁₁ only corresponds to the on-current of the reference cell M11. Then, at this time, the potential of the node N3 is determined so that the load current Il ₁₁ is supplied through the two transistors Q11 and Q12. node
N3 is also a transistor Q1 that supplies current to the memory cell.
Since it is also connected to the gate electrode of, the transistor Q1
Current drivability Il ₁ of the Il _11/2. Il ₁₁ is memory cell M1
Since it is also equal to the ON current of, Il ₁ = (ON current) / 2 after all.

That is, the load current Il ₁ of the memory cell M1 is
Transistor constant of 1 (channel width, channel length, etc.)
It is determined by the on-current of the memory cell M1 regardless of the process parameters (transconductance, threshold value, etc.). As a result, the on-side and off-side sense margins change as shown in FIG. 2 with respect to changes in the on-current of the memory cell M1 and have a wide operation margin. As a result, the on-side and off-side access times are gradually changed as shown in FIG. 3, and abruptly with respect to the decrease in the on-current of the memory cell M1 as in the conventional example shown in FIG. No longer shows a significant increase.

In the embodiment of FIG. 1, the load circuit on the reference side is 2
Although a parallel circuit of transistors Q11 and Q12 is used, this load circuit may be composed of one transistor having a size W / L larger than the transistor Q1 which supplies the current to the memory cell, or three transistors. It may be configured by a parallel circuit of the above transistors. The potential of the node N3 depends on the on-current of the reference cell M11 and the sizes of the transistors Q11 and Q12 of the load circuit on the reference side.
It is desirable to set the sizes of the transistors Q11 and Q12 so that the potential of is higher than the potential of the reference side sense point D11.

The gate electrode of the reference cell M11 in the embodiment of FIG. 1 is connected to the power supply voltage terminal, and this gate electrode is connected to the gate electrode (word line) of the memory cell and is equivalent to the buffer circuit of the decoder. Connect to
A voltage may be supplied to the gate electrode of the reference cell M11 so that the reference cell M11 is turned on when the memory cell to be read is selected by the reference cell M11.

Also, the bit line voltage detection circuits C1 and C11 in FIG.
Alternatively, the circuit may be constituted by a CMOS inverter circuit as shown in FIGS. 4A and 4B, respectively.

FIG. 5 shows another embodiment of the present invention. Compared with the embodiment of FIG. 1, first, the sense point on the memory cell side
In order to suppress the decrease in the potential of D1, a current supply circuit C2 including transistors Q5 and Q6 is added to the sense point D1 as in the conventional sense circuit of FIG. 6, and the sense point on the reference side is added. D11 is different in that a current supply circuit C21 including transistors Q51 and Q61 equivalent thereto is added. In addition, P-type transistors Q3, Q
The gate electrodes of 5, Q31 and Q51 are connected to the control line N5, the N-type transistor Q9 is connected to the node N4 of the reference side bit line voltage detection circuit C11, and the gate electrode of this transistor Q9 is also connected to the control line N5. The connection is also different from the embodiment shown in FIG. Although the control line N5 is normally set to the ground potential, it is set to the power supply voltage V cc during standby, so that the transistors Q3, Q5, Q31 and Q5
By turning off 1 and turning on the transistor Q9, the DC path of these circuits is cut off to reduce power consumption. In this embodiment, the memory cells M1 and the reference cells M11 are EPROMs. FAMOS is used.

(Effect) Since the sense circuit of the present invention is configured such that the current driving force of the transistor that supplies a current to the memory cell is determined by the on-current of the memory cell, the following effect can be achieved. it can.

(1) A wide sense margin is provided with respect to variations in the on-current of the memory cell due to variations in the channel length of the memory cell transistor and variations in the threshold value that occur due to variations in the manufacturing process.

(2) A wide sense margin is provided even with variations in the power supply voltage.

(3) A wide sense margin can be obtained with respect to the characteristics of the transistor that supplies current to the memory cell, such as the channel length, the threshold value, and the mutual conductance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing changes in sense margin and access time with respect to variations in on-current of a memory cell in the embodiment, respectively. 6A and 6B are circuit diagrams showing another example of the bit line voltage detection circuit in the same embodiment, FIG. 5 is a circuit diagram showing another embodiment, and FIGS. 6 and 7 are respectively. Circuit diagrams showing a conventional sense circuit, FIG. 8 and FIG.
Each of the figures is a diagram showing changes in the sense margin and access time with respect to variations in the on-current of the memory cell in the conventional sense circuit. Q1, Q11, Q12 ... Transistors that supply current to memory cells or reference cells, M1 ... Memory cells, M11 ... Reference cells.

Claims (1)

[Claims] 1. A sense circuit for detecting a storage state of a memory cell by supplying a current from a first P-type MOS transistor to the memory cell and detecting an ON state or an OFF state of the memory cell. At least one reference cell through which a current of the same magnitude as the current can flow is provided, a read voltage is applied to the gate electrode of this reference cell, and a current is supplied to this reference cell. A load circuit is provided, and the load circuit has at least one first W-L size (W is a channel width, L is a channel length) larger than the first P-type MOS transistor for supplying a current to a memory cell. 2 P-type MOS transistors or at least 2 whose size W / L is the same as said first P-type MOS transistor supplying current to the memory cell Becomes a parallel circuit consisting of P-type MOS transistor group including a P-type MOS transistor, and said second P of the load circuit of the reference cell
Type MOS transistors or P-type MOS transistors included in the P-type MOS transistor group, and the drain electrodes of the P-type MOS transistors included in the second P-type MOS transistor group or the P-type MOS transistor group included in the P-type MOS transistor group. The first P-type MO for supplying current to the memory cell
A sense circuit in which the gate electrode of an S transistor is connected.