JP2923677B2 - Manufacturing method of vertical channel type insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an insulated gate field effect semiconductor device of a semiconductor integrated circuit, particularly, an ultra-high-density integrated circuit (referred to as ULSI) of a 16M to 16 Gbit level. Related to providing.

The present invention relates to a semiconductor device, in particular, a vertical channel type MIS (insulating gate type) field effect semiconductor device having a microchannel type in which current flows in the vertical direction (hereinafter, a channel length is 1 μm).
The following is referred to as a μ-channel MIS FET because the thickness is 0.03 to 1 μm) and a semiconductor device in which a capacitor is connected thereto, for example.

The present invention relates to a (100) crystal plane or a crystal plane in the vicinity thereof ((100) plane or the vicinity thereof, that is, ± 10 ° from the (100) plane).
The crystal plane of the deviation within (hereinafter simply referred to as (100) plane) is provided by performing anisotropic etching on a rectangular convex region, and impurities are added to the side surface of the convex region by ion implantation. In addition, the channel formation region controls a threshold voltage, and the other aspect relates to a vertical channel type MISFET which prevents generation of a parasitic channel.

[Prior Art] Conventionally, as shown in FIG. 1, the structure of a MIS FET or a capacitor connected in series with the MIS FET is formed on one surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. A gate insulator (2), a gate electrode (18) and a source or drain (4), a drain or source (5) are provided as LDD (drain having a relatively low impurity concentration, ie, a lightly doped drain), and outside thereof. A first impurity region (15) and a second impurity region (14) having a high impurity concentration are formed in a plane to form an MIS FET (10). Further, the capacitor (20) is provided with a lower electrode (21), a dielectric (22), and an upper electrode (23) connected to the first impurity region (15). Thus, MIS FET (10),
The capacitor (20) has been formed on the semiconductor substrate so as to have the same plane. In the case of 1Tr / Cell (a memory in which one MIS FET and one capacitor are connected in series to constitute one bit), this planar configuration increases the cell area, and limits the high-density integration. Was.

On the left and right sides of the gate electrode (18), LDD (4),
As auxiliary means for producing (5), there were rectangular or triangular portions (38) and (38 '). According to the present invention, a gate electrode is provided as a laminate on the rectangular or triangular portion, and a convex region therefor is defined as a (100) plane, and four side faces having the rectangle are defined as a (100) plane. Is used.

[Object of the Invention] In the present invention, a rectangular convex region having a (100) plane on a plane and a side surface is provided, and one or two side surfaces of this region are used as a channel forming region. That is, a current flows in the vertical direction, the channel length is extremely small, 0.03 to 1 μm, and the size of one MIS FET is 1 μm.
□ to 10μm □
An object of the present invention is to provide an element structure for ULSI that can be made up to 6 Gbits. It is still another object of the present invention to provide an inverter structure by combining the MIS FET and a memory cell structure connected to another element such as a capacitor.

"Configuration of the Invention" In the present invention, a rectangular convex region is provided on a (100) plane semiconductor substrate. Then, each of the four side surfaces having the convex (100) surface is simultaneously defined as a (100) surface, and the side surface is defined as a channel forming region.
That is, it was a vertical channel type. Further, by adding an impurity to the rectangular convex region from the lateral direction or the oblique direction using an ion implantation method or the like, the threshold voltage of the channel formation region was controlled and the embedding channel was formed.

Although this impurity concentration differs depending on the interface state density, the threshold voltage is set to within ± 1 V, +0.1 to 7 V for normally-off, and -0.1 V for normally-on.
Performed at ~ -1.0V and N-channel MIS FET. P channel M
The opposite sign is used for IS FET. On the side where no channel is formed, the generation of a parasitic channel is prevented in the vertical direction so that a minute leak due to the generation of a parasitic channel does not flow. In order to prevent this parasitic channel, in the N-channel MISFET, boron is set to a concentration lower than the impurity concentration of the source or drain for LDD and higher than the impurity concentration of the substrate. Generally 1 × 10
^{It was 16 to} 2 × 10 ¹⁷ cm ⁻³ .

An object of the present invention is to provide an asymmetric MIS FET by forming the source and the drain in such a MIS FET in the lateral direction in order to facilitate electrode formation in a subsequent process. That is, a rectangular convex single crystal semiconductor region is provided on one main surface of the semiconductor substrate, and one of the source or drain of the MIS FET is configured as an LDD on the upper portion, and a side portion of the convex region is a vertical channel forming region. The bottom of the semiconductor substrate
The drain or the source of the LDD structure is used. The source or the drain and the drain or the source have an impurity concentration as low as 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ to improve the drain withstand voltage and the parasitic capacitance with the gate electrode. And prevent hot carriers from being injected into the gate insulator. That is, a rectangular or triangular gate electrode is provided on the gate insulating film at the corner portion of the convex region, in addition to the LDD.

The upper lateral portion of the gate electrode coincides with the end of the source or drain or is slightly larger on the source or drain side, and is located below the second impurity region thereon, so that the gate electrode has an offset structure. And a margin is given to manufacturing.

The source or the drain and the drain or the source are provided so that the second impurity region and the first impurity region having a high impurity concentration are easily brought into ohmic contact with an external electrode.
It is provided with a lateral surface such that the contact surface is on the upper side.

For this reason, the semiconductor device of the present invention achieves the high density for forming the ULSI not by reducing the area occupied in the substrate of the conventional lateral MISFET by scaling, but by providing it actively in the height direction. It is an object.

 An embodiment of the present invention will be described below with reference to the drawings.

Example 1 In this example, the manufacturing process is shown in FIG. 2, and a vertical channel type N-channel MISFET is formed by using a rectangular convex region of a single crystal semiconductor substrate having a (100) plane. Two are provided as a pair.

2 (A) to 2 (D) show longitudinal sectional views, and FIG. 2 (E) shows a plan view. The cross section taken along line AA ′ of FIG. 2E corresponds to FIGS. 2A to 2D.

A single crystal semiconductor substrate having a (100) plane, for example, a silicon single crystal semiconductor (100) plane, and a P-type 10 to 500 Ωcm was selected. Using a first photomask for this single crystal substrate,
As shown in FIGS. 2A and 2E, a rectangular convex region (35) was formed when viewed from above. The anisotropic etching of the silicon single crystal substrate is performed by photoresist (3
2) may be formed as a mask. It is important that the corner has a very sharp vertical surface at 90 ° to the upper surface of the substrate. The height of the convex region (35) was 0.5 to 4 μm, for example, 1.5 μm.

Then, as shown in FIG. 2 (E), in the convex region (35) having a rectangular shape, the channel formation region becomes the (100) plane (the <100> direction (40)), and the parasitic channel prevention surface also becomes (010). ) Plane (<010> direction (40 ')).

Then, the fixed charge density can be reduced to about half of that of the other (11) and (111) crystal planes on all of the sides.

Silicon nitride that has a masking action against oxidizing gas (33)
Was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask () to use the selective oxidation method, thereby forming FIG. 2A.

After doping the removed region with a P-type impurity for forming a channel cut, a field insulator (3) is
It was formed by being embedded to a thickness of 0.5 to 2 μm.

As shown in FIG. 2B, the silicon nitride film (33) is removed to form a film (2) for forming a gate insulating film on the semiconductor substrate (1) having the convex region (35). did. A semiconductor substrate (1) doped with As or phosphorus by ion implantation to a relatively low concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 from the vertical direction and to a depth of 3000 to 1 μm, for example 5000 °; N at the bottom of the surface and at the top of the convex area (35)
The drain or source (5), (5 ') and the source or drain (4) of the mold are configured as LDD.

The channel forming regions (6) and (6 ') are defined by the source or drain (4), the drain or source (5), and (5').
Before or after the formation of the gate insulating film (2), or before or after the formation of the gate insulating film (2), it is formed on the side surface of the rectangular convex region by means such as ion implantation. That is, the channel forming regions (6) and (6 ') control the threshold voltage, and for an enhancement type MISFET, normally off to +0.1 to + 1.0V, for example, to + 0.5V. Normally on -0.1 ~-for depletion type MIS FET
Achieved by controlling the dose amount to 1.0 V, for example, -0.5 V. These were used as channel formation regions, and one or both of (6) and (6 ′) were formed automatically using a photomask. Two types of impurities may be added twice as the embossed channel type. These positively added impurities to the side surfaces on the (6) and (6 ') sides of the convex region (35). For example, the ion implantation (38) and (38 ') from the lateral or oblique direction is doped with boron or boron and arsenic.

In the rectangular convex region (35) where the channel is not formed ((36) and (36 ') in FIG. 2 (E), a parasitic channel is easily generated, and the source or drain (4) and the drain or Boron was added at a higher concentration than the substrate, that is, the convex region, so as to prevent a minute leak current from being generated between the sources (5) and (5 '), and the channel was cut so that the off state was always achieved. That is, the ion implantation was achieved in the oblique direction or the lateral direction with respect to the upper surface of the substrate.

Since not only the substrate but also the insulating film (33) or (2) is damaged by these ion implantations, the whole is annealed to monocrystallize the semiconductor substrate (1) and the convex region (35).

This ion implantation step is performed in the same manner as in FIG.
This may be performed as shown in FIG.

By removing the silicon oxide film (2), another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film (2).
It may be.

Next, as shown in FIG. 2 (C), a window for forming a source or a drain was formed in the gate insulating film (2) using a third photomask (). After sufficiently cleaning the surface of the insulating film, a low pressure gas phase method (LPCVD
A silicon semiconductor film (7) doped with an impurity of one conductivity type, for example, an N-type impurity (phosphorus) to a concentration of 1 to 10 × 10 ²⁰ cm ⁻³ by a gate electrode to a thickness of 0.5 to 2.5 μm. And other leads were formed. The doping of the impurity is not performed simultaneously with the film formation, but after performing a step of performing the following anisotropic etching to leave portions (8) and (8 ′) serving as gates on the film (7), a diffusion method is used. It may be doped.

This coating (7) may be a metal or an intermetallic compound instead of silicon doped with impurities. Plus P ⁺
Or N ⁺ type semiconductor and metal or metal compound, especially Mo, W
Alternatively, it may be a multilayer film with silicide (MoSi ₂ , WSi ₂ ).

 Thus, FIG. 2 (C) was obtained.

Next, as shown in FIG. 2 (D), a photoresist (for example,
OMR-83 Tokyo Oka) ()
Thereafter, anisotropic etching was performed. For this etching, it is important to use an anisotropic etching method with very little or no side etch and taper etch, instead of an isotropic etching method using a conventionally used solution. Specifically, a reactive gas for etching, for example, nitrogen fluoride (NF ₃ ) or carbon fluoride (CF ₄ ) is chemically activated by microwaves using 2.45 GHz, and the degree of vacuum is further reduced to 0.1 to 0.001. torr especially 0.005
A fluorine shower, which was made into a plasma in an atmosphere having a degree of vacuum of about 0.01 torr, was caused to flow vertically from the upper surface of the substrate, a bias was applied to the substrate, and an attempt was made to eliminate side etching as a low-temperature etching.

As a result, when the planar portion where the photoresist is not formed in the coating (7) is completely removed, the coatings (8) and (8 ') on the side portions which are the corners of the convex region (35).
Could be left as the rectangular or triangular gate electrodes (18) and (18 ') around the side. Furthermore, the contact (1) of the first impurity region (corresponding to (15) in FIG. 2D) of the drain or source (5), (5 ′)
In this example, 1) and its lead (12) could be left as an electrode lead of the N ⁺ type.

The gate electrodes (18) and (18 ') do not exist over the upper surface of the convex region (35), and the width thereof is not the width determined by photolithography, but is anisotropic with the thickness of the side surface of the coating (7). It can be determined by the degree of the reactive etching.

And the gate electrode (18) is as shown in FIG.
Extend it as a lead (38), and use another gate electrode (1
8 ') connects the lead (12') to the contact (11 ').

In FIG. 2 (D), rectangular or substantially triangular gate electrodes (18) and (18 ') have a lower end portion having a width of 0.1 to 1 [mu] m.
However, the layer is extended as a lead on the field insulator as required for design, and the width of the lead is provided as wide as 1 to 10 μm, and other layers provided on the same substrate are provided. It goes without saying that it may be connected to the electrode lead of the MIS FET or may be electrically connected to other capacitors, resistors, and the like.

In FIG. 2 (E), the inverter, that is, the load (1
0 ') and the driver (10). Although not shown in the drawing, an interlayer insulating film is formed on the whole after these, the output is connected to the second impurity region (14), and the current is applied to the electrode (1).
2 ′) may be connected by providing a multilayer wiring.

Upper end (48) of this rectangular or triangular gate electrode
Is substantially coincident with the end (44) of the source or drain, that is, is located at the same level or above, and is located away from the end (45) of the second impurity region (14) formed in a later step. Is preferred. The width between (44) and (45) is extremely important as a margin in manufacturing.

The channel length of the MISFET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). The LDD source or drain (4) is provided as a margin for the height of the gate electrodes (18) and (18 ').
The gate electrodes (18) and (18 ') are characterized in that they do not enter an offset state.

Next, as shown in FIG. 2 (D), ohmic contact is made at the electrode with a higher concentration than the source or drain (4) and the drain or source (5), (5 ') by ion implantation. Therefore, arsenic, which is an N-type impurity, is implanted at an acceleration voltage of 30 to 150 KeV, and 1 × 10 ¹⁹ to 1 × 10 ¹⁹
At the impurity concentration of about 10 ²¹ cm ^-3 , the first impurity region (15),
(15 ') was formed on the bottom of the substrate, with its end (47) substantially matching the position of the lower end (46) of the rectangular or triangular gate electrodes (18), (18'). In addition, a second impurity region (14) is simultaneously formed on the N-type drain or source (4) above the convex region (35) to facilitate ohmic contact with another electrode.

Thus, it is a vertical channel type, and the source and drain are LD
It was possible to obtain a vertical channel type so-called vertical / horizontal type MISFET while using the D structure, while using the plane above the convex region and the bottom surface of the substrate for contact with the outside. Therefore, it is easy to form electrodes (contacts) for the source and drain, and the channel length is as small as 0.1 to 1 μm, and the length can be precisely controlled and manufactured by using the LDD structure.

As is apparent from the above embodiments, the present invention provides a vertical rectangular or triangular gate electrode (18), (18 ') adjacent to a convex region while increasing the mechanical strength and increasing the channel forming region. (16), (16 ') using the (100) plane to reduce the interface state (due to the generation of positive charges due to the presence of dangling bonds in silicon), so that the adjacent source or drain (4), A vertical channel type MISFET in which the drain or source (5) and (5 ′) are LDD was obtained.

On the other side surface of the rectangular convex region ((36) and (36 ') in FIG. 2 (E)), the side surface is also a (100) surface so that a parasitic channel does not occur. The generation of fixed charge was prevented. To this end, this aspect (10
0) plane and boron in Fig. 2 (E)
As shown in (36) and (36 '), added channel cuts were formed.

2D, the source or drain (4), the drain or source (5), (5 ')
Are separated at the channel forming regions (6) and (6 '), and the gate electrodes (18) and (18') are formed on the side surfaces of the gate insulating film (2) on the side surfaces of the channel forming regions, thereby precisely. A vertical / horizontal micro-channel (μ-channel) MISFET having a controlled channel length and a small area for covering the entire transistor substrate can be manufactured.

Furthermore, after forming a lead in the direction perpendicular to these leads (19) and (12) with a polyimide-based insulator such as PIQ, the metal on the upper surface is selectively removed by photolithography to form a multilayer wiring. Can be done.

In the embodiment of the present invention, the conductivity type is such that the substrate is P ^- type, the channel region (6) is P-type, the source or drain (4), the drain or source (5), (5 ') is the N-type low concentration region. ,
Further, (14), (15), and (15 '') are N ⁺ type high concentration regions. Further, the gate electrodes (18) and (18 '') are a so-called two-sided pair formed by using respective side surfaces of the convex region.
One μMIS FET.

Further, in the present invention, the second impurity region (14) and the gate electrode (18) of the second MISFET are connected by a multilayer wiring, and the channel is normally turned on to constitute a load. An E / D type (driver is an enhancement type, load is a depletion type) inverter structure that takes out the output from the (14) using the MIS FET (10) as a driver may be used.

FIG. 1 shows a case where two MISFETs in a rectangular convex region are formed in an N-channel type, but another MISFET is formed in a P-channel type in another portion separated by a field insulator. The use of an LSI or VLSI as a structure (complementary structure) can further promote the present invention.

Embodiment 2 FIG. 3 (A) shows another embodiment to which the present invention is applied.

FIG. 3 (A) is a longitudinal sectional view taken along line AA ′ of FIG. 3 (B), and its electric circuit is shown in FIG. 3 (C).

That is, the rectangular convex region (35) has channel forming regions (6) and (6 '), on which a source or drain (4) and a high-concentration second impurity region (14) are provided. Have.
In addition, a field insulator (3) is provided on the periphery of the bottom of the semiconductor substrate (1), and the first impurity region (15),
(15 ') and a drain or source (5) outside thereof,
Two MIS FETs (10) and (10 ') were formed as (5'), gate electrodes (18) and (18 '), and gate insulating films (2) and (2').

The channel forming region (6), (6 ') is a channel-shaped Buried, P-type regions in the N-channel MIS FET (6), (6'), N-type or P ^- region (46), (46 ' ),
P-type regions (56) and (56 ') are configured. In the plurality of oblique or lateral ion implantations, the other side surfaces (36) and (36 ') are masked with a photoresist, and conversely, boron implantation for preventing a P-type parasitic channel is performed. When performing steps (36) and (36 '), the side surfaces (6) and (6') were masked with a photoresist so as not to be implanted here.

In order to make multi-layer wiring, contacts (11), (11 '), (11'') are formed by selective growth of tungsten, and aluminum leads (12), (12'), (24) are further replaced with an interlayer insulator. (17) Formed on top.

An interlayer insulator such as polyimide is formed, and a third
May be formed.

The cell area was extremely small and could be formed at a high density. Example 1 was used for manufacturing steps not shown in this example.

In the present invention, the leads (12) and (12 ') may be used as a lower electrode of a capacitor, a dielectric may be provided thereon, and a capacitor may be provided thereon as an upper electrode to provide a 1Tr / Cell memory. Then, it could be made as a stacked memory cell. In addition, this capacitor is placed on the field insulating film (3) or on the convex region (35) and the gate electrode (1).
8) and (18 '), and the cell area could be increased in density.

In this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24), and the word line is the gate electrode (1).
8), (18 ') and a pair of 1Tr / cell memory systems.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to form a floating gate nonvolatile memory.

In the above two embodiments, the material constituting the first region or the vertical rectangular or triangular gate electrode (18)
Is mainly described as a material having the same main component as that of a substrate doped with an impurity having a P ⁺ or N ⁺ conductivity type, for example, silicon.

In the present invention, the semiconductor substrate is mainly described with single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP or a polycrystalline, amorphous or semi-amorphous semiconductor.

The above embodiment mainly shows the case of the N-channel MIS FET. However, P-channel MIS using other convex regions
It is also possible to configure a FET and use it as a complementary channel.

Further, the channel forming region may be a buried channel type instead of the MIS FET using surface diffusion. Further, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[Effects] As is clear from the above embodiments, the present invention is not a conventional structure in which a source and a drain having a pair of structures are separated from each other by a gate electrode and wired in the horizontal direction. The upper surface has the same plane as that of the substrate, and the channel has a vertical shape to form a microchannel. In order to form such a microchannel, the convex region is rectangular, and the side surfaces are all (100) planes to reduce the generation of interfacial charges, facilitate anisotropic etching, and facilitate manufacturing. In addition, generation of a parasitic channel is prevented by lateral or oblique ion implantation, and the threshold voltage in the N-channel formation region can be easily controlled.

Channel lengths should be LDD so that they can be precisely controlled.
The source and the drain are formed, and the characteristics are controlled by the ion implantation concentration. The gain electrode has a convex first shape.
The structure was reinforced mechanically so that the side portions of the region were more extended over the region, and efforts were made to increase reliability.

Due to its structural features and the channel length of 0.1 to 1 μm, an extremely short channel (μ channel) MISFET having a frequency response speed of 1 to 10 GHz can be implemented without using technology such as electron beam exposure as an absolute requirement. It has a big feature.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing a manufacturing process and a structure of the embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Convex area 3 ... Field insulator 4 ... Source or drain 5,5 '... Drain or source 14 ... Second impurity region 15,15' ... First Impurity region 18, 18 ': Gate electrode 10, 10': Insulated gate field effect transistor (MIS FE
T) 36,36 ': Boron-doped region for preventing parasitic channel 38,38': Direction of ion implantation 40,40 ': Crystal orientation ~: Patterning by photomask

Claims (2)

(57) [Claims] A step of forming a convex region on a semiconductor substrate of one conductivity type; a step of forming a source or a drain and a drain or a source on an upper portion of the convex region and a bottom of the semiconductor substrate; Forming a gate insulating film on the side surface of the convex region, and forming a channel forming region by adding an impurity for controlling a threshold voltage before or after the step of forming the gate insulating film; A step of adding an impurity of a conductivity type opposite to that of the source or drain to prevent generation of a parasitic channel on a side surface on which channel formation is not performed, simultaneously with or before or after the step; Forming a rectangular or triangular gate electrode at a corner portion of the convex semiconductor substrate. The method for manufacturing a mold field effect semiconductor device. 2. A step of forming a convex region on a semiconductor substrate of one conductivity type; a step of forming a source or drain and a drain or source on an upper portion of the convex region and a bottom of the semiconductor substrate; Forming a gate insulating film on the side surface of the convex region before or after the step; and ion-implanting the side surface of the convex region on the semiconductor substrate laterally or obliquely before or after the step. And by adding an impurity of a conductivity type opposite to that of the source or the drain to eliminate the occurrence of a parasitic channel on the side where no channel is formed, and selectively forming a channel formation region opposite to the source and the drain. Add a conductivity type impurity or an impurity of the same conductivity type to form a recessed channel type, normally-on type, or normally-off type channel. And forming a rectangular or triangular gate electrode on a corner portion of the convex semiconductor substrate on the gate insulating film, wherein the vertical channel type insulated gate type field effect semiconductor device is provided. Method of manufacturing.