JP3352999B2 - Manufacturing method of vertical channel type insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to providing a structure of a memory cell of an ultra-high density integrated circuit (referred to as ULSI) at a 16M to 16Gbit level. The present invention relates to a semiconductor device, in particular, a MIS (insulating gate) field effect semiconductor device having a microchannel type.
(Hereinafter referred to as a μ-channel MISFET because the channel length is 0.03 to 1 μm of 1 μm or less) and a capacitor connected in series with the MISFET.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 1, the structure of a MIS FET or a capacitor connected in series with the MIS FET is formed on a surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. Next, the gate insulator (2), the gate electrode (18) and the source
A drain or source (21), which is effectively a drain or source relative to the source or drain (14) and constitutes the lower electrode of the capacitor, and further comprises a capacitor insulator (22), An electrode (23) was provided.

Conventionally, an MISFET has a channel formation region in a lateral direction parallel to the upper surface of a semiconductor substrate, and a pair of source, drain (14) and drain or source are always symmetrically provided below both ends of a gate electrode. (21) is formed by forming the same plane on a semiconductor substrate. Further, in the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to constitute a one-bit memory), the gate electrode (1
8) is provided not only on the gate insulator (2) but also on the upper surface of the counter electrode (23) of the capacitor. This has self-alignment with one end of the source or drain (14) below one end of the gate electrode (18) and one end of the drain or source (21) as the other end of the gate electrode. Provided. The other end (18 '') of the gate electrode is made larger than the channel region (6) to compensate for variations in mask alignment accuracy.Poly II (polysilicon coating is applied to (23), (18) Process used). But even in such cases,
It is impossible to reduce the channel length to 1 μm or less due to the restrictions on the photo-etching process. In particular, because of the unevenness in the step portion of (18), shortening the channel length causes pattern breaks and the like. Was impossible. The present invention is characterized in that the gate electrode of the MIS FET is provided by positively utilizing the step, and the gate electrode is formed without extending over the opposing electrode of the capacitor forming the convex shape. I do.

[0004]

According to the present invention, the channel forming region below the gate electrode is made to allow a current to flow in the vertical direction, and the channel length is extremely small, 0.03 to 1 μm. An object of the present invention is to provide a ULSI element structure that can be manufactured from 16 Mbits to 16 Gbits by reducing the size of 1Tr / Cell in which capacitors are connected in series to about 1 μm □ to 10 μm □.

[0005]

According to the present invention, the channel forming region is formed in a vertical direction, that is, a vertical channel type.
The drain and drain are formed in the lateral direction to make it easier to connect with one electrode of the capacitor.
In providing T. That is, a convex single-crystal semiconductor region is provided on the main surface of the semiconductor substrate, and one of the source or drain of the MIS FET is connected to LDD (a drain having a relatively low impurity concentration, that is, a lightly-doped drain). And a side portion of the convex region is a vertical channel forming region, and the bottom of the semiconductor substrate is a drain or source having an LDD structure. The source or drain and the drain or source are formed. Means that the impurity concentration is 3 × 10 ¹⁶
To 5 × 10 ¹⁸ cm ^-3 of improving the drain breakdown voltage and a low concentration, i.e., with the LDD, co elevated regions - the Na portion is provided with a gate electrode of a rectangular or triangular.

The upper lateral portion of the gate electrode substantially coincides with the source or the drain, coincides with the end of the source or the drain, or is slightly larger on the source or the drain side, and has a second upper portion. The gate electrode is located below the impurity region to prevent the gate electrode from having an offset structure, and to allow margin (margin) in manufacturing.

The source or the drain has a second impurity region, and the drain or the source has a high impurity concentration of the first impurity region in ohmic contact with one electrode of a capacitor. In order to facilitate it, it is provided with a lateral surface. Then, a stack-type capacitor (stacked capacitor) is provided by serially connecting a capacitor in which a conductor, an insulator, and a conductor are electrically stacked through the first region.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 This embodiment is shown in FIG.
A 1Tr / Cell structure and a manufacturing process thereof will be described. In this example, a vertical channel type N-channel MISFET is provided as a pair using a convex region of a semiconductor substrate.

A semiconductor substrate such as a silicon single crystal semiconductor (1
00), P-type 10-500 Ωcm was selected. A convex region (35) was formed on the single crystal substrate by using a first photomask. For the fabrication, anisotropic etching of a silicon single crystal substrate may be formed using the photoresist (32) as a mask. It is important that the corner has a very sharp vertical surface at 90 ° to the upper surface of the substrate. The height of this projection is 0.
5 to 4 μm, for example, 1.5 μm.

A silicon nitride (33) having a masking effect on an oxidizing gas was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. After that, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask () to use the selective oxidation method, thereby forming FIG. 2A.

After doping a P-type impurity for forming a channel cut into the removed region, a field insulator (3) is buried to a thickness of 0.5 to 2 μm.

As shown in FIG. 2B, the silicon nitride film (33)
Then, a film (2) for forming a gate insulating film was formed on the semiconductor substrate (1) having the convex region (35). Doping As or phosphorus by ion implantation at a relatively low concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 from the vertical direction and at a depth of 3000 to 1 μm, for example, 5000 °, the semiconductor substrate ( N-type drain or source (5), (5 ') and source or drain
(4) is to be configured as an LDD (write-drain-drain).

Channel forming regions (6), (6 ') are formed on the side surfaces of the convex region, and ion implantation (38), (38') is performed in a lateral or oblique direction to control a threshold voltage there. )
Was doped with boron.

Since not only the substrate but also the insulating film (33) is damaged by these ion implantations, the whole is annealed to monocrystallize the semiconductor substrate (1) and the convex region (35). . The silicon oxide film (2) is removed and another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film (2).
It may be.

Next, as shown in FIG. 2C, a window for forming a source or a drain was formed in the gate insulating film (2) using a third photomask (). After sufficiently cleaning the surface of the insulating film, a low pressure gas phase method (LPCVD method) is applied on the substrate.
-Impurity of conductivity type, for example, N-type impurity (phosphorus)
There 1 to 10 × 10 ²⁰ de concentration of cm ^-3 - was formed to construct the de - flop silicon semiconductor film (7) to 0.5 to 2.5 [mu] m thickness on the gate electrode and the other directory. This impurity doping is not performed simultaneously with the film formation, but is performed by the following anisotropic etching to leave portions (8) and (8 ′) serving as gates,
After applying the conductive film (7), it may be doped by a diffusion method.

The conductive film 7 may be made of a metal or an intermetallic compound instead of silicon doped with impurities. Further, a multilayer film of a P ⁺ or N ⁺ type semiconductor and a metal or a metal compound, particularly Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ) may be used.

When the coating (7) is made of a compound or a mixture of WSi ₂ , MoSi ₂ or the like, silicon, tungsten and molybdenum, the coatings are formed by LPCVD, electron beam evaporation or reactive sputtering. 0.3 to 1.5 μm, especially 0.5 to 0.7 μm
It may be formed. Thus, FIG. 2 (C) was obtained.

Next, as shown in FIG. 2 (D), a photoresist (not shown) is formed on a region to be left as a part of the film on the upper surface.
For example, OMR-83 (manufactured by Tokyo Ohka) () was selectively coated, and then anisotropic etching was performed. For this etching, it is important to use an anisotropic etching method with very little or no side etch and taper etch, instead of an isotropic etching method using a conventionally used solution. Specifically 2.45GHz
The reactive gas for etching, for example, nitrogen fluoride (NF ₃ ) and carbon fluoride (CF ₄ ) is chemically activated by microwaves using, and the degree of vacuum is further reduced to 0.1 to 0.001 torr, particularly to 0.
A fluorine shower, which was made into a plasma in an atmosphere having a degree of vacuum of 005 to 0.01 torr, was caused to flow vertically from the upper surface of the substrate, a bias was applied to the substrate, and a low-temperature etching was performed to eliminate the side etch.

As a result, when the flat portion on which the photoresist is not formed is completely removed from the coating (7), the coating (8) on the side portion which is the corner of the convex region (3) is obtained. , (8 ')
A vertical rectangular or almost triangular gate electrode (1
8), (18 '). Using the lower end portion (46) of the gate electrode as a mask, the first impurity region having a high impurity concentration (corresponding to (15), (15 ') in FIG.
(47) was provided substantially in agreement. Furthermore, the contact (11) for the electrode of the first impurity region (15) of the MIS FET (19) and its contact
In this embodiment, the lead (12) could be left as an electrode lead in the N ⁺ type. The gate electrodes (18) and (18 ') do not exist over the upper surface of the convex region (35), and the width thereof is not the width determined by photolithography.
And the degree of anisotropic etching.

It is preferable that the upper end (48) of the rectangular or triangular gate electrode substantially coincides with the end (4) of the source or drain, that is, is located at the same degree or higher, that is, approximately coincides with the upper end. The width between (44) and (45) is extremely important as a margin in manufacturing (margin).

The channel length of the MISFET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). The gate electrodes (18) and (18 ') have an LDD source and drain (4) as a margin for the height, so that even if the anisotropic etching is made a little too much, the gate electrode can be formed. It has the feature that it does not enter the offset state. This rectangular or nearly triangular gate electrode (1
8) and (18 ′) have a width at the lower end of 0.05 to 1.5 μm, typically 0.2 to 1.0 μm, and further have a channel forming region (6),
Cover this area in the lateral direction of (6 ') and increase its height from 0.2 to 2.
5 μm, typically 0.3 to 0.8 μm. In particular, this height is a function of the film thickness of the film (7), its etching time by plasma etching, and its intensity. It could be provided as a very short channel of μm (hereinafter referred to as microchannel).

In FIG. 2D, rectangular or substantially triangular gate electrodes (18) and (18 ') have a width at the lower end of 0.1 to 1 μm.
m, but the layer can be extended as a lead over the field insulator and
The width of the lead may be as wide as 1 to 10 μm and may be connected to the electrode lead of another MIS FET provided on the same substrate, or may be electrically connected to other capacitors, resistors, etc. Needless to say.

Next, as shown in FIG. 2D, the ion implantation method has a higher concentration than the source or drain (4) and the drain or source (5), (5 '). Arsenic, which is an N-type impurity, is implanted at an accelerating voltage of 30 to 150 KeV and 1 × 10 ¹⁹ to 1 × 10
First impurity regions (15), (15 ') with an impurity concentration of about ²¹ cm ^-3
The end (47) of the rectangular or triangular gate electrode (1
8) and (18 ') were formed on the bottom of the substrate so as to substantially coincide with the position of the lower end (46). In addition, a second impurity region (14) is simultaneously formed on the N-type drain or source (4) above the convex region (35), and this is brought into ohmic contact with another electrode. Made it easier.

Then, the first and second impurity regions are formed.
(15), (15 ') and (14) show that the source / drain (4) and drain / source
This can be prevented by the presence of (5), (5 ′). In particular, the lateral diffusion of the first impurity regions (15) and (15 ') is caused by the gate electrode (1).
8), The width of the lower end of (18 ') can be provided as a margin (self-line) as a margin.

The electrode leads (11), (1) of the MIS FET (10)
2) and the first impurity region acting as a drain or source (15) are connected, and another first impurity region (15 ') and another electrode lead can be brought into ohmic contact. Another MIS FE
The lower electrode (21 ') of the capacitor (10') is connected to the first impurity region 15 ') of T (10') via a contact (13).

On top of this, a dielectric (22 ') and an upper electrode (2
3 ′) was provided to constitute 1Tr / Cell. The dielectric (22 ') was formed as a single layer or a multilayer of tantalum oxide, titanium oxide, barium titanate, and silicon oxide by a sputtering method. Thus, 1Tr / Cell of the present invention was obtained.

Further, after a lead in a direction perpendicular to the leads (19) and (12) is formed of a polyimide-based insulator such as PIQ, a metal on the upper surface thereof is selected by photolithography. After removal, a multilayer wiring can be formed.

FIG. 2E is a vertical sectional view of the MIS FET of FIG. 2D.
(10), (10 ′) and the capacitor (20 ′) are symbolized and corresponded to the numbers.

Embodiment 2 FIG. 3 shows another embodiment to which the present invention is applied.

FIG. 3A shows two MIS FEs using the first embodiment.
T (10), (10 ') and two capacitors are respectively connected in series, and two 1Tr / Cells are provided in pairs. That is, the convex region (35) has channel forming regions (6) and (6 '), on which the source or drain (4) and the high-concentration second
Impurity region (14). A field insulator (3) is provided around the bottom of the semiconductor substrate (1), and a drain or a source is provided outside the first impurity regions (15) and (15 ').
(5), (5 '), gate electrode (18), (18'), gate insulating film (2),
Two MIS FETs (10) and (10 ') were constructed as (2'). Connected to the first region (15), (15 ') of N ⁺ to make this ohmic contact
(13), (13 ') and the lower electrodes (2) of the capacitors (20), (20')
1), (21 '), dielectric (22), (22'), and furthermore, the upper electrode (2
3) and (23 ') were provided, thereby forming capacitors (20) and (20').

In FIG. 3, (14) is a bit line, and (1)
8), (18 ') are part of a memory system having a structure in which two 1Tr / Cells are paired with word lines. With such a structure, the convex region (35) can be used in common for the two MIS FETs (10) and (10 '), and the dielectrics (22) and (22') are different from the gate insulating film. The stacked memory cell is characterized by using a material having a different high dielectric constant, for example, tantalum oxide, titanium oxide, silicon nitride, barium titanate, or a multilayer film thereof. In this embodiment, the outer periphery of the gate electrodes (18) and (18 ') is the oxide interlayer insulator (1).
7), but the thickness is 0.1 to 1.0 μm
And the first impurity regions (15) and (15 ') and the capacitor (2
The connection with the lower electrodes (21) and (21 ') of (0) and (20') formed electrodes (contacts) by selective growth (13) and (13 ') of tungsten. For this reason, the lower electrodes (21) and (21 ') are made of tungsten silicide.

As described above, when the MISFET of the present invention is used, a contact can be obtained with a sufficient area by connecting to the first impurity region. That is, the first impurity regions (15) and (15 ') may be formed with the mask alignment accuracy when performing the hole making for the electrode. The channel length could be made precisely as shown in Example 1 irrespective of the contact formation region and without increasing the size of the MIS FET as viewed from above the substrate.

An interlayer insulator such as polyimide may be formed, and a third conductor wiring (9) may be formed on the upper surface thereof.

The cell area was extremely small and could be formed at high density. Example 1 was used for manufacturing steps not shown in this example.

[Embodiment 3] FIG. 3B is a longitudinal sectional view of this embodiment. As is apparent from the drawing, a single-crystal semiconductor (35) is provided on the surface of the semiconductor substrate in a convex shape on the surface of the semiconductor substrate, and gate insulating films (2), (2) ') And gate electrodes (18), (1
8 ') are formed as a pair. LDD with low impurity concentration
The drain or source (5), (5 '), source or drain (4) of the structure is provided to precisely control the channel length (6), (6'). Using a part of the gate electrode such as silicon as a mask, high-concentration first impurity regions (15) and (15 ') are provided by self-alignment, and the second high-impurity concentration The region (14) was provided by an ion implantation method.
Thus, the μ-channel MIS FETs (10) and (10 ′) are provided in a structure forming two pairs.

Next, the contact openings (9) and (9 ') provided in the first impurity regions (15) and (15') are provided in the same manner as in the first embodiment. Lower body electrode (2
0) and (20 ') are provided, for example, by forming doped silicon to a thickness of 0.1 to 1 μm. On this upper surface, tantalum oxide films (22) and (22 ') were formed to a thickness of 100 to 500 mm by sputtering. Thereafter, opposing electrodes (23), (23) ') were provided on the surface by metal or semiconductor, and after photo-etching, the capacitors (20), (20') were obtained.

Thus, the upper electrodes (23) and (23 ') of the capacitors (20) and (20') and the dielectrics (22) and (22 ') and the lower electrodes
(21) and (21 ') could be made as stacked memory cells. In addition, this capacitor is used as a field insulating film.
(3) Upper or convex region (35) and gate electrodes (18), (18 ')
It could be provided over the upper part, and the density of the cell area could be increased. A multilayer wiring (24) is provided as a word line on the interlayer insulating film (17) through a contact to the second impurity region (14), and the gate electrodes (18) and (18 ') are used as bit lines. The vertical channel type in self-alignment,
The formation of a pair of source and drain laterally arranged MISFETs was extremely effective in reducing the size, increasing the density and improving the reliability.

In this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24) and the word line is the gate electrode. (18) and (18 ') could be configured as a part of a 1Tr / cell memory system that makes a pair.

The above embodiments 2 and 3 are all 1Tr / Cell DRAMs.
(Dynamic Memory).
However, the process of the present invention can similarly form a μ-channel MIS FET such as an amplifier or an inverter on the other part of the same substrate, having the same shape.
This has been very convenient for making memory systems or logic systems.

The lower electrode, the upper electrode, and the first region of the capacitor may all have improved reliability as a silicon family formed of the same main component as the substrate. In addition, since these are integrated N-channel MIS FETs, they have a plurality of convex regions on the same substrate, and a part of them is used as a P-channel MIS FET to form a complementary (complementary) integrated circuit. Is valid.

In the above three embodiments, the material constituting the first region and the material constituting the vertical rectangular or substantially triangular gate electrode (18) have a P ⁺ or N ⁺ conductivity type. The description is centered on a material having the same main component as that of the substrate doped with impurities, for example, silicon.

However, they may be a mixture or a compound (MoSi ₂ , WSi ₂ ) of silicon and Mo, W, or may be an intrinsic, P ⁺ -type or N ⁺ -type semiconductor having a multi-layer structure. Needless to say, a multilayer structure of a semiconductor and Mo, W, platinum or a compound thereof may be provided.

In the present invention, single-crystal silicon is mainly used for the semiconductor substrate. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous or semi-amorphous semiconductor.

The channel forming region uses surface diffusion.
Instead of the MIS FET, it may be an embossed channel type. Further, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[0046]

As is clear from the above embodiments, the present invention is not a conventional structure in which a source and a drain having a pair of structures are arranged in a horizontal direction with gate electrodes separated from each other in a lateral direction. The drain is easy to make contact with the outside, and a capacitor for forming a 1Tr / Cell is formed in a stacked type by connecting to the drain. Further, the ease of manufacture and the increase in the capacity of the capacitor could be achieved by reducing the cell area constituting one bit.

The threshold voltage of the channel forming region has a structure in which an impurity such as boron is doped on the upper part of the semiconductor obliquely or laterally, and has a structural characteristic, and a threshold voltage of 0.1 to 1 μm. It has a great feature that an extremely short channel (μ channel) MISFET having a frequency response speed of 1 to 10 GHz depending on the channel length can be implemented without using a technique such as electron beam exposure as an absolute requirement.

[Brief description of the drawings]

FIG. 1 shows an example of a longitudinal sectional view of a conventionally known MISFET.

FIG. 2 is an example of a longitudinal sectional view showing a manufacturing process and a structure according to an embodiment of the present invention.

FIG. 3 is an example of a longitudinal sectional view of another embodiment of the present invention in which 1Tr / Cell memories are provided as a pair.

[Description of Signs] 1... Semiconductor substrate 2... Projecting region 3... Field insulator 5 5 ′ Drain or source 4. .Source or drain 15, 15 ': first impurity region 14: second impurity region 18, 18': gate electrode 10, 10 ': insulating gate type field effect Transistor (MIS F
ET) 20,20 '・ ・ ・ Capacitor ・ ・ ・ ・ ・ ・ Patterning processing by photomask

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/336 H01L 27/108 H01L 29/78

Claims (4)

(57) [Claims] 1. A convex region is formed on a semiconductor substrate of one conductivity type, a gate insulating film is formed on a side surface of the convex region and a bottom of the semiconductor substrate, and an upper portion of the convex region and the gate insulating film are formed. Forming a low-concentration impurity region by adding impurities to the bottom of the semiconductor substrate; forming a channel formation region by adding impurities obliquely to the side surface of the semiconductor substrate; forming a film serving as a gate electrode; By performing anisotropic etching, a gate electrode having a rectangular or triangular shape is formed at a corner of the convex region, and an impurity is added to the semiconductor substrate by using the gate electrode as a mask to form the convex region. A method of manufacturing a vertical channel type insulated gate type field effect semiconductor device, wherein a high concentration impurity region is formed at an upper portion and a bottom portion of the semiconductor substrate. 2. A convex region is formed on a semiconductor substrate of one conductivity type, a gate insulating film is formed on a side surface of the convex region and a bottom portion of the semiconductor substrate, and an upper portion of the convex region and the gate insulating film are formed. Forming a low-concentration impurity region by adding impurities to the bottom of the semiconductor substrate; forming a channel formation region by adding impurities obliquely to the side surface of the semiconductor substrate; forming a film serving as a gate electrode; Anisotropically etching, a gate having a rectangular or triangular shape at a corner portion of the convex region, and an upper end approximately corresponding to a lower end of the low-concentration impurity region located above the convex region. Forming electrodes,
A vertical channel type insulated gate type field effect semiconductor, wherein a high concentration impurity region is formed at an upper portion of the convex region and at a bottom portion of the semiconductor substrate by adding an impurity to the semiconductor substrate using the gate electrode as a mask. Method for manufacturing the device. 3. The method for manufacturing a vertical channel type insulated gate field effect semiconductor device according to claim 1, wherein the channel length of the channel formation region is 0.03 to 1 μm. 4. The method according to claim 1, wherein
A method for manufacturing a vertical channel type insulated gate field effect semiconductor device, comprising using a single crystal semiconductor substrate as the semiconductor substrate.