JPH0758792B2 - Method for manufacturing vertical channel insulating gate type field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field of application" The present invention relates to a semiconductor integrated circuit, and more particularly, to an insulating gate type field effect semiconductor device for an ultra-high density integrated circuit (ULSI) of 16M to 16G bit level. Regarding providing a method.

The present invention relates to a semiconductor device, particularly a vertical channel MIS type (insulating gate type) field effect semiconductor device (FET) having a micro channel type in which a current flows in the vertical direction (hereinafter, the channel length is 0.03 to 1 μm, which is 1 μm or less). μ channel MIS FE
A method of manufacturing a semiconductor device in which a self-alignment (self-alignment) process is applied to a microchannel as described above, and a capacitor is connected to form a composite, for example. .

In the present invention, a rectangular convex region is provided by performing anisotropic etching, and impurities are added to a side surface of the convex region from an oblique direction or a lateral direction, for example, by an ion implantation method, and a channel formation region is formed. The present invention relates to a method of forming a pair of impurity regions which form a source or a drain and a drain or a source using a gate electrode as a mask.

The present invention further relates to a manufacturing method in which the threshold voltage is controlled in the channel formation region before manufacturing the gate electrode.

The present invention further relates to a method of manufacturing a vertical channel type MIS FET which prevents generation of a parasitic channel on the side surface of another convex region before or after manufacturing the gate electrode.

“Prior Art” Conventionally, a structure of a method for manufacturing a MIS FET or a capacitor connected in series thereto has a structure as shown in FIG. 1 in which one surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. The gate insulator (2), the gate electrode (18) and the source or drain (4), the drain or source (5) are doped with impurities by vertical ion implantation from above with the gate electrode (18) as a mask. It is formed as a so-called LDD (drain having a relatively low impurity concentration, that is, a light-doped drain) while forming a self-aligned structure. Around the gate electrode (18) side, rectangular or triangular portions (38), (3
8 ') is formed, and using the end portion as a mask, the first impurity region (15) and the second impurity region (14) having a high impurity concentration are planarly formed on the outside thereof, and the MIS FET (10) is formed. Made me composed. Further, the lower electrode (21), the derivative (22), and the upper electrode (23) are provided as the capacitor (20) in connection with the first impurity region (15). As you can see, MIS FET (1
0) and the capacitor (20) were formed on the semiconductor substrate in the same plane. In the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to form a 1-bit memory), the cell area is large due to this planar structure, and there is a limit to high-density integration. It was

LDDs (4) and (5) are located on the left and right of the gate electrode (18).
The rectangular or triangular portions (38) and (38 ') are made of an insulating material as an auxiliary means for producing the. The present invention relates to a method of manufacturing a structure in which the rectangular or triangular portion is positively provided as a conductor or semiconductor gate electrode itself, not as an insulator.

"Object of the Invention" In the present invention, a rectangular convex region is provided, and one or two side surfaces of this region are used as a channel formation region. That is, the current is made to flow in the vertical direction, and the channel length is 0.03 to 1
It is to provide an element structure for ULSI which can be made up to 16M to 16 Gbits by making the size of one MIS FET as small as about 1 μm □ to 10 μ □ while making the size extremely small to 1 μm. Another object of the present invention is to provide an inverter structure by combining these MIS FETs and a memory cell structure connected to other elements such as capacitors.

[Structure of the Invention] In the present invention, a rectangular convex region is provided on a single crystal semiconductor substrate. This convex (100) plane or its vicinity ((10
Each of the four side faces having (0) face or its vicinity, that is, a deviation within ± 10 ° from the (100) face is hereinafter referred to simply as (100) face, is simultaneously defined as (100) face, and two channels are formed on this side face. A region is used and a current is passed in the vertical direction, that is, a vertical channel type.

In the present invention, the source and drain of the MIS FET are formed in the lateral direction in order to facilitate the formation of electrodes in the subsequent steps, thereby providing an asymmetric MIS FET. That is, a rectangular convex single crystal semiconductor region is provided on one main surface of the semiconductor substrate. Using the rectangular or triangular gate electrode formed in this convex region as a mask, the end of the gate electrode is formed into a source or drain and the drain or the end of the source (channel forming region and It was used as the standard for manufacturing the contact part). That is, one source or drain of the MIS FET is formed above it, the lower side of the gate electrode of this convex region is formed as a vertical channel formation region, and the drain or source is formed at the bottom of the semiconductor substrate. To make. The source or drain and the drain or source have an impurity concentration of 3 × 10 5 formed by, for example, an ion implantation method.
^While adding ^{17 to} 5 × 10 ²⁰ cm ^-3 , the addition is carried out obliquely or laterally. Then, the region with a higher concentration of impurities is not the oblique surface of the convex region or the bottom of the semiconductor substrate, but the inside of the semiconductor deeper than that. As a result, it is possible to prevent injection of hot carriers into the gate insulator.

It has a source or drain end that is roughly aligned with the upper end of the gate electrode, and the inside of the gate electrode is slightly overhanging on the channel formation region side to prevent the gate electrode from having an offset structure and to be manufactured. Give a margin.

Impurities were laterally or obliquely added to this rectangular convex region by, for example, an ion implantation method to control the threshold voltage of the channel formation region and form a buried channel.

The impurity concentration varies depending on the interface state density, but in the T-channel MIS FET, the threshold voltage is within ± 1V, and normally off is +0.1 to + 1.0V.
To make it normally-on, it was set to -0.1 to -1.0V. It has the opposite sign in the P-channel MIS FET.

On the side where the channel is not formed, the generation of the parasitic channel is prevented in the vertical direction so that a minute leak due to the generation of the parasitic channel does not flow. In order to prevent this parasitic channel, boron is used in the N-channel MIS FET at a concentration lower than the impurity concentration of the source or drain for LDD and higher than the impurity concentration of the substrate. Generally, it is set to 1 × 10 ¹⁶ to 2 × 10 ¹⁸ cm ^-3 .

Source or drain and drain or source
The second impurity region and the first impurity region having a high impurity concentration are provided with a flat surface so that a contact hole can be finely and accurately opened in order to facilitate ohmic contact with an external electrode. .

On the contrary, even if a contact hole is to be formed on the side surface, exposure to ultraviolet light for photoetching is generally performed from the upper side to the lower side in the manufacturing process, so it is not possible to form a contact hole having a size of 0.1 to 0.5 μm □ Nearly impossible.

The present invention eliminates this drawback.

For this reason, the semiconductor device of the present invention achieves high densification for constructing the ULSI by positively providing it in the height direction instead of reducing the area occupied by the substrate of the conventional lateral MIS FET by scaling. It is an object.

Examples of the present invention will be described below with reference to the drawings.

Example 1 This example shows the manufacturing process thereof in FIG.

Using the rectangular convex region (35) of the single crystal semiconductor substrate, two vertical channel N-channel MIS FETs are paired (10), (1
0 ').

2 (A) to 2 (D) are vertical sectional views thereof, and FIG. 2 (E) is a plan view thereof. AA 'in FIG. 2 (E)
2 corresponds to FIGS. 2 (A) to (D).

Single crystal semiconductor substrate, such as silicon single crystal semiconductor (10
0) surface, P type 10 to 500 Ωcm was selected. For this semiconductor substrate, using a first photomask (-indicates a photolithography process using the photomask), as shown in FIGS. 2A and 2E, a rectangular convex shape when viewed from above. Area (35) was formed. Anisotropic etching of the silicon single crystal substrate may be performed for its production. It is important that this corner has a very sharp vertical surface at 90 ° to the top surface of the substrate. The height of this convex area (35) is 0.5-4 μ
m, for example, 1.5 μm.

Then, the convex area (35) having a rectangle is shown in FIG. 2 (E).
As shown in, the channel formation region is defined by the (100) plane (<100>
Direction (40)), and the parasitic channel prevention surface is also the (010) surface (<010> direction (40 ')).

And on all sides of them a fixed charge density (11
It can be reduced to about 1/2 of that of (0) and (111) crystal planes.

Silicon nitride (33) having a masking action against oxidizing gas was formed to a thickness of about 0.1 μm. The coating film having a masking action against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. Then, as shown in FIG. 2 (A), the silicon nitride was partially removed by the second photomask ().

After the P-type impurity for forming a channel cut is doped into the removed region, a field insulator (3) is added to 0.5-2.
It is embedded in a thickness of μm to obtain the state of FIG.

As shown in FIG. 2B, the silicon nitride film (33) is removed to form a film (2) for forming a gate insulating film on the semiconductor substrate (1) having the convex region (35). did.

The channel forming regions (6) and (6 ') were formed on at least the side faces of the rectangular convex region by means such as ion implantation before or after the formation of the gate insulating film (2). That is, since the channel forming regions (6) and (6 ') are the case of the N channel type MIS FET in this embodiment, the threshold voltage is controlled, and normally off for the enhancement type MIS FET. +0.1 to + 0.1V, for example +0.5
For V, and for the depletion type MIS FET, the normally-on -0.1 to -1.0 V, for example, -0.5 V was achieved by controlling the dose amount. These were used as channel formation regions, and one or both of the channel formation regions (6) and (6 ') were automatically formed using a photomask. Two or three types of impurities may be added twice as a filling channel type. These are the convex regions (35) (6),
Impurities were positively added to the side surface on the (6 ') side. For example, ion implantation (3
8) and (38 ') were doped with boron or boron and arsenic.

In the rectangular convex region (35) where the channel is not formed ((36) and (36 ') in FIG. 2E), parasitic channels are easily generated, and the source or drain (4) and the drain (4) Alternatively, boron was added to the source (5), (5 ') in a higher concentration than that of the substrate, that is, the convex region so that a minute leak current was not generated, and a channel was cut so that the off state was always achieved. . That is, the ion implantation was accomplished from the oblique or lateral direction with respect to the plane on the substrate.

These ion implantations not only damage the substrate but also the insulating film (33) or (2), so that they are annealed by heat or intense light to remove the semiconductor substrate (1) and the convex region (35). Single crystallized.

This ion implantation process may be performed in FIG. 2 (A) or in FIG. 2 (B).

The silicon oxide film (2) may be removed to form another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide, or a composite film thereof with a thickness of 100 to 500 Å as the gate insulating film (2). Good.

Next, as shown in FIG. 2B, this gate insulating film (2)
A window for forming a source or drain electrode (contact) was formed by using a third photomask (). After sufficiently cleaning the surface of the insulating film, one conductivity type impurities such as N type impurities (phosphorus) of 1 to 10 × 10 ²⁰ cm ⁻³ are formed on the substrate by the low pressure vapor phase method (LPCVD method). 0.5-2.5 μm thick silicon semiconductor (silicon) coating (7)
To form a gate electrode and other leads with a thickness of 100 nm. The doping of the impurities is not performed at the same time as the film formation, but the anisotropic etching is performed next to the film (7) to leave the portions (8) and (8 ′) to be the gates, and then the diffusion method or You may perform by the injection method.

The film (7) may be a conductor such as a metal or an intermetallic compound, instead of the impurity-doped silicon semiconductor. Further, it may be a multilayer film of a P ⁺ or N ⁺ type semiconductor and a metal or a metal compound, especially Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ).

Thus, FIG. 2 (B) was obtained.

Then, as shown in FIG. 2C, a photoresist (eg, OM) is formed on the upper surface of the region to be left as a part of the film.
R-83 manufactured by Tokyo Ohka)
After that, anisotropic etching was performed. With respect to this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, instead of an isotropic etching method using a conventionally used solution. Specifically, a reactive gas for etching, such as nitrogen fluoride (NF ₃ ) and carbon fluoride (CF ₄ ) is chemically activated by microwave using 2.45 GHz, and the degree of vacuum is 0.1 to 0.001. torr especially 0.005
We tried to eliminate the side etch as low temperature etching by flowing a fluorine shower made into plasma in an atmosphere with a vacuum degree of ~ 0.01 torr to the vertical direction from the upper surface of the substrate and applying a bias to the substrate.

As a result, when the flat surface of the coating film (7) on which the photoresist is not formed is completely removed, the convex region (3
Films (8), (8 ') on the side surface which is the corner of 5)
Has a larger effective thickness when viewed from above, so that the vertical rectangular or triangular gate electrodes (18), (18 ') are formed around the sides.
Was left as. Further, the contact (11) and its lead (12) of the first impurity region (corresponding to (15) in FIG. 2D) of the drain or source (5), (5 ').
Was able to remain as an electrode lead with N ⁺ type in this example. The gate electrodes (18) and (18 ') do not exist over the upper surface of the convex region (35), and the width thereof is not the width determined by photolithography, but the film (7).
The thickness can be determined by the thickness of the side surface and the degree of anisotropic etching.

Then, the whole of these is oxidized to form a silicon oxide insulating film (47) in the convex region, the bottom of the semiconductor substrate and the gate electrode (1
8), (18 ') was formed to a thickness of 300-2000Å.

Next, the rectangular or triangular gate electrodes (18), (1
As shown in (37) and (37 ') using 8') as a mask, impurities are added obliquely. When the in-implantation method is used, arsenic is added at an acceleration voltage of 30 to 100 KeV to a concentration of 0.5 to 5 × 10 ¹⁵ cm ^−2, for example, 1 × 10 ¹⁵ cm ⁻² because it is an N-channel type. Then, using the gate electrodes (18), (18 ') or the end (44) of the insulating film (47) thereon as a mask, the upper part of the convex region (35) has a source or drain (4). The end portion (44 ') substantially coincides with the end portion (44) of the gate electrode, and the inside (44 ") of the end portion (44') is closer to the drain or drain when viewed from the channel forming region (6 '). Formed near the source, thus forming the source or drain (4).

On the other hand, the end (48 ') of the drain or the source (5') is formed so as to substantially coincide with the end (48) of the other gate electrode (18 '), and the end (48') is formed deeper than that position (in the source or the drain). Close to the inside of the drain or source (48 ″)
Is formed.

Thus, the source or drain (4), drain or source (5), (5 ') is the gate electrode (18), (18').
The position is determined by self-alignment (self-alignment) by the end portion of, and the positioning is performed by ion implantation from an oblique direction.

And the gate electrode (18 ') is as shown in FIG. 2 (E).
Extend it as a lead (38 ') and connect it to the other gate electrode (1
8) connects the lead (12) to the contact (11).

In FIG. 2 (D), first impurity regions (15) and (15 ') and a second impurity region (14) are formed in order to form a region having a high impurity concentration from above, and ohmic contact is made. Good. However, these impurity regions change the accelerating voltage when forming the source or drain (4), the drain or source (5), (5 '), so that the high accelerating voltage gives a low dose and the strong accelerating voltage gives a high dose. Add to dose region, eg 10
It can be formed at a time by changing doping to 1 × 10 ¹⁴ cm ⁻² at 0 KeV, 3 × 10 ¹⁴ cm ⁻² at 50 KeV, and 2 × 10 ¹⁴ cm ^{−2 at} 30 KeV.

In FIG. 2 (C), the rectangular or substantially triangular gate electrodes (18) and (18 ') have a bottom width of 0.1 to 1 μm.
However, the layer is extended as a lead (38), (38 ') on the field insulator according to the need of the design, and the width of the lead is set as wide as 1 to 10 μm. It goes without saying that it may be connected to the electrode lead of another MIS FET provided on the same substrate, or may be electrically connected to another capacitor, resistor or the like.

In the drawing, selective growth of tungsten (24), (13) is performed, and aluminum leads (24 '), (12'), (3)
8 ″) was formed and multilayer wiring was performed.

In FIGS. 2D and 2E, an inverter, that is, a power source side (38 ″), a load (10), outputs (24), (24 ′), a driver (10 ′), a ground side (12), (). After that, an interlayer insulating film is formed on the entire surface, the output is connected to the second impurity region (14), and the current is connected to the electrode (12 ') by multilayer wiring. do it.

The channel length as a MIS FET is the end (44) of the source or drain (4), or (44 ″) and the end (48 ′) or (48 ″) of the drain or source (5), (5 ′).
You can decide by the difference.

Thus, the source and drain could be a vertical channel type so-called vertical and horizontal type MIS FET while facilitating contact with the outside on the plane above the convex region and the bottom surface of the substrate. Therefore, it is easy to form electrodes (contacts) for the source and drain, and the channel length is 0.
It is as small as 1 to 1 μm, and its length can be controlled more precisely for self-alignment process by adding impurities from diagonal direction.

As is apparent from the above-described embodiments, the present invention provides the vertical rectangular or triangular gate electrodes (18) and (18 ') adjacent to the convex region to increase the mechanical strength and to form the channel forming region. The (100) plane was used for (6) and (6 ') to reduce the interface state (due to the generation of positive charges due to the presence of dangling bonds of silicon).

In addition, the other side surface of the rectangular convex region ((3) in FIG.
In (6) and (36 ')), the side surface was also (100) plane so that the generation of positive fixed charge was minimized so that the parasitic channel would not be generated. Further, boron was added thereto as shown in (36) and (36 ') of FIG. 2 (E) to form a channel cut.

Thus, it is possible to fabricate a vertical-horizontal microchannel (μ-channel) type MIS FET having a precisely controlled channel length and reducing the area of the entire transistor substrate.

In FIG. 1, two MIS FETs in a rectangular convex region are formed in an N-channel type. However, another MIS FET is formed in a P-channel type in another portion separated by a field insulator. The use of LSI or VLSI as the MIS structure (complementary structure) can further promote the present invention.

[Embodiment 2] FIG. 3A shows another embodiment to which the present invention is applied. The corresponding electric circuit is shown in FIG.

FIG. 3 (A) shows two MIS FETs (1
0), (10 ') and two capacitors (10), (10') are respectively connected in series, and two 1Tr / Cells are provided as a pair. That is, the convex region (35) has the channel forming regions (6) and (6 '), and the source or drain (4) and the high-concentration second impurity region (14) are formed on the upper portion thereof.
Have. Further, a field insulator (3) is provided on the periphery of the bottom of the semiconductor substrate (1), and drains or sources (5), (5) are provided on the first impurity regions (15), (15 ') and outside thereof. ′), Gate electrodes (18), (18 ′), gate insulating films (2), (2 ′) as two MIS FETs (1
0) and (10 ') are constructed. Make this ohmic contact N ⁺
(11), (11 ') connected to the first area (15), (15') of
Then, the lower electrodes (21) of the capacitors (20), (20 '),
(21 '), dielectrics (22), (22'), and electrodes (23), (23 ') provided on the upper side of the dielectrics, thereby forming capacitors (20), (20').

In FIG. 3A, (14) is a bit line, and (1)
8) and (18 ') are word lines to form a memory system having a structure in which two 1Tr / Cells are paired. With this structure, the convex region (35) is divided into two MIS FETs (10), (1
0 ') can be shared, and dielectrics (22), (2
2 ') can be a material having a high dielectric constant different from that of the gate insulating film, for example, tantalum oxide, titanium oxide, silicon nitride, barium titanate. It also has a feature of a stacked memory cell in which these dielectrics and electrodes are stacked on each other to increase the overall capacitance. In this embodiment, the outer periphery of the gate electrodes (18) and (18 ') is insulated by the oxide interlayer insulator (17), but the thickness is 0.1 to 1.0 .mu.m. The connection between the impurity regions (15) and (15 ') of the capacitor and the lower electrodes (21) and (21') of the capacitors (20) and (20 ') depends on the selective growth of tungsten (13) and (13'). An electrode (contact) was formed. Therefore, the lower electrodes (21) and (21 ') were made of tungsten silicide.

As described above, when the MIS FET of the present invention is used, the contact can be made constant by connecting it to the drain or source or the first impurity region even if the depth of focus of the stepper is shallow, thereby preventing precision addition due to defocus. it can. And it can be obtained with a sufficient area margin. That is, the first impurity regions (15) and (15 ') may be formed within the range of the mask alignment accuracy when the holes for the electrodes are formed. If the accuracy is good, the area required as the drain or the source can be reduced. The channel length could be precisely produced as shown in Example 1 regardless of the contact formation region and without increasing the size of the MIS FET viewed from the substrate.

An interlayer insulating material such as polyimide may be formed, and the third conductor wiring may be formed on the upper surface thereof.

The cell area could be made extremely small and high density. Example 1 was used for manufacturing steps not shown in this example.

[Embodiment 3] A longitudinal sectional view of this embodiment is shown in FIG. 3 (B). FIG. 3C shows a circuit diagram corresponding to another embodiment of the memory cell.

As is clear from the drawing, a convex region (35) is provided on the semiconductor substrate surface, and gate insulating films (2) and (2 ') are provided at the corners around the side and the substrate bottom. Further, the gate electrodes (18) and (18 ') are formed in a pair. Drains or sources (5) and (5 ') and sources or drains (4) were formed by ion implantation using a part of the gate electrode such as silicon as a mask. Furthermore, in order to form the channel as a recessed channel type, the boron-doped (46), (46 '), arsenic-doped recessed channels (6), (6') have their channel lengths (6), (6 '). It is provided by the self-alignment method for precise control. Thus μ channel MIS FET (1
0) and (10 ') are provided in a structure that forms two pairs.

Next, the contact openings (9) and (9 ') provided in the first impurity regions (15) and (15') are provided in the same manner as in the first embodiment. The side electrodes (20) and (20 ') are made of, for example, doped silicon of 0.1 to
It was formed to have a thickness of 1 μm. Tantalum oxide films (22) and (22 ') are deposited on the upper surface by sputtering to 100-500Å
Formed to a thickness of. Alternatively, silicon nitride or silicon oxide shown in the second embodiment may be used. They were made by nitriding or oxidizing the lower electrode. After this, the counter electrode (23),
(23) ′) is provided by a metal or a semiconductor and is photo-etched to obtain capacitors (20) and (20 ′).

Thus, the upper electrodes (23) and (23 ') of the capacitors (20) and (20') and the dielectrics (22) and (22 ') and the lower electrodes (21) and (21') are stacked. It could be made as a (stacked) memory cell. In addition, this capacitor can be provided on the field insulating film (3) or over the convex region (35) and the gate electrodes (18), (18 '), and when viewed from the semiconductor substrate as a whole, it looks as if it is a contact part. The cell area could be made higher so that it looks like a capacitor. The multilayer wiring (24 ') is provided as a word line on the interlayer insulating film (17) through the contact (24) to the second impurity region (14), and the gate electrodes (18) and (18') are used as bit lines. By using the MIS FETs in vertical channel type, source and drain laterally arranged type in pairs in a self-aligning manner, it was effective for miniaturization, high density and improvement of reliability.

Also in this embodiment, as in the second embodiment, a material having a high dielectric constant such as tantalum oxide can be used as the material of the dielectric, and the bit line is the region (24 ') and the word line is the gate electrode (1).
It could be configured as a part of a 1Tr / cell memory system that makes a pair with 8) and (18 ').

Since these are integrated N-channel MIS FETs, they have a plurality of convex regions on the same substrate, and some of them are P-channel MIS FETs to form complementary (complementary) integrated circuits. Is valid.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to form a floating gate type nonvolatile memory.

In the above three embodiments, the material forming the first region and the vertical rectangular or substantially triangular gate electrode (1
The material constituting 8) is mainly composed of a material having the same main component as that of a substrate doped with an impurity having a P ⁺ or N ⁺ type conductivity, such as silicon.

However, they may be a mixture or compound (MoSi ₂ , WSi ₂ , TiSi ₂ ) of silicon and Mo, W, Ti, or have a multilayer structure of an intrinsic, P ⁺ -type or N ⁺ -type semiconductor, It goes without saying that a semiconductor such as silicon and a multi-layer structure of Mo, W, platinum or a compound thereof may be provided.

In the present invention, the semiconductor substrate is mainly made of single crystal silicon. However, even with compound semiconductors such as GaAs and InP,
Needless to say, it may be a polycrystalline, amorphous or semi-amorphous semiconductor.

The channel formation region may be a buried channel type instead of the MIS FET using surface diffusion. Alternatively, a method using a majority carrier may be used. These are based on the method of controlling the structure of the channel portion under the gate insulating film.

[Effect] As is apparent from the above embodiments, according to the present invention, impurities are added obliquely or laterally to form the channel length by the gate electrode in the source or drain and the drain or the source in a self-aligned manner. With control, the source and drain could be formed. Then, the gate electrode has a structure in which the side portion of the gate electrode is in contact with the convex-shaped first region so as to be mechanically reinforced so as to achieve high reliability. The threshold voltage of the channel formation region has a structure in which impurities such as boron are provided above the semiconductor obliquely or laterally, and its structural characteristics, and the frequency response due to the channel length of 0.1 to 1 μm. It has a great feature that an extremely short channel (μ channel) MIS FET having a speed of 1 to 10 GHz can be implemented without using a technique such as electron beam exposure as an absolutely necessary condition.

[Brief description of drawings]

FIG. 1 shows a longitudinal sectional view of a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing the manufacturing process and structure of the embodiment of the present invention. FIG. 3 is a vertical sectional view of another embodiment of the present invention in which a pair of 1Tr / Cell memories are provided. 1 ... Semiconductor substrate 3 ... Field insulator 5,5 '... Drain or source 4 ... Source or drain 6,6' ... Channel forming region 15,15 '... First impurity region 14 ... Impurity region 2 of 18, 18 '... Gate electrode 10, 10' ... Insulated gate type field effect transistor (MIS F
ET) 20,20 '…… Capacitor ～ …… Patterning process by photomask 37,37 ′ …… Ion implantation direction 38,38 ′ …… Ion implantation direction

Claims (1)

[Claims] 1. A step of forming a convex region on a semiconductor substrate of one conductivity type, a step of forming a gate insulating film on a side surface of the convex region, and a step of forming the convex insulating film on the gate insulating film. Forming a coating film for forming a gate electrode on a corner portion of the semiconductor substrate, anisotropically etching the coating film to form a rectangular or triangular gate electrode on the corner portion, Impurities are obliquely added to the semiconductor substrate using the electrodes as masks to form drains or sources at the bottom of the semiconductor substrate and sources or drains at the tops of the convex regions. A method for manufacturing a vertical channel type insulated gate type field effect semiconductor device, which comprises: