JP3054178B2 - Insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides an insulated gate type field effect semiconductor device of a semiconductor integrated circuit, particularly, an ultra-high-density integrated circuit (referred to as ULSI) of 16M to 16Gbit level. About doing.

The present invention relates to a semiconductor device, especially a MIS (insulating gate type) field effect semiconductor device having a microchannel type (hereinafter referred to as 0.03 to 1 μm having a channel length of 1 μm or less).
A channel MIS FET) and a semiconductor device in which a capacitor is connected thereto, for example.

According to the present invention, a {100} crystal plane or a crystal plane in the vicinity thereof (the {100} plane or its vicinity, that is, a crystal plane having a deviation within ± 10 ° from the {100} plane is hereinafter simply referred to as a {100} plane) is rectangular. A convex region of the shape is formed by performing anisotropic etching, and a channel for flowing a current in the vertical direction is formed on a side surface having a {100} crystal plane of the convex region of the single crystal or a crystal plane in the vicinity thereof. Vertical channel type MIS FET.

[Prior Art] Conventionally, as shown in FIG. 1, the structure of an MIS FET or a capacitor connected in series with the MIS FET is formed on one surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. Then, the gate insulator (2), the gate electrode (18) and the source or drain (4), the drain or source (5) are connected to an LDD (a drain having a relatively low impurity concentration, that is, a lightly doped drain). A first impurity region (15) and a second impurity region (14) having a high impurity concentration are formed two-dimensionally on the outside thereof to form a MISFET (10). Further, the capacitor (20) is provided with a lower electrode (21), a dielectric (22), and an upper electrode (23) connected to the first impurity region (15). Thus, MIS FET (10),
The capacitor (20) has been formed on the semiconductor substrate so as to have the same plane. In the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to constitute one bit memory), this planar configuration increases the cell area and limits the integration of high density. there were.

On the left and right sides of the gate electrode (18), LDD (4),
As auxiliary means for producing (5), there were rectangular or triangular portions (38) and (38 '). According to the present invention, a gate electrode is provided as a laminate on the rectangular or triangular portion, and a convex region therefor is defined as a {100} surface, and each of the four sides having the rectangle is defined as a {100} surface. Is used.

[Object of the present invention] In the present invention, a rectangular convex region having a {100} plane on a plane and a side surface is provided, and one or two side surfaces of this region are used as a channel forming region. That is, a current flows in the vertical direction, the channel length is extremely small, 0.03 to 1 μm, and the size of one and the MISFET is 1 μm.
□ to 10μm □
An object of the present invention is to provide an element structure for ULSI that can be made up to 6 Gbits. It is still another object of the present invention to provide an inverter structure by combining the MIS FET and a memory cell structure connected to another element such as a capacitor.

[Structure of the Invention] In the present invention, a rectangular convex region is provided on a {100} semiconductor substrate. Then, each of the four side surfaces having the convex {100} surface is simultaneously defined as a {100} surface, the side surface is defined as a channel forming region, and a current flows in a vertical direction.
That is, it was a vertical channel type. Further, by adding an impurity to the rectangular convex region from the lateral or oblique direction by ion implantation or the like, the threshold voltage of the channel forming region is controlled, the embedding channel is formed, and the channel is formed. On the aspect where the formation is not performed, the generation of the parasitic channel is prevented in the vertical direction so that the minute leak due to the generation of the parasitic channel does not flow.
Another object of the present invention is to provide an asymmetric MIS FET by forming the source and drain in such a MIS FET in the lateral direction so as to facilitate electrode formation in a subsequent process.
That is, a rectangular convex single-crystal semiconductor region is provided on one main surface of the semiconductor substrate, and one source or drain of the MIS FET is configured as an LDD on the upper portion, and a side portion of the convex region is a vertical channel. The bottom of the semiconductor substrate is a drain or source having an LDD structure. The source, drain and drain or source have an impurity concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 . In addition to improving the drain breakdown voltage by lowering the concentration, the parasitic capacitance with the gate electrode is reduced, and the injection of hot carriers into the gate insulator is prevented. That is, a rectangular or triangular gate electrode is provided on the gate insulating film at the corner portion of the convex region, in addition to the LDD.

The upper lateral portion of the gate electrode coincides with the edge of the source or drain or is slightly larger on the source or drain side, and is located below the second impurity region on the upper side, and the gate electrode is located at the lower side. The offset structure is prevented, and a margin (margin) is provided for manufacturing.

The source or drain and the drain or source are used to make the second impurity region and the first impurity region having a high impurity concentration easily in ohmic contact with an external electrode.
It is provided with a lateral surface such that the contact surface is on the upper side.

For this reason, the semiconductor device of the present invention achieves the high density for forming the ULSI by not providing the area occupied in the substrate of the conventional lateral MIS FET by scaling, but by providing it actively in the height direction. The purpose is to let them.

 An embodiment of the present invention will be described below with reference to the drawings.

Example 1 In this example, the manufacturing process is shown in FIG. 2, and a vertical channel type N channel type MISFET is formed by using a rectangular convex region of a single crystal semiconductor substrate having a {100} plane. Two are provided as a pair.

2 (A) to 2 (D) show longitudinal sectional views, and FIG. 2 (E) shows a plan view. AA 'in FIG. 2 (E)
2 correspond to FIGS. 2A to 2D.

As a single crystal semiconductor substrate having a {100} plane, for example, a silicon single crystal semiconductor {100} plane, P-type 10 to 500 Ωcm was selected. As shown in FIGS. 2A and 2E, a rectangular convex region (35) was formed on the single crystal substrate using the first photomask as shown in FIGS. For the fabrication, anisotropic etching of a silicon single crystal substrate may be formed using the photoresist (32) as a mask. It is important that the corner has a very sharp vertical surface at 90 ° to the upper surface of the substrate. The height of the convex area (35) is 0.5 to 4 μm.
m, for example, 1.5 μm.

Then, as shown in FIG. 2 (E), in the convex region (35) having a rectangular shape, the channel formation region becomes the (100) plane (the <100> direction (40)), and the parasitic channel prevention surface also becomes (010). ) Plane (<010> direction (40 ')).

Then, the fixed charge density can be reduced to about half of that of the other (11) and (111) crystal planes on all of the sides.

Silicon nitride that has a masking action against oxidizing gas (33)
Was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multi-layered film of mixed silicon oxide, polycrystalline silicon and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask () to use the selective oxidation method, thereby forming FIG. 2A.

After doping a P-type impurity for forming a channel cut into the removed region, the field insulator (3) is removed.
It was formed by being embedded to a thickness of 0.5 to 2 μm.

As shown in FIG. 2B, the silicon nitride film (33) is removed to form a film (2) for forming a gate insulating film on the semiconductor substrate (1) having the convex region (35). did. De The vertical than ^{3 × 10 16 ~5 × 10 18} cm -3 and a relatively low concentration in a to and 3000A～1myuemu, for example, ion implantation of As or phosphorus to a depth of 5000 Å - flop, and the semiconductor substrate ( 1) N at the bottom of the surface and at the top of the convex area (35).
Mold drain or source (5), (5 ') and source
This is for configuring the source or drain (4) as an LDD.

The channel forming regions (6) and (6 ') are connected to the source or drain (4), the drain or source (5),
Before or after the formation of (5 '), or before or after the formation of the gate insulating film (2), it was formed on the side surface of the rectangular convex region by means such as ion implantation. That is, the channel forming regions (6) and (6 ') control the threshold voltage, and are normally off for the enhancement type MISFET or are normally off for the depletion type MISFET. Mully-on, and one or both of (6) and (6 ') were automatically formed using a photomask. The two kinds of impurities may be added twice as the embossed channel type. Impurities were positively added to the side surfaces (6) and (6 ') of these convex regions (35). For example, lateral or oblique ion implantations (38) and (38 ') were doped with boron or boron and arsenic.

In the rectangular convex region (35) where no channel is formed ((36) and (36 ') in FIG. 2E), a parasitic channel is likely to occur, and the source or drain (4) Boron is added at a higher concentration than the substrate, that is, the convex region, so that a small leak current is not generated between the drain or the source (5) and (5 '), so that the off state is constantly achieved. In other words, ion implantation was performed in an oblique direction or a lateral direction with respect to the upper surface of the substrate.

Since not only the substrate but also the insulating film (33) or (2) is damaged by these ion implantations, the whole is annealed to monocrystallize the semiconductor substrate (1) and the convex region (35). did.

This ion implantation step is performed in the same manner as in FIG.
This may be performed as shown in FIG.

By removing the silicon oxide film (2), another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film (2).
It may be.

Next, as shown in FIG. 2C, a window for forming a source or a drain was formed in the gate insulating film (2) using a third photomask (). After sufficiently cleaning the surface of the insulating film, a low pressure gas phase method (LPCVD
A silicon semiconductor film (7) doped with an impurity of one conductivity type, for example, an N-type impurity (phosphorus) to a concentration of 1 to 10 × 10 ²⁰ cm ⁻³ to a thickness of 0.5 to 2.5 μm. Formed to form gate electrodes and other leads. This impurity doping is not performed simultaneously with the film formation, but is diffused after performing the following anisotropic etching process to leave portions (8) and (8 ') serving as gates on the film (7). Doping may be performed by a method.

This coating (7) may be a metal or an intermetallic compound instead of silicon doped with impurities.

Further, a multilayer film of a P ⁺ or N ⁺ type semiconductor and a metal or a metal compound, particularly Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ) may be used.

 Thus, FIG. 2 (C) was obtained.

Next, as shown in FIG. 2 (D), a photoresist (for example,
ORM-83 (manufactured by Tokyo Ohka) () was selectively coated, followed by anisotropic etching. For this etching, it is important to use an anisotropic etching method with very little or no side etch and taper etch, instead of an isotropic etching method using a conventionally used solution. Specifically 2.45GHz
A reactive gas for etching, for example, nitrogen fluoride (NF ₃ ) or carbon fluoride (CF ₄ ) is chemically activated by microwaves using, and the degree of vacuum is further reduced to 0.1 to 0.001 torr.
A fluorine shower, which was made into a plasma in an atmosphere having a degree of vacuum of 0.005 to 0.01 torr, was caused to flow vertically from the upper surface of the substrate, a bias was applied to the substrate, and an effort was made to eliminate side etching as low-temperature etching.

As a result, when the planar portion on which the photoresist is not formed is completely removed from the coating (7), the coatings (8), (8) on the side portions which are the corners of the convex region (35) are obtained. ′)
Could be left as vertical rectangular or triangular gate electrodes (18) and (18 ') around the sides. Further, the contact (11) of the first impurity region (corresponding to (15) in FIG. 2D) of the drain or source (5), (5 ') and its lead (12) are In the embodiment, N ⁺ type electrode leads could be left. The gate electrodes (18) and (18 ') do not exist over the upper surface of the convex region (35), and the width thereof is not the width determined by photolithography, but differs from the thickness of the side surface of the coating (7). It can be determined by the degree of isotropic etching.

And the gate electrode (18) is as shown in FIG.
It is extended as a lead (38) and other gate electrodes (1
8 ') connects the lead (12') to the contact (11 ').

In FIG. 2 (D), rectangular or substantially triangular gate electrodes (18) and (18 ') have a lower end portion having a width of 0.1 to 1 .mu.m.
m, but the layer can be extended as a lead over the field insulator and
The width of the lead may be as wide as 1 to 10 μm, and may be connected to the electrode lead of another MIS FET provided on the same substrate, or may be electrically connected to another capacitor, a resistor, or the like. Needless to say.

FIG. 2 (E) shows an inverter, that is, a load (1).
0 ') and the driver (10). Although omitted in the drawings, after these, an interlayer insulating film is formed entirely,
The output may be connected to the second impurity region (14), and the current may be connected to the electrode (12 ') by providing a multilayer wiring.

Upper end (48) of this rectangular or triangular gate electrode
Is substantially coincident with the end (44) of the source or drain, that is, located at the same level or above, and located off the end (45) of the second impurity region (14) formed in a later step. Is preferred. The width between (44) and (45) is extremely important as a margin in manufacturing (margin).

The channel length of the MISFET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). The LDD source or drain (4) is provided as a margin for the height of the gate electrodes (18) and (18 ').
The gate electrodes (18) and (18 ') are characterized in that they do not enter an offset state.

Next, as shown in FIG. 2 (D), the ion implantation method has a higher concentration than the source or drain (4) and the drain or source (5), (5 '). Arsenic, which is an N-type impurity, is implanted at an accelerating voltage of 30 to 150 KeV to make contact with electrodes, and 1 × 10 ¹⁹ to 1 × 10 ¹⁹
The first impurity region (1 × 10 ²¹ cm ⁻³⁾
5) and (15 ') were formed on the bottom of the substrate with their ends (47) substantially matching the positions of the lower ends (46) of the rectangular or triangular gate electrodes (18) and (18'). . In addition, a second impurity region (14) is simultaneously formed on the N-type drain or source (4) above the convex region (35),
This facilitated ohmic contact with other electrodes.

Thus, it is a vertical channel type, and the source and drain are LD
It was possible to obtain a vertical channel type so-called vertical / horizontal type MISFET while using the D structure, while using the plane above the convex region and the bottom surface of the substrate for contact with the outside. Therefore, it is easy to form an electrode (contact) for the source and drain, and the channel length is as small as 0.1 to 1 μm, and the length can be controlled and manufactured precisely by using the LDD structure.

As is clear from the above embodiments, the present invention provides a vertical rectangular or triangular gate electrode (18), (18 ') adjacent to a convex region while increasing the mechanical strength and increasing the channel forming region. In (6) and (6 '), the {100} plane is used to reduce interface states (due to the generation of positive charges due to the presence of dangling bonds in silicon). ), Drain or source (5), (5 ') is LDD
A vertical channel type MIS FET was obtained.

On the other side surface of the rectangular convex region ((36), (36 ') in FIG. 2 (E)), the side surface is also set to {100} surface so that no parasitic channel is generated. The generation of fixed charge was prevented. Therefore, this aspect has to be
Fig. 2 (E)
As shown in (36) and (36 '), the addition was performed to form a channel cut.

2D, the source or drain (4), the drain or source (5),
(5 ') is separated at the channel formation regions (6) and (6'), and the gate insulating film (2) on the side surface of the channel formation region
By forming gate electrodes (18) and (18 ') on the side surfaces of the transistor, a vertical-horizontal micro-channel (μ-channel) type having a precisely controlled channel length and a small area for the entire transistor substrate is reduced. MIS FET can be made.

Further, after a lead in a direction perpendicular to these leads (19) and (12) is formed of a polyimide-based insulator such as PIQ, the metal on the upper surface is selectively removed by photolithography. Thus, a multilayer wiring can be formed.

In the embodiment of the present invention, the conductivity type is P-type for the substrate, P ^- type for the channel region (6), N-type for the source or drain (4), drain or source (5), (5 '). The (14), (15), and (15 ″) are high concentration regions of the N ⁺ type, and the gate electrodes (18) and (18 ″) are side surfaces of the convex region. This is a so-called two μMIS FETs that constitute a pair using the MISFET.

In the present invention, the second impurity region (14) and the gate electrode (18) of the second MISFET are connected by a multilayer wiring, and the channel is normally turned on to form a load. An E / D type (driver is an enhancement type, load is a depletion type) and an inverter structure may be used in which the first MIS FET (10) is used as a driver and its output is taken out from (14).

FIG. 1 shows an N-channel type of two MISFETs in a rectangular convex region. Another MISFET is formed in a P-channel type at another portion separated by a field insulator. The use of LSI and VLSI as the MIS structure (complementary structure) can further promote the present invention.

Embodiment 2 FIG. 3 (A) shows another embodiment to which the present invention is applied.

FIG. 3 (A) is a longitudinal sectional view taken along the line AA 'of FIG. 3 (B), and its electric circuit is shown in FIG. 3 (C).

That is, the rectangular convex region (35) has channel forming regions (6) and (6 '), on which the source or drain (4) and the high concentration second impurity region (14) are formed. ). Further, a field insulator (3) is provided in a peripheral portion of a bottom portion of the semiconductor substrate (1) to form a first impurity region (1).
5), (15 ') and outside thereof two drain or source (5), (5'), gate electrodes (18), (18 '), gate insulating film (2), (2') MIS FET (1
0) and (10 ').

The channel forming region (6), (6 ') is a channel-shaped Buried in the N-channel MIS FET P-type region (6), (6'), N-type or P ^- region (46), (4
6 ') and P-type regions (56) and (56').
In this plurality of oblique or lateral ion implantations, the other side surfaces (36) and (36 ') are masked with a photoresist, and conversely, boron implantation for preventing a P-type parasitic channel is performed. 36), (36 ') when performing on side (6),
(6 ') was masked with a photoresist so as not to be injected here.

For multi-layer wiring, contacts (11), (11 ') and (11 ") are formed by selective growth of tungsten, and aluminum leads (12), (12') and (24) are interlayer-insulated. Formed on material (17).

An interlayer insulator such as polyimide is formed, and a third
May be formed.

The cell area was extremely small and could be formed at a high density. Example 1 was used for manufacturing steps not shown in this example.

In the present invention, the leads (12) and (12 ') may be used as a lower electrode of a capacitor, a dielectric may be provided thereon, and a capacitor may be provided thereon as an upper electrode, thereby forming a 1Tr / Cell memory. . Then, it could be made as a stacked memory cell. In addition, this capacitor is connected to the field insulating film (3) or the convex region (35) and the gate electrode (1).
8) and (18 '), and the cell area could be increased in density.

In this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24), and the word line is the gate electrode (1).
8), (18 ') and a pair of 1Tr / cell memory systems.

In the present invention, a floating gate type nonvolatile memory may be formed by providing an electrically floating electrode in the gate insulating film.

In the above two embodiments, the material constituting the first region or the vertical rectangular or triangular gate electrode (1
The material constituting 8) is mainly described with a material having the same main component as that of a substrate doped with an impurity having a P ⁺ or N ⁺ conductivity type, for example, silicon.

In the present invention, the semiconductor substrate is mainly described with single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP or a polycrystalline, amorphous or semi-amorphous semiconductor.

Further, the channel forming region may be a buried channel type instead of the MIS FET using surface diffusion. Further, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

"Effects" As is clear from the above embodiments, the present invention is not a conventional structure in which a source and a drain having a pair of structures are separated from each other by a gate electrode and are wired in the horizontal direction. Microchannels were obtained by making it easy to make contact with the outside, having the same upper surface as the substrate, and having a vertical channel. In order to form such a microchannel, the convex region is rectangular.
By setting all of the side surfaces to {100} surfaces, generation of interface charges was reduced, and anisotropic etching was facilitated to facilitate manufacture. In addition, generation of a parasitic channel is prevented by ion implantation in the lateral or oblique direction, and the threshold voltage in the N-channel formation region is easily controlled.

Channel lengths should be LDD so that they can be precisely controlled.
The source and the drain are formed, and the characteristics are controlled by the ion implantation concentration. Gate electrode is convex first
The structure was reinforced mechanically so that the side portions of the region were more extended over the region, and efforts were made to increase reliability.

Due to its structural features and the channel length of 0.1 to 1 μm, an ultra-short channel (μ channel) MIS FET having a frequency response speed of 1 to 10 GHz can be used without using a technique such as electron beam exposure as an absolute requirement. It has a major feature that it is implemented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing a manufacturing process and a structure of the embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Convex area | region 3 ... Field insulator 4 ... Source or drain 5, 5 '... Drain or source 14 ... 2nd impurity region 15, 15 '... second impurity region 18, 18' ... gate electrode 10, 10 '... insulating gate type field effect transistor (MIS F
ET) 36,36 ': Boron-doped region for preventing parasitic channel 38,38': Direction of ion implantation 40,40 ': Crystal orientation ~: Patterning process by photomask

Claims (1)

(57) [Claims] 1. A semiconductor device according to claim 1, wherein the semiconductor substrate has a rectangular shape as viewed from above, and all the side surfaces have a {100} surface, a convex region having a channel forming region of the convex region, and two opposite side surfaces having a channel forming region. An insulating film covering at least a part of the bottom of the semiconductor substrate; a rectangular or triangular gate electrode provided near the channel forming region via the insulating film; and an upper portion of the convex region. An insulated gate field effect semiconductor device having a source or a drain and a drain or a source provided at the bottom portion, wherein the side surface of the convex region having the channel forming region is different from a side surface thereof. An insulating gate type field effect semiconductor device, wherein impurities of a conductivity type different from a conductivity type of the source and the drain are added to two side surfaces.