JP2990231B2 - Manufacturing method of vertical channel type insulated gate field effect semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, particularly, an ultra-high-density integrated circuit (referred to as ULSI) at a 16M to 16 Gbit level.

The present invention proposes a method for manufacturing a semiconductor device, particularly a MIS (insulating gate) field-effect semiconductor device having a microchannel type (hereinafter referred to as a μ-channel MIS FET having a channel length of 1 μm or less and 0.03 to 1 μm). It is in.

The present invention provides a vertical channel type MIS FE in which a convex region is provided on a surface of a semiconductor substrate by performing anisotropic etching, and a channel is formed on a side surface of the convex region of the single crystal.
It relates to a method for manufacturing T.

[Prior Art] Conventionally, as shown in FIG. 1, the structure of a MIS FET or a capacitor connected in series with the MIS FET is formed on one surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. A drain or source (21), which is effectively a drain or source and constitutes a lower electrode of the capacitor, is provided relative to the gate insulator (2), the gate electrode (18) and the source or drain (14); A capacitor insulator (22) and a counter electrode (23) were provided.

Conventionally, MIS FETs have a channel formation region in the lateral direction parallel to the upper surface of the semiconductor substrate, and a pair of source, drain (14) and drain or source (21) must be formed symmetrically under both ends of the gate electrode on the semiconductor substrate. They were formed by forming the same plane. Furthermore, in the case of 1Tr / Cell (one MIS FET and one capacitor are connected in series to form a memory that constitutes one bit), the gate electrode (18) is not only on the gate insulator (2) but also on the capacitor. Of the counter electrode (23). This is a gate electrode (18)
One end of the source or drain (14) is provided under one end of the gate electrode, and the one end of the drain or source (21) is self-aligned with the other end on the gate electrode. The other end (18 ″) of the gate electrode was made larger than the channel region (6) to use poly II (polycrystalline silicon film for (23) and (18)) to compensate for variations in mask alignment accuracy. Process), but in such cases,
It is impossible to reduce the channel length to 1 μm or less due to the restrictions on the photo-etching process. In particular, because of the unevenness in the step portion of (18), shortening the channel length is not likely to cause pattern breaks and the like. It was possible. The present invention is characterized in that the gate electrode of the MIS FET is provided by positively utilizing the step in reverse, and the gate electrode is formed without extending over the counter electrode of the capacitor forming the convex shape. I do.

"Object of the present invention" The present invention is such that a current flows in a vertical direction in a channel forming region under the gate electrode, and the channel length is 0.03 to 0.03.
One MIS FET with extremely small size of 1μm
An object of the present invention is to provide a method of manufacturing an element structure for ULSI that can be manufactured from 16 Mbits to 16 Gbits by reducing the size to about 1 μm □ to 10 μ □.

"Constitution of the Invention" The present invention provides an asymmetric MIS by forming this channel formation region in a vertical direction, that is, a vertical channel type, and forming a source and a drain in a horizontal direction to facilitate electrode formation in a subsequent process. It is in providing FET. That is, a convex single crystal semiconductor region is provided on one main surface of the semiconductor substrate,
The upper part is LDD for one source or drain of MIS FET.
(A drain with a relatively low impurity concentration, that is, a lightly doped drain). Further, the side of the convex region is a vertical channel forming region, and the bottom of the semiconductor substrate is a drain or a source having an LDD configuration. source or drain and the drain or source of improving the drain breakdown voltage in the impurity concentration of ^{3 × 10 16 ~5 × 10 18} cm -3 low concentrations, i.e. with the LDD, the corner portion of the convex region rectangular or This is provided with a triangular gate electrode.

The upper lateral portion of the gate electrode substantially coincides with the source or the drain, is coincident with the edge of the source or the drain, or is provided slightly larger on the source or the drain side, and is located on the lower side of the second impurity region. In addition, the gate electrode is prevented from having an offset structure, and a margin is provided for manufacturing.

In addition, the source or the drain and the drain or the source are provided with a lateral surface so that the second impurity region and the first impurity region having a high impurity concentration are easily brought into ohmic contact with an external electrode.

Therefore, the semiconductor device of the present invention achieves high density by forming the ULSI not by reducing the area occupied by the substrate of the conventional lateral MIS FET by scaling, but by providing it actively in the height direction. It is an object.

 An embodiment of the present invention will be described below with reference to the drawings.

Example 1 This example shows the manufacturing process in FIG. 2, in which two vertical channel type N-channel MISFETs are provided as a pair using a convex region of a semiconductor substrate. .

Semiconductor substrate such as silicon single crystal semiconductor (100), P type 1
I chose 0-500Ωcm. A convex region (35) was formed on the single crystal substrate using the first photomask.
For the fabrication, anisotropic etching of a silicon single crystal substrate may be formed using the photoresist (32) as a mask.
It is important that this corner portion is extremely sharp at 90 ° with respect to the upper surface of the substrate and protrudes vertically. The height of this projection is 0.5 ~ 4μ
m, for example, 1.5 μm.

Silicon nitride that has a masking action against oxidizing gas (33)
Was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask () to use the selective oxidation method, thereby forming FIG. 2A.

After doping the removed region with a P-type impurity for forming a channel cut, a field insulator (3) is
It was formed by being embedded to a thickness of 0.5 to 2 μm.

As shown in FIG. 2B, the silicon nitride film (33) is removed to form a film (2) for forming a gate insulating film on the semiconductor substrate (1) having the convex region (35). did. A semiconductor substrate (1) doped with As or phosphorus by ion implantation to a relatively low concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 from the vertical direction and to a depth of 3000 to 1 μm, for example 5000 °; N at the bottom of the surface and at the top of the convex area (35)
This is for configuring the drain or source (5), (5 ') and the source or drain (4) of the mold as LDD (lightly doped drain).

Channel forming regions (6) and (6 ') are formed on the side surfaces of the convex region, and ion implantation (38) and (3) are performed in lateral or oblique directions to control the threshold voltage there.
8 ') was doped with boron.

Since not only the substrate but also the insulating film (33) is damaged by these ion implantations, the whole is annealed to monocrystallize the semiconductor substrate (1) and the convex region (35).

The silicon oxide film (2) is removed and another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film (2).
It may be.

Next, as shown in FIG. 2 (C), a window for forming a source or a drain was formed in the gate insulating film (2) using a third photomask (). After sufficiently cleaning the surface of the insulating film, a low pressure gas phase method (LPCVD
A silicon semiconductor film (7) doped with an impurity of one conductivity type, for example, an N-type impurity (phosphorus) to a concentration of 1 to 10 × 10 ²⁰ cm ⁻³ by a gate electrode to a thickness of 0.5 to 2.5 μm. And other leads were formed. This doping of impurities is not performed simultaneously with the film formation, but is performed by the following anisotropic etching to leave portions (8) and (8 ') serving as gates, and a diffusion method after the film (7) is formed. May be doped.

This coating (7) may be a metal or an intermetallic compound instead of silicon doped with impurities. Plus P ⁺
Alternatively, it may be a multilayer film of an N ⁺ type semiconductor and a metal or a metal compound, particularly Mo, W or a silicon compound thereof (MoSi ₂ , WSi ₂ ).

When this coating (7) is made of a compound or a mixture of WSi ₂ , MoSi ₂ , silicon, tungsten and molybdenum,
These films may be formed by LPCVD, electron beam evaporation, or reactive sputtering to form 0.3 to 1.5 μm, particularly 0.5 to 0.7 μm.

 Thus, FIG. 2 (C) was obtained.

Next, as shown in FIG. 2 (D), a photoresist (for example,
OMR-83 (manufactured by Tokyo Ohka) (), followed by anisotropic etching. For this etching, it is important to use an anisotropic etching method with very little or no side etch and taper etch, instead of an isotropic etching method using a conventionally used solution. Specifically 2.45GHz
A reactive gas for etching, for example, nitrogen fluoride (NF ₃ ) or carbon fluoride (CF ₄ ) is chemically activated by microwaves using, and the degree of vacuum is further reduced to 0.1 to 0.001 torr.
A fluorine shower, which was made into a plasma in an atmosphere having a vacuum degree of 0.005 to 0.01 torr, was caused to flow vertically from the upper surface of the substrate, and a bias was applied to the substrate.

As a result, when the plane portion where the photoresist is not formed in the coating (7) is completely removed, the coatings (8) and (8 ') on the side portions which are the corners of the convex region (3).
Could be left around the side as vertical rectangular or substantially triangular gate electrodes (18), (18 '). Further, a first impurity region for drain or source (second impurity region)
(Corresponding to (15) and (15 ') in Figure (D)) Contact (11)
In this example, the lead (12) could be left as an electrode lead of the N ⁺ type in this example. Gate electrode (1
8) and (18 ') do not exist over the upper surface of the convex region (35), and the width is not the width determined by photolithography. It can be determined according to the degree of etching.

Upper end (48) of this rectangular or triangular gate electrode
Is substantially coincident with the end (44) of the source or drain, that is, is located at the same level or above, and is located away from the end (45) of the second impurity region (14) formed in a later step. Is preferred. The width between (44) and (45) is extremely important as a margin in manufacturing.

The channel length of the MISFET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). As a margin for the height of the gate electrodes (18) and (18 '), the LDD source and drain (4)
And the gate electrode is not offset even if the anisotropic etch is somewhat broken.
This rectangular or substantially triangular gate electrode (18), (1
8 ') has a width at the lower end of 0.05 to 1.5 μm, typically 0.
A channel forming region (6),
Cover this area in the side direction of (6 ') and set the height to 0.2 to
2.5 μm, typically 0.3 to 0.8 μm. In particular, this height is a function of the film thickness of the film (5) and its etching time and intensity by plasma etching. A very short channel (hereinafter referred to as a microchannel) could be provided.

In FIG. 2 (D), rectangular or substantially triangular gate electrodes (18) and (18 ') have a lower end portion having a width of 0.1 to 1 .mu.m.
m, but the layer is extended as a lead on the field insulator as required for design, and the width of the lead is provided as wide as 1 to 10 μm. It is needless to say that it may be connected to the electrode lead of the MISFET or to another capacitor, resistor or the like.

Next, as shown in FIG. 2 (D), the ohmic contact is made at the electrode with higher precision than the source or drain (4) and the drain or source (5), (5 ') by ion implantation. Therefore, arsenic, which is an N-type impurity, is implanted at an accelerating voltage of 30 to 150 KeV, and 1 × 10 ¹⁹ to 1
The first impurity region (1 × 10 ²¹ cm ⁻³⁾
5) and (15 ') were formed on the bottom of the substrate so that their ends (47) were approximately aligned with the positions of the lower ends (46) of the rectangular or triangular gate electrodes (18) and (18'). . In addition, the upper portion of the N-type drain or source (4) above the convex region (35) is also used as the second impurity region (14) without using any photomask, and the convex shape (35) is also used. It was formed while being precisely controlled only by the acceleration voltage of ion implantation from the vertical direction, and this was easily brought into ohmic contact with another electrode.

Then, the first and second impurity regions (15),
(15 ') and (14) prevent the channel length from being varied by the re-diffusion due to the heat treatment after the ion implantation by the presence of the LDD source or drain (4) and the drain or source (5), (5'). be able to. In particular, the diffusion of the first impurity regions (15) and (15 ') in the lateral direction is performed in such a manner that the width of the lower end (46) of the gate electrodes (18) and (18') is set as a margin (self margin). You can have it.

Further, the electrode leads (11) and (12) are connected to a first impurity region acting as a drain or a source (15), and the other first impurity region (15 ') is connected to another electrode lead (19). In order to make ohmic contact with the electrode (13), there are provided higher concentration impurity regions (15) and (15 ') under the electrode (13), and a drain or source (14) contact is formed in these regions.

Thus, it is a vertical channel type, and the source and drain are LD
While having the D structure, the upper side of the convex region and the bottom surface and the lateral surface of the substrate were used for contact with the outside, and a vertical channel type so-called vertical / horizontal MISFET was able to be obtained. Therefore, it is easy to form an electrode (contact) for the source and the drain, and the channel length is as small as 0.1 to 1 μm, and the length can be controlled and manufactured precisely by using the LDD structure.

As is apparent from the above embodiments, the present invention provides a vertical rectangular or substantially triangular gain electrode (18), (18 ').
The source (4) adjacent to the channel forming regions (16), (16 ') while increasing the mechanical strength adjacent to the convex region,
Drain (5), (5 ') LDD vertical channel type MIS
FET was obtained.

Further, since the thickness of the gate electrodes (18) and (18 ') is large, the strength is geometrically weak, and the
Since the irregularities of the inherent defect in SI tend to be severe, it is electrically isolated with an insulating film (17),
Further, it is characterized in that it can be reinforced mechanically by bending over the convex region.

As apparent from FIG. 2 (D), the source or drain (4), the drain or source (5),
(5 ') is separated at the channel formation regions (6) and (6'), and the gate insulating film (2) on the side surface of the channel formation region
By forming gate electrodes (18) and (18 ') on the side surfaces of the transistor, the vertical and horizontal micro-channel (μ channel) type has a precisely controlled channel length and reduces the area of the entire transistor substrate. MIS FET can be made.

Furthermore, after forming a lead in the direction perpendicular to these leads (19) and (12) with a polyimide-based insulator such as PIQ, the metal on the upper surface is selectively removed by photolithography to form a multilayer wiring. Can be done.

FIG. 2E is a vertical sectional view of the MIS FET (1) shown in FIG. 2D.
MOS FETs that symbolize (0) and (10 ') with the corresponding numbers
It is written.

In the embodiment of the present invention, the conductivity type is P-type for the substrate, P ^- type for the channel regions (6) and (6 '), N-type for the source or drain (4), and the drain or source (5) and (5'). (14), (15), and (15 ') are N ⁺
The high-concentration region of the mold. In addition, the gate electrodes (18), (1
8 ′) are so-called two μMIS FETs that form a pair using each side surface of the convex region.

Also, a P-type first MIS FET (1
0), and the output may be taken out from (14) using the second MIS FET (10 ') as a driver. At that time, the load (10) is a depression type MIS
An FET may be used, and the driver (10 ') may be an enhancement type.

FIG. 1 shows two MIS FETs formed on a substrate, and another MIS FET is formed on another part separated by a field insulator.
The present invention can further promote the so-called LSI and VLSI in which FETs are provided on the same substrate to form a plurality of MIS FETs.

Embodiment 2 FIG. 3 (A) shows another embodiment to which the present invention is applied.

FIG. 3A shows two MIS FETs (1
0), (10 ') and two capacitors are respectively connected in series, and two 1Tr / Cells are provided.
That is, the channel-forming region (6),
(6 '), on which a source or drain (4) and a high-concentration second impurity region (14) are provided. In addition, a field insulator (3) is provided on the periphery of the bottom of the semiconductor substrate (1) to provide the first impurity regions (15), (1).
5 ') and a drain or source (5) outside thereof,
(5 '), two MIS FETs (10), (1) as gate electrodes (18), (18'), and gate insulating films (2), (2) '.
0 ′). The lower electrodes (21), (20) and (20) of the capacitors (20) and (20 ') are connected (13) and (13') to the first regions (15) and (15 ') of N ⁺ to make ohmic contact. twenty one'),
Dielectrics (22), (22 ') and the upper electrode (2
3) and (23 ') are provided.
(20 ').

In FIG. 3 (A), (14) is a bit line,
(18) and (18 ') are part of a memory system having a structure in which two 1Tr / Cells are paired with word lines. With such a structure, the convex region (35) is divided into two MIS FETs (1
0), (10 '), and dielectric (2
2) and (22 ') are stacked memory cells that can use a material having a high dielectric constant different from the gate insulating film, such as tantalum oxide, titanium oxide, silicon nitride, barium titanate, or a multilayer film of these materials. In this embodiment having characteristics, the outer periphery of the gate electrodes (18) and (18 ') is insulated by the oxide interlayer insulator (17), and the thickness is 0.1 to 1.0 μm. The connection between the first impurity regions (15) and (15 ') and the lower electrodes (21) and (21') of the capacitors (20) and (20 ') is made by selective growth of tungsten (13) and (13). ′) To form electrodes (contacts). Therefore, the lower electrodes (21) and (21 ') are made of tungsten silicide.

As described above, when the MISFET of the present invention is used, a contact can be obtained while being connected to the first impurity region with a sufficient area. That is, the first impurity region (1
5), (15 ') can be made. The channel length could be made precisely as shown in Example 1 irrespective of the contact formation region and without increasing the size of the MIS FET as viewed from above the substrate.

An interlayer insulator such as polyimide is formed, and a third
May be formed.

The cell area was extremely small and could be formed at a high density. Example 1 was used for manufacturing steps not shown in this example.

Embodiment 3 FIG. 3B is a longitudinal sectional view of this embodiment.

As is apparent from the drawing, a short crystal semiconductor (35) is provided on the surface of the semiconductor substrate in a convex shape on the surface of the semiconductor substrate, and a gate insulating film (2),
(2 ') is provided, and gate electrodes (18) and (18') are formed as a pair. A drain or source (5), (5 ') and a source or drain (4) with a low impurity concentration LDD concentration are provided for precisely controlling channel lengths (6), (6'). Using a part of the gate electrode such as silicon as a mask, the first impurity region (1
5) and (15 ') are provided by self-alignment, and a second high-impurity-concentration region (14) is also provided by ion implantation above the convex region. Thus, μ channel MIS FET
(10) and (10 ') are provided in a paired structure.

Next, the contact openings (9) and (9 ') provided in the first impurity regions (15) and (15') are provided in the same manner as in the first embodiment. The side electrodes (20) and (20 ') are, for example, doped silicon
It was formed so as to have a thickness of about 1 μm. A tantalum oxide film (22), (22 ') is sputtered on this upper surface by 100-500.
Å was formed. After this, a counter electrode (2
3), (23 ')) are provided by metal or semiconductor, and after photo-etching, the capacitors (20), (2')
0 ').

Thus, the upper electrodes (23) and (23 ') of the capacitors (20) and (20') and the dielectrics (22) and (22 ') and the lower electrodes (21) and (21') are stacked. It could be made as a memory cell. In addition, this capacitor can be provided over the field insulating film (3) or over the convex region (35) and the gate electrodes (18) and (18 '), and the cell area can be increased in density. . Multi-layer wiring (24) through contact to second impurity region (14)
Is provided as a word line on the interlayer insulating film (17), and the gate electrodes (18) and (18 ') are used as bit lines, thereby forming a vertical channel type, a source / drain horizontal MISFET in a self-aligned manner. Forming in pairs was extremely effective in reducing the size, increasing the density, and improving the reliability.

In this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24), and the word line is the gate electrode (1).
8), (18 ') and a pair of 1Tr / cell memory systems.

In addition, since these are integrated N-channel MIS FETs, a plurality of convex regions are provided on the same substrate, and a part thereof is used as a P-channel MIS FET to form a complementary (complementary) integrated circuit. Is valid.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to form a floating gate nonvolatile memory.

In the above three embodiments, the material forming the first region and the material forming the vertical rectangular or substantially triangular gate electrode (18) are made of impurities having a P ⁺ or N ⁺ conductivity type. The same main components and materials as the doped substrate, such as silicon, are mainly described.

However, they may also be mixtures or compounds of silicon and Mo, W (MoSi ₂ , WSi ₂ ), and may be intrinsic, P ⁺ or
It goes without saying that the N ⁺ type semiconductor may have a multilayer structure, or may have a multilayer structure of a semiconductor such as silicon and Mo, W, platinum or a compound thereof.

In the present invention, the semiconductor substrate is mainly described with single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP or a polycrystalline, amorphous or semi-amorphous semiconductor.

Further, the channel forming region may be a buried channel type instead of the MIS FET using surface diffusion. Alternatively, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[Effects] As is clear from the above embodiments, the present invention is not a conventional structure in which a source and a drain having a pair of structures are separated from each other by a gate electrode and wired in the horizontal direction. The upper surface has the same plane as that of the substrate, and the channel has a vertical shape to form a microchannel. Even in such a microchannel, a source and a drain as an LDD are formed in the microchannel so that the channel length can be precisely controlled, and the channel length is controlled by ion implantation concentration. The gate electrode has a structure that is mechanically reinforced so that a side portion thereof is more entangled with the convex first region, and efforts have been made to improve reliability. The threshold voltage of the channel forming region has a structure in which an impurity such as boron is doped in the upper part of the semiconductor obliquely or laterally, and the frequency response speed depends on its structural characteristics and the channel length of 0.1 to 1 μm. It has a great feature that an extremely short channel (μ channel) MISFET having 1 to 10 GHz can be implemented without using a technique such as electron beam exposure as an absolute requirement.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing a manufacturing process and a structure of the embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which 1Tr / Cell memories are provided in a pair. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Convex area | region 3 ... Field insulator 5, 5 '... Drain or source 4 ... Source or drain 15, 15' ... 1st impurity region 14 ... 2nd Impurity region 18, 18 'Gate electrode 10, 10' Insulated gate field effect transistor (MIS F
ET) 20,20 '…… Capacitor …… Pattern processing by photomask

Claims (1)

(57) [Claims] A step of forming a convex region in a semiconductor substrate of one conductivity type; and a step of forming a low-concentration impurity region by adding an impurity to a bottom portion of the semiconductor substrate and an upper portion of the convex region. Forming a gate insulating film on the side surface of the convex region; forming a film for forming a gate electrode; anisotropically etching the film to form a corner of the convex region; A step of forming a gate electrode having a rectangular or triangular shape in the portion, and an upper end portion substantially matching a lower end portion of the low-concentration impurity region located above the convex region; and using the gate electrode as a mask, Forming a high-concentration impurity region at the bottom of the semiconductor substrate and above the convex region by adding an impurity to the semiconductor substrate. A method for manufacturing a semiconductor device results.