JP3636296B2 - Pachinko machine - Google Patents

Description

【００３６】
【表２】

【００３７】
【表３】

【００３８】
【表４】

【００３９】
また、大当りとなる図柄の組合わせは表５に示す通りであって、左，中，右の図柄が全て一致した場合には上図柄の如何を問わず大当りの図柄組合わせとなり、また、左および中図柄の数字が一致した場合には、右図柄の数字が左および中図柄の数字よりも１つだけ小さく（但し、左および中図柄が“０”で一致した場合には右図柄が“９”の時）、かつ、上図柄の表示が“＋１”となった時にのみ大当りの図柄組合わせとなる。
【００４０】
【表５】

【００４１】
即ち、左，中，右，上大当たり図柄データ記憶レジスタｒ０ａ乃至ｒ３ａに記憶される図柄の組合わせは表５に示される組合わせ図柄のうちのいずれかであり、それ以外の組合わせは全て左，中，右，上外れ図柄データ記憶レジスタｒ０ｂ乃至ｒ３ｂに記憶されることになる。よって、機械式回転ドラムのように各図柄を完全に無作為に変動表示して大当りがでる確率は、当り図柄の組合わせ数を図柄の総組合わせ数で除した値７０／１４４００となるが、実施形態においては、左，中，右第１種始動口１６，３，１７への入賞検出時点でセットされた確定乱数記憶レジスタＲｉの値と設定値との関係に基いて変動表示停止時に表示する図柄を選択するようにしているので、大当りの発生確率は各図柄の組合わせ発生確率等と無関係に任意に設定することができる。なお、レジスタｒ０ａ乃至ｒ３ａ，レジスタｒ０ｂ乃至ｒ３ｂ，レジスタｒ０乃至ｒ３の各値は内部処理指標の値を示すものであって、実際の変動表示に用いられる表示指標ｉｌ，ｉｃ，ｉｒ，ｉｕの現在値とは無関係である。
【００４２】
図１０乃至図２０に示すタスク３の処理は主に図柄の変動表示に関するものである。
【００４３】
タスク３の処理を開始したＣＰＵ３２は、まず、左，中，右第１種始動口１６，３，１７への入賞検出に基く新規の図柄変動表示の開始が可能であるか否かを状態記憶フラグＦａに１もしくは２が設定されているか否かにより検出する（ステップｃ１，ステップｃ２）。状態記憶フラグＦａの値が１であれば図柄変動表示の実行中であり、また、状態記憶フラグＦａの値が２であれば大入賞口１５の開放動作の実行中であって、いずれの場合にも新規の図柄変動表示の開始は不能である。なお、状態記憶フラグＦａの値が１の時はＣＰＵ３２はタスク３の処理で図柄の変動表示を継続して実行し、また、状態記憶フラグＦａの値が２の場合には、実質上、タスク３の処理が非実行とされる。
【００４４】
また、状態記憶フラグＦａが１および２以外の値であれば図柄の変動表示も大入賞口１５の開放動作も行われていないので、新規の図柄変動が開始可能な状態にある（初期段階ではＦａ＝０）。
【００４５】
この場合、ＣＰＵ３２は、まず、記憶状態識別フラグＦ０に１がセットされているか否か、即ち、タスク１の処理で左，中，右第１種始動口１６，３，１７への入賞が既に検出されているか否かを判別する（ステップｃ３）。
【００４６】
左，中，右第１種始動口１６，３，１７への入賞が検出されていれば、入賞検出時点における大当り用乱数記憶レジスタＲＡＮ１の値がタスク１の処理で確定乱数記憶レジスタＲｉに記憶され、かつ、確定乱数記憶レジスタＲｉに対応した記憶状態識別フラグＦｉに１がセットされるが、この時、ＣＰＵ３２は左，中，右第１種始動口１６，３，１７への入賞が検出される毎にｉ＝０〜３の順で確定乱数記憶レジスタＲｉに乱数を記憶してゆくので、記憶状態識別フラグＦ０に１がセットされていれば、左，中，右第１種始動口１６，３，１７への入賞が少なくとも１回は検出されていることを意味する（ステップａ７〜ステップａ１３参照）。
【００４７】
そして、記憶状態識別フラグＦ０に１がセットされていれば、ＣＰＵ３２はステップｃ４に移行し、状態記憶フラグＦａに１をセットして変動表示の開始を記憶し、変動表示の選択処理を規定する変動状態記憶フラグＦｂに０をセットして（ステップｃ５）、ｔａ乃至ｔｇのパラメータに予め決められた値を設定することになる（ステップｃ６）。ｔａ乃至ｔｇは、図２３に示すように、左，中，右の各図柄の変動速度の切り替え時間を示す値である。
【００４８】
左，中，右の各図柄の変動速度の切り替え時間を設定したＣＰＵ３２は、次いで、ドットマトリクスＬＥＤ表示体２２の左，中，右，上の各図柄表示ＬＥＤ（Ｌ），（Ｃ），（Ｒ），（Ｕ）の各々に表示すべき図柄を示す表示指標ｉｌ，ｉｃ，ｉｒ，ｉｕの値を連続的にインクリメントして各図柄を高速変動させる処理を開始し（ステップｃ７）、タイマＴを作動させて変動表示開始後の経過時間の測定を開始する（ステップｃ８）。なお、実際の図柄送りは各図柄表示ＬＥＤ（Ｌ），（Ｃ），（Ｒ），（Ｕ）の各行の表示出力を数行ずつ所定周期毎に切り替えることにより、あたかも図柄が上下に流れるように連続的に行われるが、この点に関しては、ＬＥＤ素子等を用いた表示技術として周知であるから説明を省略する。実質的な表示制御手段はＣＰＵ３２と各表示指標ｉｌ，ｉｃ，ｉｒ，ｉｕおよびＬＥＤ表示回路３４により構成される（図７参照）。
【００４９】
次周期以降の処理では既に状態記憶フラグＦａに１がセットされているから、表示制御手段としてのＣＰＵ３２はステップｃ１の判別処理実行後ステップｃ９に移行し、以下、変動状態記憶フラグＦｂの現在値０に応じて、変動表示開始後の経過時間Ｔが設定値ｔａに達するまでの間、ステップｃ１およびステップｃ９乃至ステップｃ１０の判別処理と左，中，右，上の各図柄表示ＬＥＤ（Ｌ），（Ｃ），（Ｒ），（Ｕ）の高速変動に関するステップｃ１１の処理を所定の処理周期で繰り返し実行することとなる。
【００５０】
このようにして各図柄の高速変動処理を繰り返し実行する間に変動表示開始後の経過時間Ｔが設定値ｔａに達すると（ステップｃ１０）、ＣＰＵ３２は乱数ホールド手段である確定乱数記憶レジスタＲ０の値を読み込んで確定値記憶レジスタＲａに格納し（ステップｃ１２）、図２２（ｂ）に示されるように、記憶状態識別フラグＦ１乃至Ｆ３および確定乱数記憶レジスタＲ１乃至Ｒ３のデータを記憶状態識別フラグＦ０乃至Ｆ２および確定乱数記憶レジスタＲ０乃至Ｒ２に順次シフトして、記憶状態識別フラグＦ３および確定乱数記憶レジスタＲ３に０をセットする（ステップｃ１３）。
【００５１】
次いで、ＣＰＵ３２は、確定値記憶レジスタＲａの値が設定値７と一致するか否か、即ち、今回の図柄変動処理の開始刺激となった左，中，右第１種始動口１６，３，１７への入賞検出時にホールドされた乱数の値が大当りに対応する設定値と一致するか否かを判別し（ステップｃ１４）、確定値記憶レジスタＲａの値が設定値と一致すれば、当り図柄記憶手段である左，中，右，上大当たり図柄データ記憶レジスタｒ０ａ乃至ｒ３ａの各値を左，中，右，上表示図柄記憶レジスタｒ０ｃ乃至ｒ３ｃに格納する一方（ステップｃ１５）、確定値記憶レジスタＲａの値が設定値と一致しなければ、外れ図柄記憶手段である左，中，右，上外れ図柄データ記憶レジスタｒ０ｂ乃至ｒ３ｂの各値を左，中，右，上表示図柄記憶レジスタｒ０ｃ乃至ｒ３ｃの各々に格納して（ステップｃ１６）、変動停止時に各図柄表示ＬＥＤに表示すべき図柄を確定する。即ち、左，中，右，上表示図柄記憶レジスタｒ０ｃ乃至ｒ３ｃの各々は最終表示図柄記憶手段であって、ＣＰＵ３２によるステップｃ１２およびステップｃ１４乃至ステップｃ１６の処理は最終表示図柄設定手段に対応する（図７参照）。
【００５２】
次いで、ＣＰＵ３２は、左図柄表示ＬＥＤ（Ｌ）の変動停止時間ｔｃ時に左表示図柄記憶レジスタｒ０ｃの内部処理指標に対応する図柄が表示されるように左図柄に関する表示指標ｉｌの値を設定変更して（ステップｃ１７）、左図柄表示ＬＥＤ（Ｌ）の変動速度を高速変動から中速変動に切り替えると共に（ステップｃ１８）、変動状態記憶フラグＦｂに１をセットして（ステップｃ１９）、この周期の処理を終了する。
【００５３】
ｔａ時における左図柄表示ＬＥＤ（Ｌ）の表示指標ｉｌの値は自明でないが、左図柄表示ＬＥＤ（Ｌ）の中速変動時間ｔｂ−ｔａ＝Ａの値と左図柄表示ＬＥＤ（Ｌ）の低速変動時間ｔｃ−ｔｂ＝Ｂの値は予め設定されており、また、左図柄表示ＬＥＤ（Ｌ）の中速変動時速度と低速変動速度の各々は一定であるから、左図柄表示ＬＥＤ（Ｌ）の変動停止時間ｔｃ時に左図柄表示ＬＥＤ（Ｌ）に表示すべき図柄の表示指標ｒ０ｃの情報のみに基いて、表示指標ｉｌの設定変更値を求めることができる。
【００５４】
実施形態の処理タイミングによれば、高速変動から中速変動への切り替えに際し、表示指標ｉｌの現在値が変動停止時に左図柄表示ＬＥＤ（Ｌ）に表示すべき図柄の表示指標ｒ０ｃよりも２図柄前の表示指標となるようにｉｌの値を設定変更することにより、変動停止時にｒ０ｃの図柄を得ることができる。即ち、ＣＰＵ３２によるステップｃ１７の処理は変動図柄差し替え手段を構成する（図７参照）。
【００５５】
次周期以降の処理では、ＣＰＵ３２はステップｃ１およびステップｃ９の判別処理実行後ステップｃ２０に移行し、以下、変動状態記憶フラグＦｂの現在値１に応じて、変動表示開始後の経過時間Ｔが設定値ｔｂに達するまでの間、ステップｃ１，ステップｃ９およびステップｃ２０乃至ステップｃ２１の判別処理と、左図柄表示ＬＥＤ（Ｌ）の中速変動に関する処理および中，右，上の各図柄表示ＬＥＤ（Ｃ），（Ｒ），（Ｕ）の高速変動に関するステップｃ２２の処理を所定の処理周期で繰り返し実行することとなる。
【００５６】
このようにして各図柄の変動処理を繰り返し実行する間に変動表示開始後の経過時間Ｔが設定値ｔｂに達すると（ステップｃ２１）、ＣＰＵ３２は左図柄表示ＬＥＤ（Ｌ）の変動速度を中速変動から低速変動に切り替えると共に（ステップｃ２３）、変動状態記憶フラグＦｂに２をセットして（ステップｃ２４）、この周期の処理を終了する。
【００５７】
次周期以降の処理では変動状態記憶フラグＦｂの値が２となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０の判別処理実行後ステップｃ２５に移行し、以下、変動状態記憶フラグＦｂの現在値２に応じて、変動表示開始後の経過時間Ｔが設定値ｔｃに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０およびステップｃ２５乃至ステップｃ２６の判別処理と、左図柄表示ＬＥＤ（Ｌ）の低速変動に関する処理および中，右，上の各図柄表示ＬＥＤ（Ｃ），（Ｒ），（Ｕ）の高速変動に関するステップｃ２７の処理を所定の処理周期で繰り返し実行することとなる。
【００５８】
そして、経過時間Ｔが設定値ｔｃに達したことがステップｃ２６の判別処理で検出されると、ＣＰＵ３２は左図柄表示ＬＥＤ（Ｌ）の低速変動を停止し（ステップｃ２８）、変動状態記憶フラグＦｂに３をセットして（ステップｃ２９）、この周期の処理を終了する。左図柄表示ＬＥＤ（Ｌ）の低速変動が停止された時点で、左図柄表示ＬＥＤ（Ｌ）には、左表示図柄記憶レジスタｒ０ｃに記憶された指標に対応する図柄が静止表示されることとなるが、外部ノイズ等の影響で正常な表示制御が阻害されたりすると、変動表示停止時に別の図柄が表示される場合もある。このような場合であっても、表示指標ｉｌの値に基いてＲＯＭ３１から読込まれたデータに基いて図柄が表示されることにかわりはないから、表示指標ｉｌの値と左図柄との関係は常に確保される。
【００５９】
次周期以降の処理では変動状態記憶フラグＦｂの値が３となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０の判別処理実行後ステップｃ３１に移行し、以下、変動状態記憶フラグＦｂの現在値３に応じて、変動表示開始後の経過時間Ｔが設定値ｔｄに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５およびステップｃ３０乃至ステップｃ３１の判別処理と、中，右，上の各図柄表示ＬＥＤ（Ｃ），（Ｒ），（Ｕ）の高速変動に関するステップｃ３２の処理を所定の処理周期で繰り返し実行することとなる。
【００６０】
そして、経過時間Ｔが設定値ｔｄに達したことがステップｃ３１の判別処理で検出されると、ＣＰＵ３２は、中図柄表示ＬＥＤ（Ｃ）の変動停止時間ｔｆ時に中表示図柄記憶レジスタｒ１ｃの内部処理指標に対応する図柄が表示されるように中図柄に関する表示指標ｉｃの値を設定変更して（ステップｃ３３）、中図柄表示ＬＥＤ（Ｃ）の変動速度を高速変動から中速変動に切り替えると共に（ステップｃ３４）、変動状態記憶フラグＦｂに４をセットして（ステップｃ３５）、この周期の処理を終了する。
【００６１】
中図柄表示ＬＥＤ（Ｃ）の中速変動時間ｔｅ−ｔｄ＝Ａの値と低速変動時間ｔｆ−ｔｅ＝Ｂの値は左図柄表示ＬＥＤ（Ｌ）の場合と同様であるから、表示指標ｉｃの設定変更に関する条件も左図柄表示ＬＥＤ（Ｌ）の場合と同様であり、高速変動から中速変動への切り替えに際し、表示指標ｉｃの現在値が変動停止時に中図柄表示ＬＥＤ（Ｃ）に表示すべき図柄の表示指標ｒ１ｃよりも２図柄前の表示指標となるようにｉｃの値を設定変更することにより、変動停止時にｒ１ｃの図柄を得ることができる。即ち、ＣＰＵ３２によるステップｃ３３の処理は変動図柄差し替え手段の一部を構成する（図７参照）。
【００６２】
次周期以降の処理では変動状態記憶フラグＦｂの値が４となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６の判別処理実行後ステップｃ３７に移行し、以下、変動状態記憶フラグＦｂの現在値４に応じて、変動表示開始後の経過時間Ｔが設定値ｔｅに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０およびステップｃ３６乃至ステップｃ３７の判別処理と、中図柄表示ＬＥＤ（Ｃ）の中速変動に関する処理および右，上の各図柄表示ＬＥＤ（Ｒ），（Ｕ）の高速変動に関するステップｃ３８の処理を所定の処理周期で繰り返し実行することとなる。
【００６３】
このようにして各図柄の変動処理を繰り返し実行する間に変動表示開始後の経過時間Ｔが設定値ｔｅに達すると（ステップｃ３７）、ＣＰＵ３２は中図柄表示ＬＥＤ（Ｃ）の変動速度を中速変動から低速変動に切り替えると共に（ステップｃ３９）、変動状態記憶フラグＦｂに５をセットして（ステップｃ４０）、この周期の処理を終了する。
【００６４】
次周期以降の処理では変動状態記憶フラグＦｂの値が５となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１の判別処理実行後ステップｃ４２に移行し、以下、変動状態記憶フラグＦｂの現在値５に応じて、変動表示開始後の経過時間Ｔが設定値ｔｆに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６およびステップｃ４１乃至ステップｃ４２の判別処理と、中図柄表示ＬＥＤ（Ｃ）の低速変動に関する処理および右，上の各図柄表示ＬＥＤ（Ｒ），（Ｕ）の高速変動に関するステップｃ４３の処理を所定の処理周期で繰り返し実行することとなる。
【００６５】
そして、経過時間Ｔが設定値ｔｆに達したことがステップｃ４２の判別処理で検出されると、ＣＰＵ３２は中図柄表示ＬＥＤ（Ｃ）の低速変動を停止し（ステップｃ４４）、変動状態記憶フラグＦｂに６をセットして（ステップｃ４５）、この周期の処理を終了する。中図柄表示ＬＥＤ（Ｃ）の低速変動が停止された時点で、中図柄表示ＬＥＤ（Ｃ）には、中表示図柄記憶レジスタｒ１ｃに記憶された指標に対応する図柄が静止表示されることとなる。また、外部ノイズ等の影響で正常な表示制御が阻害された場合であっても、表示指標ｉｃの値と中図柄との関係は常に確保される。
【００６６】
次周期以降の処理では変動状態記憶フラグＦｂの値が６となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６の判別処理実行後ステップｃ４７に移行し、以下、変動状態記憶フラグＦｂの現在値６に応じて、変動表示開始後の経過時間Ｔが設定値ｔｇに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１およびステップｃ４６乃至ステップｃ４７の判別処理と、右，上の各図柄表示ＬＥＤ（Ｒ），（Ｕ）の高速変動に関するステップｃ４８の処理を所定の処理周期で繰り返し実行することとなる。
【００６７】
そして、経過時間Ｔが設定値ｔｇに達したことがステップｃ４７の判別処理で検出されると、ＣＰＵ３２は、左図柄表示ＬＥＤ（Ｌ）の表示指標ｉｌの現在値と中図柄表示ＬＥＤ（Ｃ）の表示指標ｉｃの現在値とが一致しているか否か、即ち、最終的に表示された左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄とが一致しているか否かを判別し（ステップｃ４９）、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄との一致不一致に応じて、ｔｇ時以降の図柄変動処理に必要とされる各種のデータを設定することとなる。
【００６８】
まず、ステップｃ４９の判別結果が偽となった場合、即ち、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄とが一致していず、大当りの発生する確率が皆無の場合には、ＣＰＵ３２は、右，上各図柄の変動速度の切り替え時間を示すｔｈ乃至ｔｌのパラメータに予め決められた値を設定した後（ステップｃ５０）、右図柄表示ＬＥＤ（Ｒ）の変動停止時間ｔｉ時に右表示図柄記憶レジスタｒ２ｃの内部処理指標に対応する図柄が表示されるように右図柄に関する表示指標ｉｒの値を設定変更して（ステップｃ５１）、右図柄表示ＬＥＤ（Ｒ）の変動速度を高速変動から中速変動に切り替えると共に（ステップｃ５６）、変動状態記憶フラグＦｂに７をセットして（ステップｃ５７）、この周期の処理を終了する。
【００６９】
右図柄表示ＬＥＤ（Ｒ）の中速変動時間ｔｈ−ｔｇ＝Ｃの値と右図柄表示ＬＥＤ（Ｒ）の低速変動時間ｔｉ−ｔｈ＝Ｄの値は固定的であるから、右図柄表示ＬＥＤ（Ｒ）の変動停止時間ｔｉ時に右図柄表示ＬＥＤ（Ｒ）に表示すべき図柄の表示指標ｒ２ｃの情報のみに基いて、表示指標ｉｒの設定変更値を求めることができる。実施形態の処理タイミングによれば、高速変動から中速変動への切り替えに際し、表示指標ｉｒの現在値が変動停止時に右図柄表示ＬＥＤ（Ｒ）に表示すべき図柄の表示指標ｒ２ｃよりも２図柄前の表示指標となるようにｉｒの値を設定変更することにより、変動停止時にｒ２ｃの図柄を得ることができる。従って、ＣＰＵ３２によるステップｃ５１の処理は変動図柄差し替え手段の一部である（図７参照）。
【００７０】
また、ステップｃ４９の判別結果が真となった場合、即ち、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄とが一致しており、大当りの発生する可能性のある場合には、２図柄リーチ状態となる。ＣＰＵ３２は、右図柄に関する表示指標ｉｒの現在値を特定の値３に設定変更した後（ステップｃ５２）、変動時間用乱数記憶レジスタＲＡＮ２の値と変動停止時に表示すべき表示指標ｒ２ｃの情報に基いてｔｈ乃至ｔｊのパラメータを選択的に設定することとなる（ステップｃ５３〜ステップｃ５５）。
【００７１】
即ち、変動時間用乱数記憶レジスタＲＡＮ２の値が０であった場合には表６に示されるようなＲＯＭ３１の選択条件ファイルに基いて、変動停止時に表示すべき図柄の表示指標ｒ２ｃに対応する変動時間Ｃを選択してパラメータｔｈにｔｇ＋Ｃを設定し（ステップｃ５４）、また、変動時間用乱数記憶レジスタＲＡＮ２の値が１であった場合には表７に示されるようなＲＯＭ３１の選択条件ファイルに基いて、変動停止時に表示すべき図柄の表示指標ｒ２ｃに対応する変動時間Ｃを選択してパラメータｔｈにｔｇ＋Ｃを設定し、パラメータｔｈの値に予め決められた一定の値を加えてパラメータｔｉおよびｔｊの値を設定する（ステップｃ５５）。
【００７２】
【表６】

【００７３】
【表７】

【００７４】
従って、変動時間用乱数記憶レジスタＲＡＮ２の値が０で、かつ、変動停止時に表示すべき図柄の表示指標ｒ２ｃの値が０の場合であれば、変動時間Ｃとして表６から３．１０４ｓが選択され、パラメータｔｈの値はｔｇ＋Ｃ＝１０．０１６ｓとなり、また、変動時間用乱数記憶レジスタＲＡＮ２の値が１で、かつ、変動停止時に表示すべき図柄の表示指標ｒ２ｃの値が１５の場合であれば、変動時間Ｃとして表７から１１．０４０ｓが選択され、パラメータｔｈの値はｔｇ＋Ｃ＝１７．９５２ｓとなる。
【００７５】
つまり、ステップｃ５４およびステップｃ５５の処理は、ステップｃ１７，ステップｃ３３およびステップｃ５１に示される処理のように中速および低速時の変動時間を一定として変動停止時に表示すべき図柄の表示指標ｒ２ｃの値に対応して中速変動開始時における表示指標ｉｒの値を再設定するかわりに、中速変動開始時における表示指標ｉｒの値を特定の値に決めて変動停止時に表示すべき図柄の表示指標ｒ２ｃの値に対応して中速および低速の変動時間を設定するものであり、これらステップｃ５２，ステップｃ５４およびステップｃ５５の処理も変動図柄差し替え手段の一部である。なお、表６および表７に示す変動時間Ｃの値は実施形態の処理タイミングに基いて一例を示すものであり、変動時間等を制限するものではない。
【００７６】
そして、ステップｃ５４もしくはステップｃ５５の処理でｔｈ乃至ｔｊのパラメータを設定したＣＰＵ３２は、右図柄表示ＬＥＤ（Ｒ）の変動速度を高速変動から中速変動に切り替えた後（ステップｃ５６）、変動状態記憶フラグＦｂに７をセットして（ステップｃ５７）、この周期の処理を終了する。
【００７７】
変動状態記憶フラグＦｂに７がセットされる結果、次周期以降の処理では、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８の判別処理実行後、ＣＰＵ３２はステップｃ５９に移行し、以下、変動状態記憶フラグＦｂの現在値７に応じて、変動表示開始後の経過時間Ｔが設定値ｔｈに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６およびステップｃ５８乃至ステップｃ５９の判別処理と、右図柄表示ＬＥＤ（Ｒ）の中速変動と上図柄表示ＬＥＤ（Ｕ）の高速変動に関するステップｃ６０の処理を所定の処理周期で繰り返し実行することとなる。
【００７８】
このようにして各図柄の変動処理を繰り返し実行する間に変動表示開始後の経過時間Ｔが設定値ｔｈに達すると（ステップｃ５９）、ＣＰＵ３２は右図柄表示ＬＥＤ（Ｒ）の変動速度を中速変動から低速変動に切り替えると共に（ステップｃ６１）、変動状態記憶フラグＦｂに８をセットして（ステップｃ６２）、この周期の処理を終了する。
【００７９】
次周期以降の処理では変動状態記憶フラグＦｂの値が８となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３の判別処理実行後ステップｃ６４に移行し、以下、変動状態記憶フラグＦｂの現在値８に応じて、変動表示開始後の経過時間Ｔが設定値ｔｉに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８およびステップｃ６３乃至ステップｃ６４の判別処理と、右図柄表示ＬＥＤ（Ｒ）の低速変動と上図柄表示ＬＥＤ（Ｕ）の高速変動に関するステップｃ６５の処理を所定の処理周期で繰り返し実行することとなる。
【００８０】
そして、経過時間Ｔが設定値ｔｉに達したことがステップｃ６４の判別処理で検出されると、ＣＰＵ３２は右図柄表示ＬＥＤ（Ｒ）の低速変動を停止し（ステップｃ６６）、変動状態記憶フラグＦｂに９をセットして（ステップｃ６７）、この周期の処理を終了する。右図柄表示ＬＥＤ（Ｒ）の低速変動が停止された時点で、右中図柄表示ＬＥＤ（Ｒ）には、右表示図柄記憶レジスタｒ２ｃに記憶された指標に対応する図柄が静止表示されることとなる。また、外部ノイズ等の影響で正常な表示制御が阻害された場合であっても、表示指標ｉｒの値と右図柄との関係は常に確保される。
【００８１】
次周期以降の処理では変動状態記憶フラグＦｂの値が９となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８の判別処理実行後ステップｃ６９に移行し、以下、変動状態記憶フラグＦｂの現在値９に応じて、変動表示開始後の経過時間Ｔが設定値ｔｊに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３およびステップｃ６８乃至ステップｃ６９の判別処理と、上図柄表示ＬＥＤ（Ｕ）の高速変動に関するステップｃ７０の処理を所定の処理周期で繰り返し実行することとなる。
【００８２】
そして、経過時間Ｔが設定値ｔｊに達したことがステップｃ６９の判別処理で検出されると、ＣＰＵ３２は、左図柄表示ＬＥＤ（Ｌ）の表示指標ｉｌの現在値と中図柄表示ＬＥＤ（Ｃ）の表示指標ｉｃの現在値とが一致しているか否か、即ち、最終的に表示された左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄とが一致しているか否か（ステップｃ７１）、および、左図柄表示ＬＥＤ（Ｌ）の表示指標ｉｌの現在値と右図柄表示ＬＥＤ（Ｒ）の表示指標ｉｒの現在値とが一致しているか否か、即ち、最終的に表示された左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄および右図柄表示ＬＥＤ（Ｒ）の停止図柄が全て一致しているか否かを判別し（ステップｃ７５）、図柄の一致不一致に応じて、ｔｊ時以降の図柄変動処理に必要とされる各種のデータを設定することとなる。
【００８３】
まず、ステップｃ７１の判別結果が偽となった場合、即ち、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄とが一致していない場合には、ＣＰＵ３２は、ステップｃ５０の処理で設定された変動時間の確定値ｔｋ，ｔｌに基き、上図柄表示ＬＥＤ（Ｕ）の変動停止時間ｔｌ時に上表示図柄記憶レジスタｒ３ｃの内部処理指標に対応する図柄が表示されるように、上図柄に関する表示指標ｉｕの値を設定変更して（ステップｃ７２）、上図柄表示ＬＥＤ（Ｕ）の変動速度を高速変動から中速変動に切り替えると共に（ステップｃ７３）、変動状態記憶フラグＦｂに１０をセットして（ステップｃ７４）、この周期の処理を終了する。
【００８４】
この場合、上図柄表示ＬＥＤ（Ｕ）の中速変動時間ｔｋ−ｔｊ＝Ｅの値と上図柄表示ＬＥＤ（Ｕ）の低速変動時間ｔｌ−ｔｋ＝Ｆの値は固定的であるから、上図柄表示ＬＥＤ（Ｕ）の変動停止時間ｔｌ時に上図柄表示ＬＥＤ（Ｕ）に表示すべき図柄の表示指標ｒ３ｃの情報のみに基いて、表示指標ｉｕの設定変更値を求めることができる。この場合は、左図柄表示ＬＥＤ（Ｌ）や中図柄表示ＬＥＤ（Ｃ）の場合と同様、変動停止時に表示すべき表示指標ｒ３ｃよりも２図柄前の値に表示指標ｉｕの値を設定変更することとなる。ＣＰＵ３２によるステップｃ７２の処理も変動図柄差し替え手段の一部である（図７参照）。
【００８５】
また、ステップｃ７１の判別結果が真であって、かつ、ステップｃ７５の判別結果が偽となった場合、即ち、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄のみが一致している場合には、ＣＰＵ３２は、ステップｃ５４もしくはステップｃ５５で設定されたｔｊの値と予め決められた中速変動時間Ｅおよび低速変動時間Ｆに基いて変動時間ｔｋ，ｔｌを設定し（ステップｃ７６）、上図柄表示ＬＥＤ（Ｕ）の変動停止時間ｔｌ時に上表示図柄記憶レジスタｒ３ｃの内部処理指標に対応する図柄が表示されるように、上図柄に関する表示指標ｉｕの値を設定変更する（ステップｃ７２）。この場合も、上図柄表示ＬＥＤ（Ｕ）の中速変動時間Ｅの値と上図柄表示ＬＥＤ（Ｕ）の低速変動時間Ｆの値は固定的であるから、前記と同様、変動停止時に表示すべき表示指標ｒ３ｃよりも２図柄前の値に表示指標ｉｕの値を設定変更することにより所望の停止図柄を得ることができる。
【００８６】
なお、表５を用いて大当りとなる図柄の組合せについて前述したように、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄が一致し、左図柄表示ＬＥＤ（Ｌ）の停止図柄と右図柄表示ＬＥＤ（Ｒ）の停止図柄が一致していない場合であっても、右図柄表示ＬＥＤ（Ｒ）の停止図柄が、左図柄表示ＬＥＤ（Ｌ）の停止図柄よりも１つだけ小さい場合に限り、大当りとなる図柄の一部に一致して大当りの発生する可能性があることとなる。
【００８７】
これに対し、ステップｃ７１およびステップｃ７５の判別結果が共に真となった場合、即ち、左図柄表示ＬＥＤ（Ｌ）の停止図柄と中図柄表示ＬＥＤ（Ｃ）の停止図柄および右図柄表示ＬＥＤ（Ｒ）の停止図柄が全て一致した場合には、大当りの発生する可能性があることとなる。ＣＰＵ３２はステップｃ７７に移行して、上図柄に関する表示指標ｉｕの現在値を特定の値１に設定変更した後、表８に示されるようなＲＯＭ３１の選択条件ファイルに基いて、変動停止時に表示すべき図柄の表示指標ｒ３ｃに対応する変動時間Ｅを選択してパラメータｔｋにｔｊ＋Ｅを設定し、更に、パラメータｔｋの値に予め決められた一定の値を加えてパラメータｔｌの値を設定する（ステップｃ７８）。
【００８８】
【表８】

【００８９】
ステップｃ７７，ステップｃ７８の処理は、中速変動開始時における表示指標ｉｕの値を特定の値に決め、変動停止時に表示すべき図柄の表示指標ｒ３ｃの値に対応して中速および低速の変動時間を設定するものであり、その処理方式は、前記のステップｃ５２とステップｃ５４，ステップｃ５５の処理と同様であり、ステップｃ７７，ステップｃ７８の処理も変動図柄差し替え手段の一部である。なお、表８に示す変動時間Ｅの値は実施形態の処理タイミングに基いて一例を示すものであり、変動時間等を制限するものではない。
【００９０】
そして、ステップｃ７８の処理でｔｋ，ｔｌのパラメータを設定したＣＰＵ３２は、上図柄表示ＬＥＤ（Ｕ）の変動速度を高速変動から中速変動に切り替えると共に（ステップｃ７３）、変動状態記憶フラグＦｂに１０をセットして（ステップｃ７４）、この周期の処理を終了する。
【００９１】
変動状態記憶フラグＦｂに１０がセットされる結果、次周期以降の処理では、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８，ステップｃ７９の判別処理実行後、ＣＰＵ３２はステップｃ８０に移行し、以下、変動状態記憶フラグＦｂの現在値１０に応じて、変動表示開始後の経過時間Ｔが設定値ｔｋに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８およびステップｃ７９乃至ステップｃ８０の判別処理と、上図柄表示ＬＥＤ（Ｕ）の中速変動に関するステップｃ８１の処理を所定の処理周期で繰り返し実行することとなる。
【００９２】
このようにして上図柄の中速変動処理を繰り返し実行する間に変動表示開始後の経過時間Ｔが設定値ｔｋに達すると（ステップｃ８０）、ＣＰＵ３２は上図柄表示ＬＥＤ（Ｕ）の変動速度を中速変動から低速変動に切り替えると共に（ステップｃ８２）、変動状態記憶フラグＦｂに１１をセットして（ステップｃ８３）、この周期の処理を終了する。
【００９３】
次周期以降の処理では変動状態記憶フラグＦｂの値が１１となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８，ステップｃ７９，ステップｃ８４の判別処理実行後ステップｃ８５に移行し、以下、変動状態記憶フラグＦｂの現在値１１に応じて、変動表示開始後の経過時間Ｔが設定値ｔｌに達するまでの間、ステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８，ステップｃ７９およびステップｃ８４乃至ステップｃ８５の判別処理と、上図柄表示ＬＥＤ（Ｕ）の低速変動に関するステップｃ８６の処理を所定の処理周期で繰り返し実行することとなる。
【００９４】
次いで、経過時間Ｔが設定値ｔｌに達したことがステップｃ８５の判別処理で検出されると、ＣＰＵ３２は上図柄表示ＬＥＤ（Ｕ）の低速変動を停止し（ステップｃ８７）、上表示図柄記憶レジスタｒ３ｃに記憶された指標に対応する図柄を静止表示する。また、外部ノイズ等の影響で正常な表示制御が阻害された場合であっても、表示指標ｉｕの値と上図柄との関係は常に確保される。
【００９５】
そして、全ての図柄の変動表示を終了したＣＰＵ３２は、表示指標ｉｌ，ｉｃ，ｉｒ，ｉｕの現在値に基いて左，中，右，上の各図柄表示ＬＥＤ（Ｌ），（Ｃ），（Ｒ），（Ｕ）の組合わせが表５に示すような当り図柄の組合わせと一致しているか否かを判別し（ステップｃ８８）、当り図柄の組合わせであれば変動状態記憶フラグＦｂに１２を設定し（ステップｃ８９）、タイマＴａに点灯切替え周期を設定して計時を開始し（ステップｃ９０）、切替え回数記憶レジスタＣを初期化する（ステップｃ９１）。また、当り図柄の組合わせでなければ、状態記憶フラグＦａおよび変動状態記憶フラグＦｂの値を初期化して（ステップｃ９２，ステップｃ９３）、この周期の処理を終了する。ＣＰＵ３２によるステップｃ８８の判別処理は実質上の最終判定手段である（図７参照）。
【００９６】
この実施形態においては左，中，右第１種始動口１６，３，１７への入賞検出時におけるステップａ１２の処理で大当り用乱数記憶レジスタＲＡＮ１の現在値が確定乱数記憶レジスタＲｉに記憶された時点で確定乱数記憶レジスタＲｉの値が設定値７と一致するか否かによって大当りの発生の有無が既に決定され、また、ステップｃ１７の処理で左図柄表示ＬＥＤ（Ｌ）の中速変動表示が開始される時点ではステップｃ１４乃至ステップｃ１６の処理により大当り図柄の組合わせや外れ図柄の組合わせが確定されているが、外部ノイズ等の影響で正常な表示制御が阻害され、最終的に表示される図柄に狂いが生じることも考えられる。
【００９７】
しかし、本実施形態においては、最終的な図柄組合わせの判定に際し、予め確定された図柄組合わせのかわりに、変動表示停止時の図柄に対応する表示指標ｉｌ，ｉｃ，ｉｒ，ｉｕの現在値を用いるにようにしているので、表示図柄に狂いを生じたような場合であっても、実際に表示された図柄の組合わせに対応した的確な判定を行うことができる。
【００９８】
実施形態において大当りの発生する確率は、大当りに対応する設定値の範囲を大当り用乱数記憶レジスタＲＡＮ１の値域で除した値であり、この例では、大当りに対応する設定値の値が７のみであって、大当り用乱数記憶レジスタＲＡＮ１の取り得る値が０乃至２０４の整数であるから、大当りの発生する確率は１／２０５（０．９７５／２００）となる。従って、表１乃至表４に示される各図柄を表記した４つの回転ドラムを有し、表５に示すような条件を当り図柄の組合わせとして設定した機械式回転ドラム型の図柄表示装置の大当り発生確率７０／１４４００（０．９７２／２００）と略一致するが、ステップａ２の判別処理で用いられる比較値の値を変更したり、ステップｃ１４の判別処理で用いられる比較値の値を領域として設定したりすることにより、大当りの発生確率を任意に操作することができる。
【００９９】
例えば、ステップａ２の判別処理で用いられる比較値の値を２１０とすれば大当りの発生する確率は１／２１０（０．９５２／２００）となり、また、ステップｃ１４の判別処理で用いられる比較値の値Ｘを５＜Ｘ＜８の領域として設定すると大当りの発生する確率は２／２０５（１．９５１／２００）となる。
【０１００】
このような操作は大当りの発生する確率に影響を与えるのみであって、大当り図柄や外れ図柄の内容自体はタスク２の処理により、左，中，右，上大当たり図柄データ記憶レジスタｒ０ａ乃至ｒ３ａおよび左，中，右，上外れ図柄データ記憶レジスタｒ０ｂ乃至ｒ３ｂの各々にランダムに設定されるから、特定の図柄の組合わせが出易くなるようなことはなく、違和感がない。
【０１０１】
そして、最終的な表示図柄の組合わせが大当りとなった場合、次周期以降の処理では変動状態記憶フラグＦｂの値が１２となるから、ＣＰＵ３２はステップｃ１，ステップｃ９，ステップｃ２０，ステップｃ２５，ステップｃ３０，ステップｃ３６，ステップｃ４１，ステップｃ４６，ステップｃ５８，ステップｃ６３，ステップｃ６８，ステップｃ７９，ステップｃ８４の判別処理実行後ステップｃ９４に移行し、以下、タイマＴａの設定時間が経過する毎にステップｃ９５乃至ステップｃ９８の表示切り替え処理を繰り返し実行することとなる。
【０１０２】
表示切り替え処理を開始したＣＰＵ３２は切替え回数記憶レジスタＣの値をインクリメントした後（ステップｃ９５）、表示切替え処理の実行回数が設定値Ｎに達したか否かを判別し（ステップｃ９６）、表示切替え処理の実行回数が設定値Ｎの範囲内にあれば、以下、タイマＴａの設定時間が経過する毎に、ドットマトリクスＬＥＤ表示体２２の図柄表示ＬＥＤ（Ｌ），（Ｃ），（Ｒ）とドットマトリクスＬＥＤ表示体２３の図柄表示ＬＥＤ（ｌ），（ｃ），（ｒ）との間で大当り図柄の表示出力を交互に切り替えて、あたかも大当り図柄が前後に移動しているように表示し（ステップｃ９７）、タイマＴａに点灯切替え周期を再設定して（ステップｃ９８）、切替え回数記憶レジスタＣの値が設定値Ｎに達するまでの間、この表示切り替え処理を繰り返し実行する。
【０１０３】
そして、表示切り替え処理の実行回数が設定値Ｎに達したことがステップｃ９６の判別処理で検出されると、ＣＰＵ３２は切替え回数記憶レジスタＣおよび変動状態記憶フラグＦｂの値を初期化し（ステップｃ９９，ステップ１００）、状態記憶フラグＦａに２を設定して（ステップ１０１）、大入賞口１５の開放に関するタスク４の処理の実行を許可する。なお、切替え回数記憶レジスタＣの値が設定値Ｎに達した段階では大当りの図柄表示がドットマトリクスＬＥＤ表示体２３の側に復帰する。
【０１０４】
図２１はタスク４の処理の概略を示すフローチャートである。状態記憶フラグＦａに２が設定されると、ＣＰＵ３２はステップｄ１の判別処理実行後ステップｄ２に移行し、ソレノイド等で開閉駆動されるアタッカ状の大入賞口１５の開閉操作を開始し、所定の開放時間の経過もしくは大入賞口１５への遊技球の入賞個数の検出等に基く開閉動作の終了条件が成立するまでの間、所定の処理周期でステップｄ２の開閉処理を繰り返し実行し、ステップｄ３の判別処理で終了条件の成立が検出されると、ステップｄ４の処理で大入賞口１５を閉鎖して１開放動作を終了し、ステップｄ５の処理で状態記憶フラグＦａの値を初期化する。
【０１０５】
タスク３またはタスク４の処理で状態記憶フラグＦａの値が初期化される結果、次周期以降のステップｃ１およびステップｃ２の判別結果は共に偽となり、記憶状態識別フラグＦ０の値が再度ＣＰＵ３２により検出されることとなる（ステップｃ３）。
【０１０６】
従って、左，右，中第一種始動口１６，３，１７への再度の入賞検出により確定乱数記憶レジスタＲ０に乱数が新たに記憶された場合や、複数の入賞検出によって確定乱数記憶レジスタＲ１以降に記憶された値がシフトされたような場合には、ステップｃ４以降の処理により再度の図柄合わせ処理が、第１回目を含め、最高４回まで続けて開始されることとなる。
【０１０７】
【発明の効果】
請求項１に記載の構成によれば、図柄表示制御手段は、判定手段による判定結果がはずれであり、はずれ停止図柄組合せの設定を行う場合には、はずれ図柄組合せ記憶手段に記憶されているはずれ図柄組合せを設定し、該はずれ図柄組合せが停止表示されるように制御する一方、設定された停止図柄組合せが予め定めたリーチ状態となる場合には、第１のリーチ状態で図柄を変動表示した後、第１のリーチ状態におけるはずれ図柄組合せを表示し、その後第２のリーチ状態で図柄を変動表示した後で、設定された停止図柄組合せが停止表示されるように制御するので、はずれ図柄を停止表示する場合に図柄表示制御手段による図柄変動表示処理とは別のタイミングで実行される別処理によって作成記憶されているはずれ図柄がそのまま使用されるので、変動中に停止図柄を選択したり停止図柄の補正を行ったりする面倒な処理を行う必要がなく確実にはずれ図柄の停止表示を行うことができる。また、設定された停止図柄組合せが予め定めたリーチ状態となる場合には、２段階のリーチ状態を表示し得るので、遊技者の大当りに対する期待感を維持させることができ、遊技の興趣を向上させることができる。
【図面の簡単な説明】
【図１】 本発明の一実施形態におけるパチンコ機の図柄表示装置の要部を示す側断面図
【図２】 同実施形態のパチンコ機の図柄表示装置を装着した遊技盤を示す正面図
【図３】 同実施形態の図柄表示手段の一部を構成するドットマトリクスＬＥＤ表示体を示す平面図
【図４】 同実施形態の図柄表示手段の一部を構成する別のドットマトリクスＬＥＤ表示体を示す平面図
【図５】 ドットマトリクスＬＥＤ表示体の視認状態の一例を示す図
【図６】 同実施形態のパチンコ機の図柄表示装置の制御部を示す要部ブロック図
【図７】 機能実現手段としてのＣＰＵを示す機能ブロック図
【図８】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図９】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１０】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１１】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１２】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１３】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１４】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１５】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１６】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１７】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１８】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図１９】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図２０】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図２１】 同実施形態のＣＰＵによる処理の一部を示すフローチャート
【図２２】 乱数ホールド手段としての確定乱数記憶レジスタＲｉの記憶動作を示す作用原理図
【図２３】 同実施形態のパチンコ機の図柄表示装置における図柄変動処理を示すタイミングチャート
【符号の説明】
１ 遊技盤
２ 図柄表示装置の要部を構成する図柄表示ユニット
３ 始動信号発生手段としての中第１種始動口
１６ 始動信号発生手段としての左第１種始動口
１７ 始動信号発生手段としての右第１種始動口
２２ 図柄表示手段を構成するドットマトリクスＬＥＤ表示体
２３ 図柄表示手段を構成するドットマトリクスＬＥＤ表示体
３２ 機能実現手段としてのＣＰＵ
ｒ０ 組合わせ図柄発生手段を構成する左図柄データ記憶レジスタ
ｒ１ 組合わせ図柄発生手段を構成する中図柄データ記憶レジスタ
ｒ２ 組合わせ図柄発生手段を構成する右図柄データ記憶レジスタ
ｒ３ 組合わせ図柄発生手段を構成する上図柄データ記憶レジスタ
ｒ０ａ 当り図柄記憶手段を構成する左大当り図柄データ記憶レジスタ
ｒ１ａ 当り図柄記憶手段を構成する中大当り図柄データ記憶レジスタ
ｒ２ａ 当り図柄記憶手段を構成する右大当り図柄データ記憶レジスタ
ｒ３ａ 当り図柄記憶手段を構成する上大当り図柄データ記憶レジスタ
ｒ０ｂ 外れ図柄記憶手段を構成する左外れ図柄データ記憶レジスタ
ｒ１ｂ 外れ図柄記憶手段を構成する中外れ図柄データ記憶レジスタ
ｒ２ｂ 外れ図柄記憶手段を構成する右外れ図柄データ記憶レジスタ
ｒ３ｂ 外れ図柄記憶手段を構成する上外れ図柄データ記憶レジスタ
ＲＡＮ１ 乱数発生手段を構成する大当り用乱数記憶レジスタ
Ｒｉ 乱数ホールド手段を構成する確定乱数記憶レジスタ
ｒ０ｃ 最終表示図柄記憶手段を構成する左表示図柄記憶レジスタ
ｒ１ｃ 最終表示図柄記憶手段を構成する中表示図柄記憶レジスタ
ｒ２ｃ 最終表示図柄記憶手段を構成する右表示図柄記憶レジスタ
ｒ３ｃ 最終表示図柄記憶手段を構成する上表示図柄記憶レジスタ
ｉｌ 表示指標
ｉｃ 表示指標
ｉｒ 表示指標
ｉｕ 表示指標[0001]
BACKGROUND OF THE INVENTION
The present invention includes a symbol display device, displays a plurality of symbols displayed on the symbol display device in a variable manner upon detection of a ball entering a specific mouth, and is provided on the condition that the symbols are displayed as winning symbols. Jackpot Pachinko machine About.
[0002]
[Prior art]
A symbol display device of a pachinko machine using a slot machine-like symbol display means by a mechanical rotary drum is well known.
[0003]
In addition, a symbol display means composed of a dot matrix LED or the like is provided on the game board surface of the pachinko machine, and a plurality of symbols are displayed on each of the symbol display means in response to a signal from a winning detection switch provided at the first type starting port. A symbol display device for a pachinko machine that is displayed in a cyclic manner for a predetermined time has already been proposed by the present applicant as JP-A-1-136680.
[0004]
These symbol display devices are designed to determine whether or not a symbol is missed depending on whether or not the symbols displayed on each symbol display means are in a specific combination when the symbol variation display ends. However, in the case where a plurality of symbols display forms a part of the symbol from the time when the symbol variation display is started until the symbol variation display ends (in this specification, a plurality of symbols are displayed). When the display mode is a part of the winning symbol, it is referred to as a reach state), and the player's expectation for the big hit is increased.
[0005]
In the conventional gaming machine, when the symbol is in the reach state in the symbol display device, the reach state is only once during one symbol change. For this reason, when reaching the reach state, the expectation for the big hit will be high, but at the stage when the reach state is over, if the player wins, the player may get drunk with a sense of satisfaction and achievement, but not a hit When it becomes clear, the expectation for the jackpot disappears all at once, and the degree of disappointment is also great.
[0006]
[Problems to be solved by the invention]
An object of the present invention is to provide a symbol display device. If you reach a reach but not a big hit, Expectation of player's big hit Last Can improve the interest of the game Pachinko machine Is to provide.
[0007]
[Means for Solving the Problems]
The pachinko machine according to claim 1 is provided with a symbol display device, and a plurality of symbols displayed on the symbol display device are variably displayed by detecting a ball entering the start opening. combination In order to solve the above problem, In response to detection of a ball entering the starting port According to the determination means for determining whether or not the big hit, and the determination result by the determination means Stopped on the symbol display device Stop pattern combination And setting the plurality of symbols in the variable display to the set stop symbols. combination The symbol display control means for stopping and displaying at The symbol combination creating step of creating the stop symbol combination by a separate process executed at a timing different from the symbol variation display process by the symbol display control means, and whether or not the created stop symbol combination is an out symbol combination Stop symbol combination creating processing means comprising: a symbol combination determining step for determining the symbol combination and a symbol combination storing step for storing the missing symbol combination in the symbol combination storing means if the determination result is a missing symbol combination; The symbol display control means comprises: When the determination result by the determination means is out of order and setting of the stop symbol combination is performed, the off symbol combination stored in the off symbol combination storage unit is set, and the off symbol combination is stopped and displayed. On the other hand, when the set stop symbol combination is in a predetermined reach state, the symbols are variably displayed in the first reach state, and then the off-set symbol combination in the first reach state is displayed. Then, after the symbols are variably displayed in the second reach state, control is performed so that the set stop symbol combination is stopped and displayed. It is characterized by that.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a front view showing a game board of a pachinko machine according to one embodiment, and a symbol display unit 2 constituting a main part of the symbol display device of the pachinko machine according to the present invention is arranged at a substantially central portion of the game board 1. Furthermore, a middle first type starting port 3 constituting a part of the starting signal generating means in the symbol display device is disposed at the lower center of the game board 1.
[0013]
In FIG. 2, reference numeral 4 is a left shoulder winning opening, reference numeral 5 is a right shoulder winning opening, reference numeral 6 is a left tulip type accessory, reference numeral 7 is a right tulip type accessory, reference numeral 8 is a windmill with a lamp, reference numeral 9 is a windmill, reference numeral Reference numeral 10 denotes a decorative indicator lamp, reference numeral 11 denotes an out-ball socket, reference numeral 12 denotes a ball guide rail, and reference numeral 13 denotes a return rubber. However, since these elements are well known, description thereof will be omitted.
[0014]
Reference numeral 14 in FIG. 2 is a winning device that is linked to the symbol display device, and an attacker-like large winning opening 15 that is opened and closed by a solenoid or the like is provided at a substantially central portion thereof, and on both sides of the large winning opening 15. A left first type start port 16 and a right first type start port 17 that constitute part of the start signal generating means together with the middle first type start port 3 are arranged. Inside the middle first type starting port 3, the left first type starting port 16 and the right first type starting port 17, the middle first type starting port winning detection switch SW1 constituting the main part of the starting signal generating means and the left Each of the first type start port winning detection switch SW2 and the right first type start port winning detection switch SW3 is provided.
[0015]
The inside of the big winning opening 15 in the winning device 14 is divided into three winning areas by game ball distributing pieces 18 and 19, and the big winning opening 15 is provided in the central winning area having the game ball dividing pieces 18 and 19 on both sides. A specific area winning detection switch SW4 is provided as an accessory continuous operation device that is continuously opened. Under the winning device 14, a continuous number display LED 20 that displays the number of consecutive opening of the big winning opening 15 by the specific area winning detection switch SW4 and a winning opening that numerically displays the number of winnings during one opening operation of the big winning opening 15 are displayed. A winning number display LED 21 is arranged.
[0016]
The continuous opening operation of the special winning opening 15 is up to 16 times in total including the first opening operation based on the symbol matching of the symbol display unit 2 and the continuous opening operation by the operation of the specific area winning detection switch SW4. The duration of one opening operation of the big winning opening 15 is set to 29.5 seconds. However, when the total number of game balls won in the big winning opening 15 during one opening operation exceeds 10, One open operation is completed upon detection of the first winning prize.
[0017]
FIG. 1 is a side sectional view showing the symbol display unit 2 divided vertically in the center. The symbol display unit 2 is arranged with respect to the dot matrix LED display 22 and the game board surface arranged substantially at right angles to the game board surface. And a symbol display means comprising a dot matrix LED display body 23 arranged substantially in parallel, and a symbol display by the dot matrix LED display body 23 and a mirror image of the symbol display by the dot matrix LED display body 22 are both of the game board 1. A half mirror 24 is disposed at a position where it can be seen from the front.
[0018]
FIG. 3 is a plan view showing the dot matrix LED display body 22 from the display surface 22b side with the edge 22a of the substantially rectangular dot matrix LED display body 22 facing upward, and the LEDs constituting the dot matrix LED display body 22 Left symbol display by 64 elements from 1 row 1 column to 8 rows and 8 columns, 64 elements from 1 row 9 columns to 8 rows and 16 columns, and 64 elements from 1 row 17 columns to 8 rows and 24 columns The LED (L), the middle symbol display LED (C), and the right symbol display LED (R) are configured, and the upper symbol display LED (by the 128 elements from the 9th row 1st column to the 16th row 24th column) of the dot matrix LED display 22 ( U) is configured.
[0019]
FIG. 4 is a plan view showing the dot matrix LED display body 23 as viewed from the front of the game board 1. The LED elements constituting the dot matrix LED display body 23 are 64 elements from 1 row 1 column to 8 rows 8 columns, and Each of 64 elements from 1 row 9 columns to 8 rows 16 columns and 64 elements from 1 row 17 columns to 8 rows 24 columns, left symbol display LED (l), middle symbol display LED (c) and right symbol display LED (r) is configured.
[0020]
The dot matrix LED display body 22 and the dot matrix LED display body 23 and the half mirror 24 are respectively left, middle and right symbol display by the dot matrix LED display body 23 and left, middle and right by the dot matrix LED display body 22. The position is set so that the mirror image of the symbol display appears to overlap. Reference numeral 30 denotes a transparent cover member that protects the display surface of the dot matrix LED display 22.
[0021]
The distance from each of the left, middle and right symbol display LEDs (l), (c) and (r) of the dot matrix LED display body 23 to the half mirror 24 is the left, middle and right of the dot matrix LED display body 22. When the half mirror 24 is visually recognized from the front of the game board 1, it is shorter than the distance from each of the symbol display LEDs (L), (C), (R) to the reflecting surface of the half mirror 24. The left, middle and right symbols of the display body 23 appear to be in front of the left, middle and right symbols of the dot matrix LED display body 22, and the upper symbol display by the dot matrix LED display body 22 is There is no interference with the left, middle and right symbol display by the dot matrix LED display 23 (see FIG. 1).
[0022]
As an example, “BB” is displayed on the upper symbol display LED (U) of the dot matrix LED display body 22, and the left, middle and right symbol display LEDs (l), (c) of the dot matrix LED display body 23 are displayed. ) And (r) are shown in FIG. 5 when “7” is displayed.
[0023]
The symbol display unit 2 includes a top prize opening 25 at the top thereof, and a character display LED 26 and a memory number display LED 27 are disposed at the lower rear portion of the half mirror 24. The memory number display LED 27 displays the number of game balls won in the left, right and middle first-class start ports 16, 3 and 17 during the symbol variation display or the large winning port 15 opening operation, The number of lights is displayed up to four times, and the character display LED 26 informs the player of the function of the memory number display LED 27 by displaying characters such as “MEMORY”. In addition, an arch-shaped game ball distributing portion 29 is projected on the upper edge of the substantially rectangular viewing window 28 formed in front of the half mirror 24 in the symbol display unit 2 to prevent visual disturbance due to rolling of the game ball. Inadvertent entry of game balls into the symbol display unit 2 is prevented.
[0024]
The control unit of the symbol display device drives each part of the symbol display unit 2 according to the ROM 30 storing the control program of the symbol display unit 2 and display symbol data, the RAM 31 used for temporary storage of data, and the ROM 30 control program. It is comprised by CPU32 which controls (refer FIG. 6). Note that ROM here does not mean storage means that cannot be written or rewritten.
[0025]
Each of the first type start port winning detection switches SW1, SW2, SW3 arranged in the left, middle, and right first type start ports 16, 3, 17 is connected to the CPU 32 via the switch detection unit 33, and is also a dot. Each of the left, middle and right symbol display LEDs (L), (C), (R), (l), (c), (r) and the upper symbol display LEDs (U) in the matrix LED display bodies 22, 23 The drive is controlled by the CPU 32 via the LED display circuit 34.
[0026]
The CPU 32 also serves as a drive control means such as a character display LED 26 and a stored number display LED 27 as well as a winning device 14, a decoration indicator lamp 10, a continuous number display LED 20, a large prize opening winning number display LED 21 in the game board 1. Since the drive control system of the member is well known, the description is omitted. Reference numeral 35 denotes a clock circuit that defines the processing cycle of the CPU 32.
[0027]
FIG. 7 is a functional block diagram showing the CPU 32 as the function realizing means. The CPU 32 in this embodiment is a random number generating means, a random number holding means, a combined symbol generating means, a final display symbol setting means, a variable symbol replacing means, and a final symbol. It has a function as a determination means. Each of the final display symbol storage means, the winning symbol storage means and the off symbol storage means is constituted by a RAM 31, and the display control means is constituted by a CPU 32, a ROM 30 and an LED display circuit 34. The display symbol setting means includes a combination symbol generation means, a final display symbol setting means, and a variable symbol replacement means.
[0028]
The processing operation of the symbol display device according to the present embodiment will be described below with reference to flowcharts (FIGS. 8 to 21) showing the main part of the control program stored in the ROM 30. FIG. The processing of task 1 shown in FIG. 8, the processing of task 2 shown in FIG. 9, the processing of task 3 shown in FIGS. 10 to 20, and the processing of task 4 shown in FIG. In response to this, the CPU 32 repeatedly executes the process in substantially parallel every predetermined processing cycle (order of μs).
[0029]
The CPU 32 sequentially increments the value of the jackpot random number storage register RAN1 in the range of 0 to 205 for each predetermined processing period in the processing of the task 1 shown in FIG. 8, and the value of the jackpot random number storage register RAN1 reaches 205. Each time the value of the register RAN1 is initialized to 0 each time, the value of the random time storage register RAN2 for change time is cyclically switched between 0 and 1 each time the value of the register RAN1 makes a round (steps a1 to a6). In addition, each time a winning detection signal is input from the left, middle, and right first-type start opening winning detection switches SW1, SW2, and SW3, the unused random number storage register RAN1 is set to the unused fixed random number storage register Ri. The current value is stored (step a7 to step 13). Each time the CPU 32 detects a winning at the first type starting ports 16, 3, 17, the CPU 32 detects the fixed random number storage register Ri in which the storage state identification flag Fi is not set based on the value of the search index i. Since the current value of the jackpot random number storage register RAN1 is stored in the storage register Ri and the storage state identification flag Fi is set, as shown in FIG. Up to four current values of RAN1 are stored.
[0030]
The value of the jackpot random number storage register RAN1 changes in a regular manner at every predetermined processing cycle, but between the winning detection timing at the left, middle, and right first type start ports 16, 3, and 17 and the current value of RAN1. Has no causal relationship, the current value of RAN1 at the time of winning detection can be used as a random number. Also, the value of RAN1 changes in increments of 0 to 205, but since the value of RAN1 that has reached 205 is immediately initialized by upstream processing, a value of 205 is detected by the processing at the time of winning detection. It will never be done.
[0031]
That is, the big hit random number storage register RAN1 is a random number generating means for continuously generating random numbers in the range from 0 to 204, and the fixed random number storage register Ri is a first type start of the left, middle and right as start signal generating means. Random number holding means for receiving a winning detection signal from the mouth winning detection switches SW1, SW2 and SW3 and storing the current value of the random number generating means RAN1 (see FIG. 7). In this embodiment, the comparison value for setting the range of the jackpot random number storage register RAN1 is set to 205, but this value is not fixed, and can be changed to an arbitrary value by changing a parameter in the program. Can be reset. Further, a dip switch or the like for arbitrarily setting the comparison value is provided on the control board, and the setting value of the dip switch or the like is read in the initialization process when the power is turned on, and this value is stored in the RAM 31 as the comparison value. It may be.
[0032]
The process of task 2 shown in FIG. 9 sequentially changes the value of the internal processing index stored in each of the left symbol data storage register r0, the middle symbol data storage register r1, the right symbol data storage register r2, and the upper symbol data storage register r3. In this case, the CPU 32 randomly creates a winning symbol combination and a missing symbol combination, and the CPU 32 performs each of the left, middle, right, and upper symbol data storage registers r0 to r3 in steps b1 to b12. All the combinations of symbols that can be displayed are created by changing the values of the internal processing index stored in the process sequentially and individually for each processing cycle, and the combination of the internal processing indexes created in that processing cycle is the winning symbol. (Step b13), if it is a winning symbol, the current value of each internal processing index is set to the left, middle Stored in each of the right and upper jackpot symbol data storage registers r0a to r3a (step b14), and if the combination of the internal processing indexes created in the processing cycle is out of relation, the current status of each internal processing index The value is stored in each of the left, middle, right, and outlier symbol data storage registers r0b to r3b (step b15).
[0033]
Accordingly, only the value of the internal processing index relating to the jackpot symbol is sequentially updated and stored in each of the left, middle, right, and upper jackpot symbol data storage registers r0a to r3a, and the left, middle, right, and missed symbols are also stored. In each of the data storage registers r0b to r3b, only the value of the internal processing index relating to the off symbol is successively changed and stored. That is, each of the left, middle, right, and upper symbol data storage registers r0 to r3 is a substantially combined symbol generation means, and each of the winning symbol storage means and the off symbol storage means is left, middle, right, and upper jackpot. It consists of symbol data storage registers r0a to r3a and left, middle, right and upside symbol data storage registers r0b to r3b (see FIG. 7).
[0034]
The relationship between the values of the internal processing indices stored in the symbol data storage registers r0, r1, r2 and r3 and the symbols is as shown in Tables 1 to 4, and the left, middle, right and upper display indices il, It is equal to the relationship between ic, ir, iu and symbols. Values that can be taken by the internal processing index regarding the left symbol and the middle symbol are 0 to 14 (see Tables 1 and 2), and values that can be taken by the internal processing index regarding the right symbol are 0 to 15 (Table 3). Reference), possible values of the internal processing index relating to the upper symbol are 0 to 3 (see Table 4). Therefore, in order to create all the combined symbols that can be displayed in a circle, 15 ² • 16.4 processing cycles are required.
[0035]
[Table 1]

[0036]
[Table 2]

[0037]
[Table 3]

[0038]
[Table 4]

[0039]
The combinations of symbols that are jackpots are as shown in Table 5. If the left, middle, and right symbols all match, the symbol combination is a jackpot regardless of the above symbols. When the numbers of the middle symbols match, the number of the right symbols is one smaller than the numbers of the left and middle symbols (however, if the left and middle symbols match “0”, the right symbol is “ 9 ”) and only when the upper symbol display is“ +1 ”, the symbol combination is a big hit.
[0040]
[Table 5]

[0041]
That is, the combination of symbols stored in the left, middle, right and upper jackpot symbol data storage registers r0a to r3a is one of the combinations shown in Table 5, and all other combinations are left. , Middle, right, upside-down symbol data storage registers r0b to r3b. Therefore, the probability of winning a big hit by displaying each symbol in a completely random manner as in a mechanical rotary drum is 70/14400, which is obtained by dividing the number of symbol combinations by the total number of symbols. In the embodiment, when the variable display is stopped based on the relationship between the value of the fixed random number storage register Ri set when the winning is detected at the first, second, and first type starting ports 16, 3, and 17 and the set value. Since the symbols to be displayed are selected, the jackpot occurrence probability can be arbitrarily set regardless of the combination occurrence probability of each symbol. The values of the registers r0a to r3a, the registers r0b to r3b, and the registers r0 to r3 indicate the values of the internal processing indexes, and the current values of the display indexes il, ic, ir, and iu used for actual variation display. It is independent of the value.
[0042]
The processing of task 3 shown in FIG. 10 to FIG. 20 mainly relates to symbol variation display.
[0043]
The CPU 32 that has started the processing of the task 3 first stores a state as to whether or not a new symbol variation display can be started based on winning detection at the first, second, and first type starting ports 16, 3, and 17 of the left, middle, and right. Detection is performed based on whether 1 or 2 is set in the flag Fa (step c1, step c2). If the value of the state memory flag Fa is 1, the symbol variation display is being executed, and if the value of the state memory flag Fa is 2, the opening operation of the big prize opening 15 is being executed. In addition, a new symbol variation display cannot be started. Note that when the value of the state storage flag Fa is 1, the CPU 32 continuously executes the symbol display by the processing of the task 3, and when the value of the state storage flag Fa is 2, the CPU 32 effectively Process 3 is not executed.
[0044]
If the state memory flag Fa is a value other than 1 and 2, neither the symbol change display nor the opening operation of the special winning opening 15 is performed, so that a new symbol change can be started (in the initial stage). Fa = 0).
[0045]
In this case, the CPU 32 first determines whether or not 1 is set in the storage state identification flag F0, that is, in the processing of the task 1, the left, middle, and right first type start ports 16, 3, and 17 have already won. It is determined whether or not it has been detected (step c3).
[0046]
If winning at the left, middle, and right first-type start ports 16, 3, and 17 is detected, the value of the jackpot random number storage register RAN1 at the time of winning detection is stored in the fixed random number storage register Ri by the processing of task 1 In addition, 1 is set to the storage state identification flag Fi corresponding to the fixed random number storage register Ri. At this time, the CPU 32 detects winning in the left, middle, and right first type start ports 16, 3, and 17. Each time the random number is stored in the fixed random number storage register Ri in the order of i = 0 to 3, if the storage state identification flag F0 is set to 1, the left, middle and right first type start ports This means that winnings 16, 16, and 17 have been detected at least once (see step a7 to step a13).
[0047]
If 1 is set to the storage state identification flag F0, the CPU 32 proceeds to step c4, sets 1 to the state storage flag Fa, stores the start of the variable display, and defines the variable display selection process. The variable state storage flag Fb is set to 0 (step c5), and predetermined values are set to the parameters ta to tg (step c6). As shown in FIG. 23, ta to tg are values indicating switching times of the changing speeds of the left, middle, and right symbols.
[0048]
The CPU 32 having set the switching time of the fluctuation speed of each of the left, middle, and right symbols, next, the respective symbol display LEDs (L), (C), (on the left, middle, right, and upper sides of the dot matrix LED display 22. R) and (U) start the process of continuously incrementing the values of the display indices il, ic, ir, iu indicating the symbols to be displayed in each of the symbols (R), (U) (step c7). To start measuring the elapsed time after the start of the variable display (step c8). Note that the actual symbol feed is as if the symbols flow up and down by switching the display output of each row of each symbol display LED (L), (C), (R), (U) every several cycles. However, since this point is well known as a display technique using an LED element or the like, description thereof is omitted. Substantial display control means is constituted by the CPU 32, each display index il, ic, ir, iu and the LED display circuit 34 (see FIG. 7).
[0049]
Since the state storage flag Fa has already been set to 1 in the processing after the next cycle, the CPU 32 as the display control means proceeds to step c9 after executing the discrimination processing in step c1, and hereinafter the current value of the fluctuation state storage flag Fb. Depending on 0, until the elapsed time T after the start of the variable display reaches the set value ta, the discrimination processing of step c1 and step c9 to step c10 and the left, middle, right, and upper symbol display LEDs (L) , (C), (R), (U), the process of step c11 relating to the high-speed fluctuation is repeatedly executed at a predetermined processing cycle.
[0050]
When the elapsed time T after the start of variation display reaches the set value ta (step c10) while the high-speed variation process for each symbol is repeatedly performed in this way, the CPU 32 determines the value of the fixed random number storage register R0, which is a random number holding means. Is stored in the fixed value storage register Ra (step c12), and as shown in FIG. 22B, the data of the storage state identification flags F1 to F3 and the fixed random number storage registers R1 to R3 are stored in the storage state identification flag F0. To F2 and the fixed random number storage registers R0 to R2 are sequentially shifted, and 0 is set to the storage state identification flag F3 and the fixed random number storage register R3 (step c13).
[0051]
Next, the CPU 32 determines whether or not the value of the fixed value storage register Ra matches the set value 7, that is, the left, middle, and right first type starting ports 16, 3, and 3 that have become the starting stimulus of the current symbol variation process. It is determined whether or not the value of the random number held when the winning to 17 is detected matches the set value corresponding to the jackpot (step c14), and if the value of the fixed value storage register Ra matches the set value, the winning symbol The values of the left, middle, right, and upper jackpot symbol data storage registers r0a to r3a, which are storage means, are stored in the left, middle, right, and upper display symbol storage registers r0c to r3c (step c15), while the fixed value storage register If the value of Ra does not match the set value, the left, middle, right, and upper display symbol storage registers r0c to r3b are set to the values of the left, middle, right, and upper symbol data storage registers r0b to r3b, which are outliers. r Stored in each of the c (Step c16), to determine the symbol to be displayed on the symbol display LED during variation stopped. That is, each of the left, middle, right, and upper display symbol storage registers r0c to r3c is a final display symbol storage means, and the processing of step c12 and steps c14 to c16 by the CPU 32 corresponds to the final display symbol setting means ( (See FIG. 7).
[0052]
Next, the CPU 32 changes the value of the display index il related to the left symbol so that the symbol corresponding to the internal processing index of the left symbol display register r0c is displayed at the fluctuation stop time tc of the left symbol display LED (L). (Step c17), the fluctuation speed of the left symbol display LED (L) is switched from high speed fluctuation to medium speed fluctuation (step c18), and the fluctuation state storage flag Fb is set to 1 (step c19). End the process.
[0053]
Although the value of the display index il of the left symbol display LED (L) at the time of ta is not obvious, the value of the medium symbol variation time tb-ta = A of the left symbol display LED (L) and the low speed of the left symbol display LED (L) The value of the fluctuation time tc−tb = B is set in advance, and the left symbol display LED (L) has a constant medium speed fluctuation speed and a low speed fluctuation speed that are constant. The setting change value of the display index il can be obtained based only on the information of the display indicator r0c of the symbol to be displayed on the left symbol display LED (L) at the fluctuation stop time tc.
[0054]
According to the processing timing of the embodiment, when switching from high speed fluctuation to medium speed fluctuation, the current value of the display index il is 2 symbols rather than the display index r0c of the symbol to be displayed on the left symbol display LED (L) when the fluctuation is stopped. By changing the il value so that it becomes the previous display index, the symbol r0c can be obtained when the fluctuation is stopped. That is, the process of step c17 by the CPU 32 constitutes a changing symbol replacement means (see FIG. 7).
[0055]
In the processing after the next cycle, the CPU 32 proceeds to step c20 after executing the discrimination processing of step c1 and step c9. Hereinafter, the elapsed time T after the start of the fluctuation display is set according to the current value 1 of the fluctuation state storage flag Fb. Until the value tb is reached, the determination processing in step c1, step c9 and steps c20 to c21, the processing relating to the medium speed fluctuation of the left symbol display LED (L), and the symbol display LEDs (C ), (R), and (U), the process of step c22 relating to the high-speed fluctuation is repeatedly executed at a predetermined processing cycle.
[0056]
When the elapsed time T after the start of variation display reaches the set value tb (step c21) while the variation processing for each symbol is repeatedly executed in this way, the CPU 32 changes the variation rate of the left symbol display LED (L) to the medium speed. While switching from the fluctuation to the low speed fluctuation (step c23), 2 is set to the fluctuation state storage flag Fb (step c24), and the processing of this cycle is finished.
[0057]
Since the value of the fluctuation state storage flag Fb is 2 in the processing after the next cycle, the CPU 32 proceeds to step c25 after executing the discrimination processing of step c1, step c9 and step c20, and hereinafter, the current value of the fluctuation state storage flag Fb. 2, until the elapsed time T after the start of the fluctuation display reaches the set value tc, the discrimination processing of step c1, step c9, step c20 and steps c25 to c26 and the left symbol display LED (L) The processing related to the low-speed fluctuation and the processing in step c27 relating to the high-speed fluctuation of the middle, right, and upper symbol display LEDs (C), (R), and (U) are repeatedly executed at a predetermined processing cycle.
[0058]
When the elapsed time T has reached the set value tc in the determination process of step c26, the CPU 32 stops the low speed fluctuation of the left symbol display LED (L) (step c28), and the fluctuation state storage flag Fb. Is set to 3 (step c29), and the processing in this cycle is completed. At the time when the low-speed fluctuation of the left symbol display LED (L) is stopped, the symbol corresponding to the index stored in the left symbol display register r0c is statically displayed on the left symbol display LED (L). However, if normal display control is hindered by the influence of external noise or the like, another symbol may be displayed when the variable display is stopped. Even in such a case, since the symbol is displayed based on the data read from the ROM 31 based on the value of the display index il, the relationship between the value of the display index il and the left symbol is Always secured.
[0059]
Since the value of the fluctuation state storage flag Fb is 3 in the processing after the next cycle, the CPU 32 proceeds to step c31 after executing the discrimination processing of step c1, step c9, step c20, step c25, and step c30. In accordance with the current value 3 of the storage flag Fb, until the elapsed time T after the start of the fluctuation display reaches the set value td, the determination processing of Step c1, Step c9, Step c20, Step c25 and Step c30 to Step c31 The process of step c32 regarding the high-speed fluctuation of the symbol display LEDs (C), (R), and (U) in the middle, right, and upper is repeatedly executed at a predetermined processing cycle.
[0060]
Then, when it is detected in the determination process of step c31 that the elapsed time T has reached the set value td, the CPU 32 performs an internal process of the middle display symbol storage register r1c at the fluctuation stop time tf of the middle symbol display LED (C). The value of the display index ic relating to the middle symbol is changed so that the symbol corresponding to the index is displayed (step c33), and the fluctuation speed of the middle symbol display LED (C) is switched from high speed fluctuation to medium speed fluctuation ( In step c34), 4 is set in the fluctuation state storage flag Fb (step c35), and the processing in this cycle is completed.
[0061]
Since the value of the medium speed change time te-td = A and the value of the low speed change time tf-te = B of the middle symbol display LED (C) are the same as those of the left symbol display LED (L), The conditions related to the setting change are the same as in the case of the left symbol display LED (L). When switching from high speed fluctuation to medium speed fluctuation, the current value of the display index ic is displayed on the middle symbol display LED (C) when the fluctuation is stopped. By changing the setting of the value of ic so that it becomes a display index two symbols before the display symbol r1c for the power symbol, the symbol r1c can be obtained when the fluctuation is stopped. That is, the process of step c33 by the CPU 32 constitutes a part of the changing symbol replacement means (see FIG. 7).
[0062]
In the processing after the next cycle, the value of the fluctuation state storage flag Fb is 4. Therefore, the CPU 32 proceeds to step c37 after executing the discrimination processing of step c1, step c9, step c20, step c25, step c30, and step c36. Depending on the current value 4 of the fluctuation state storage flag Fb, steps c1, step c9, step c20, step c25, step c30, and steps c36 to c36 until the elapsed time T after the start of fluctuation display reaches the set value te. The determination process of step c37, the process related to the medium speed fluctuation of the middle symbol display LED (C), and the process of step c38 related to the high speed fluctuation of the right and upper symbol display LEDs (R) and (U) are performed at a predetermined processing cycle. It will be executed repeatedly.
[0063]
When the elapsed time T after the start of the fluctuation display reaches the set value te during the repeated execution of the fluctuation process for each symbol in this way (step c37), the CPU 32 changes the fluctuation speed of the middle symbol display LED (C) to the medium speed. While switching from the fluctuation to the low speed fluctuation (step c39), the fluctuation state storage flag Fb is set to 5 (step c40), and the processing of this cycle is completed.
[0064]
In the processing after the next cycle, the value of the fluctuation state storage flag Fb becomes 5, so the CPU 32 proceeds to step c42 after executing the discrimination processing of step c1, step c9, step c20, step c25, step c30, step c36, step c41. Thereafter, in accordance with the current value 5 of the fluctuation state storage flag Fb, until the elapsed time T after the start of fluctuation display reaches the set value tf, step c1, step c9, step c20, step c25, step c30, The determination process of step c36 and step c41 to step c42, the process related to the low speed fluctuation of the middle symbol display LED (C), and the process of step c43 related to the high speed fluctuation of the right and upper symbol display LEDs (R) and (U). It is repeatedly executed at a predetermined processing cycle.
[0065]
Then, when it is detected by the discrimination process in step c42 that the elapsed time T has reached the set value tf, the CPU 32 stops the low speed fluctuation of the middle symbol display LED (C) (step c44), and the fluctuation state storage flag Fb. Is set to 6 (step c45), and the processing in this cycle is completed. When the low-speed fluctuation of the middle symbol display LED (C) is stopped, the symbol corresponding to the index stored in the middle symbol display memory register r1c is statically displayed on the middle symbol display LED (C). . Even when normal display control is hindered by the influence of external noise or the like, the relationship between the value of the display index ic and the middle symbol is always ensured.
[0066]
Since the value of the fluctuation state storage flag Fb is 6 in the processing after the next cycle, the CPU 32 performs the step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46 after executing the discrimination processing. The process proceeds to c47, and thereafter, according to the current value 6 of the fluctuation state storage flag Fb, until the elapsed time T after the start of fluctuation display reaches the set value tg, step c1, step c9, step c20, step c25, Step c30, step c36, step c41 and step c46 to step c47, and the processing of step c48 regarding the high-speed fluctuation of each of the right and upper symbol display LEDs (R) and (U) are repeatedly executed at a predetermined processing cycle. Will be.
[0067]
Then, when it is detected in the determination process of step c47 that the elapsed time T has reached the set value tg, the CPU 32 detects the current value of the display index il of the left symbol display LED (L) and the middle symbol display LED (C). Whether the display symbol ic of the left symbol display LED (L) is the same as the stop symbol of the left symbol display LED (L) and the stop symbol of the middle symbol display LED (C). (Step c49), it is necessary for the symbol variation process after tg according to the coincidence mismatch between the stop symbol of the left symbol display LED (L) and the stop symbol of the middle symbol display LED (C). Various data will be set.
[0068]
First, if the determination result of step c49 is false, that is, the stop symbol of the left symbol display LED (L) does not match the stop symbol of the middle symbol display LED (C), and there is a probability that a big hit will occur. If there is none, the CPU 32 sets a predetermined value in the th to tl parameters indicating the switching time of the fluctuation speed of the right and upper symbols (step c50), and then the right symbol display LED (R). The value of the display index ir related to the right symbol is changed so that the symbol corresponding to the internal processing index of the right display symbol memory register r2c is displayed during the fluctuation stop time ti (step c51), and the right symbol display LED (R) Is switched from high-speed fluctuation to medium-speed fluctuation (step c56), 7 is set in the fluctuation state storage flag Fb (step c57), and the processing of this cycle is completed.
[0069]
Since the value of the medium speed fluctuation time th-tg = C of the right symbol display LED (R) and the value of the slow fluctuation time ti-th = D of the right symbol display LED (R) are fixed, the right symbol display LED ( The setting change value of the display index ir can be obtained based only on the information of the display indicator r2c of the symbol to be displayed on the right symbol display LED (R) at the fluctuation stop time ti of R). According to the processing timing of the embodiment, when switching from high speed fluctuation to medium speed fluctuation, the current value of the display index ir is 2 symbols rather than the display index r2c of the symbol to be displayed on the right symbol display LED (R) when the fluctuation is stopped. By changing the value of ir so that it becomes the previous display index, the symbol r2c can be obtained when the fluctuation is stopped. Therefore, the process of step c51 by the CPU 32 is a part of the changing symbol replacement means (see FIG. 7).
[0070]
Further, when the determination result of step c49 becomes true, that is, the stop symbol of the left symbol display LED (L) matches the stop symbol of the middle symbol display LED (C), and the possibility of generating a big hit If there is a 2 pattern reach State and Become. After changing the current value of the display index ir related to the right symbol to the specific value 3 (step c52), the CPU 32 changes the value of the random time storage register RAN2 for variable time and the information of the display index r2c to be displayed at the time of stoppage of the change. Thus, the parameters th to tj are selectively set (step c53 to step c55).
[0071]
That is, when the value of the random time storage register RAN2 for variation time is 0, the variation corresponding to the display index r2c of the symbol to be displayed when the variation is stopped based on the selection condition file of the ROM 31 as shown in Table 6 The time C is selected and the parameter th is set to tg + C (step c54). If the value of the random time storage register RAN2 for variation time is 1, the selection condition file of the ROM 31 as shown in Table 7 is displayed. Based on this, the variation time C corresponding to the symbol display index r2c to be displayed when the variation is stopped is selected, tg + C is set to the parameter th, and a predetermined value is added to the value of the parameter th, and the parameters ti and The value of tj is set (step c55).
[0072]
[Table 6]

[0073]
[Table 7]

[0074]
Therefore, if the value of the random time storage register RAN2 for fluctuation time is 0 and the value of the display index r2c of the symbol to be displayed when the fluctuation is stopped is 0, 3.104s from Table 6 is selected as the fluctuation time C. The value of the parameter th is tg + C = 10.016 s, and the value of the random time storage register RAN2 for variation time is 1 and the value of the display indicator r2c of the symbol to be displayed when the variation is stopped is 15. For example, 11.040 s is selected from Table 7 as the variation time C, and the value of the parameter th is tg + C = 17.952 s.
[0075]
In other words, the processing of step c54 and step c55 is the value of the display index r2c of the symbol to be displayed at the time of the fluctuation stop with the fluctuation time at the medium speed and low speed fixed as in the processes shown at step c17, step c33 and step c51. Instead of resetting the value of the display index ir at the start of the medium speed fluctuation, instead of resetting the value of the display index ir at the start of the medium speed fluctuation, the value of the display index ir at the start of the medium speed fluctuation is determined to be a specific value and the display indicator The medium speed and low speed fluctuation times are set corresponding to the value of r2c, and the processing of these steps c52, c54 and c55 is also part of the fluctuation symbol replacement means. Note that the values of the variation time C shown in Table 6 and Table 7 are examples based on the processing timing of the embodiment, and do not limit the variation time or the like.
[0076]
Then, the CPU 32 having set the th to tj parameters in the process of step c54 or step c55 switches the fluctuation speed of the right symbol display LED (R) from high speed fluctuation to medium speed fluctuation (step c56), and then stores the fluctuation state. The flag Fb is set to 7 (step c57), and the processing in this cycle is finished.
[0077]
As a result of setting 7 in the fluctuation state storage flag Fb, in the processing after the next cycle, the discrimination processing of step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, and step c58 is executed. Thereafter, the CPU 32 proceeds to step c59, and thereafter, in accordance with the current value 7 of the variation state storage flag Fb, until the elapsed time T after the start of variation display reaches the set value th, step c1, step c9, step c20, Step c25, Step c30, Step c36, Step c41, Step c46 and Step c58 to Step c59, the middle symbol variation of the right symbol display LED (R), and the high symbol variation of the upper symbol display LED (U) Step c60 is repeatedly executed at a predetermined processing cycle. It becomes a.
[0078]
When the elapsed time T after the start of variation display reaches the set value th during repeated execution of variation processing for each symbol in this way (step c59), the CPU 32 changes the variation rate of the right symbol display LED (R) to medium speed. While switching from the fluctuation to the low speed fluctuation (step c61), the fluctuation state storage flag Fb is set to 8 (step c62), and the processing of this cycle is completed.
[0079]
In the processing after the next cycle, the value of the fluctuation state storage flag Fb becomes 8. Therefore, the CPU 32 performs step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63. After the determination process is executed, the process proceeds to step c64, and thereafter, in accordance with the current value 8 of the fluctuation state storage flag Fb, until the elapsed time T after the start of fluctuation display reaches the set value ti, step c1, step c9, Step c20, step c25, step c30, step c36, step c41, step c46, step c58 and step c63 through step c64, the right symbol display LED (R) low-speed fluctuation and the upper symbol display LED (U) The process of step c65 regarding high speed fluctuation is a predetermined process. So that the repeatedly executed in a cycle.
[0080]
Then, when it is detected in the discrimination process in step c64 that the elapsed time T has reached the set value ti, the CPU 32 stops the low speed fluctuation of the right symbol display LED (R) (step c66), and the fluctuation state storage flag Fb. Is set to 9 (step c67), and the processing in this cycle is completed. When the low speed fluctuation of the right symbol display LED (R) is stopped, the symbol corresponding to the index stored in the right symbol display register r2c is statically displayed on the middle right symbol display LED (R). Become. Further, even when normal display control is hindered by the influence of external noise or the like, the relationship between the value of the display index ir and the right symbol is always ensured.
[0081]
In the processing after the next cycle, the value of the fluctuation state storage flag Fb becomes 9, so the CPU 32 performs step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63. , After execution of the discrimination process in step c68, the process proceeds to step c69. Hereinafter, in accordance with the current value 9 of the fluctuation state storage flag Fb, until the elapsed time T after the start of the fluctuation display reaches the set value tj, the steps c1, Step c70 regarding step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63 and steps c68 to c69, and the high-speed fluctuation of the upper symbol display LED (U). The process of the predetermined process So that the run repeatedly in the period.
[0082]
When the elapsed time T has reached the set value tj in the discrimination process at step c69, the CPU 32 detects the current value of the display index il of the left symbol display LED (L) and the middle symbol display LED (C). Whether the display symbol ic of the left symbol display LED (L) is the same as the stop symbol of the left symbol display LED (L) and the stop symbol of the middle symbol display LED (C). Whether or not the current value of the display indicator il of the left symbol display LED (L) and the current value of the display indicator ir of the right symbol display LED (R) match, that is, It is determined whether or not the stop symbol of the left symbol display LED (L), the stop symbol of the middle symbol display LED (C), and the stop symbol of the right symbol display LED (R) are all consistently displayed ( Step c75), responding to the pattern mismatch Te, so that the setting various data required for the symbol variation processing after time tj.
[0083]
First, when the determination result of step c71 is false, that is, when the stop symbol of the left symbol display LED (L) and the stop symbol of the middle symbol display LED (C) do not match, the CPU 32 Based on the fixed values tk and tl of the variation time set in the process of step c50, the symbol corresponding to the internal processing index of the upper symbol storage register r3c is displayed at the variation stop time tl of the upper symbol display LED (U). As described above, the value of the display symbol iu relating to the upper symbol is changed (step c72), the fluctuation speed of the upper symbol display LED (U) is switched from high speed fluctuation to medium speed fluctuation (step c73), and the fluctuation state storage flag Fb is set to 10 (step c74), and this cycle of processing is terminated.
[0084]
In this case, the value of the medium symbol variation time tk-tj = E of the upper symbol display LED (U) and the value of the slow symbol variation time tl-tk = F of the upper symbol display LED (U) are fixed. The setting change value of the display index iu can be obtained based only on the information of the display indicator r3c of the symbol to be displayed on the upper symbol display LED (U) at the time when the display LED (U) fluctuates. In this case, as in the case of the left symbol display LED (L) and the middle symbol display LED (C), the value of the display index iu is changed to a value two symbols before the display index r3c to be displayed when the fluctuation is stopped. It will be. The process of step c72 by the CPU 32 is also a part of the changing symbol replacement means (see FIG. 7).
[0085]
Further, when the determination result of step c71 is true and the determination result of step c75 is false, that is, the stop symbol of the left symbol display LED (L) and the stop symbol of the middle symbol display LED (C). If only the two match, the CPU 32 sets the fluctuation times tk and tl based on the value of tj set in step c54 or step c55 and the predetermined medium speed fluctuation time E and low speed fluctuation time F. (Step c76), the value of the display index iu related to the upper symbol is set so that the symbol corresponding to the internal processing index of the upper display symbol storage register r3c is displayed at the fluctuation stop time tl of the upper symbol display LED (U). Change (step c72). Also in this case, since the value of the medium speed fluctuation time E of the upper symbol display LED (U) and the value of the low speed fluctuation time F of the upper symbol display LED (U) are fixed, they are displayed when the fluctuation is stopped as described above. A desired stop symbol can be obtained by changing the setting of the value of the display indicator iu to a value two symbols before the power display indicator r3c.
[0086]
In addition, as described above for the combination of symbols that is a big hit using Table 5, the stop symbol of the left symbol display LED (L) matches the stop symbol of the middle symbol display LED (C), and the left symbol display LED (L ) The stop symbol of the right symbol display LED (R) is not the same as the stop symbol of the left symbol display LED (L). Only if one is smaller, there is a possibility that a jackpot will occur in accordance with a part of the symbol that will be a jackpot Will be .
[0087]
On the other hand When the determination results of step c71 and step c75 are both true, that is, the stop symbol of the left symbol display LED (L), the stop symbol of the middle symbol display LED (C), and the stop symbol of the right symbol display LED (R) If all the symbols match, there is a possibility that a jackpot will occur. It becomes. The CPU 32 proceeds to step c77, changes the current value of the display index iu related to the upper symbol to a specific value 1, and then displays it when the fluctuation is stopped based on the selection condition file of the ROM 31 as shown in Table 8. The variation time E corresponding to the display symbol r3c of the power symbol is selected, tj + E is set to the parameter tk, and a predetermined value is added to the parameter tk to set the value of the parameter tl (step) c78).
[0088]
[Table 8]

[0089]
In the processing of step c77 and step c78, the value of the display index iu at the start of the medium speed fluctuation is determined to be a specific value, and the medium speed and low speed fluctuations correspond to the value of the display index r3c of the symbol to be displayed when the fluctuation is stopped. The time is set, and the processing method is the same as the processing of Step c52, Step c54, and Step c55, and the processing of Step c77 and Step c78 is also a part of the changing symbol replacement means. Note that the value of the fluctuation time E shown in Table 8 shows an example based on the processing timing of the embodiment, and does not limit the fluctuation time or the like.
[0090]
The CPU 32 having set the parameters tk and tl in the process of step c78 switches the fluctuation speed of the upper symbol display LED (U) from the high speed fluctuation to the medium speed fluctuation (step c73), and sets the fluctuation state storage flag Fb to 10 Is set (step c74), and the processing of this cycle is completed.
[0091]
As a result of setting 10 to the fluctuation state storage flag Fb, in the processing after the next cycle, step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63, After executing the discrimination processing of step c68 and step c79, the CPU 32 proceeds to step c80, and hereinafter, the elapsed time T after the start of the fluctuation display reaches the set value tk according to the current value 10 of the fluctuation state storage flag Fb. During the interval between step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63, step c68 and steps c79 to c80, the upper symbol display LED ( U) Medium speed The processing of steps c81 on Dynamic becomes possible to execute repeatedly at a predetermined processing cycle.
[0092]
When the elapsed time T after the start of the fluctuation display reaches the set value tk (step c80) while the upper pattern medium speed fluctuation process is repeatedly executed in this way, the CPU 32 changes the fluctuation speed of the upper symbol display LED (U). While switching from the medium speed fluctuation to the low speed fluctuation (step c82), the fluctuation state storage flag Fb is set to 11 (step c83), and the processing of this cycle is completed.
[0093]
In the processing after the next cycle, the value of the fluctuation state storage flag Fb is 11, so that the CPU 32 performs step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63. , Step c68, step c79, and step c84 are executed, and then the process proceeds to step c85. Thereafter, the elapsed time T after the start of the fluctuation display reaches the set value tl according to the current value 11 of the fluctuation state storage flag Fb. The determination process of step c1, step c9, step c20, step c25, step c30, step c36, step c41, step c46, step c58, step c63, step c68, step c79 and steps c84 to c85, Figure The repeatedly executing the processing in step c86 regarding slow variation of the display LED (U) at a predetermined processing cycle.
[0094]
Next, when it is detected in the discrimination process in step c85 that the elapsed time T has reached the set value tl, the CPU 32 stops the low-speed fluctuation of the upper symbol display LED (U) (step c87), and the upper symbol storage register. The symbol corresponding to the index stored in r3c is displayed statically. Even when normal display control is hindered by the influence of external noise or the like, the relationship between the value of the display index iu and the upper symbol is always ensured.
[0095]
Then, the CPU 32 that has finished displaying all the symbols on the left, middle, right, and upper symbol display LEDs (L), (C), () based on the current values of the display indices il, ic, ir, and iu. It is determined whether or not the combination of R) and (U) matches the combination of winning symbols as shown in Table 5 (step c88). 12 is set (step c89), the lighting switching cycle is set in the timer Ta, the time measurement is started (step c90), and the switching count storage register C is initialized (step c91). If it is not a combination of winning symbols, the values of the state storage flag Fa and the fluctuation state storage flag Fb are initialized (step c92, step c93), and the processing of this cycle is finished. The determination process of step c88 by the CPU 32 is substantially the final determination means (see FIG. 7).
[0096]
In this embodiment, the current value of the jackpot random number storage register RAN1 is stored in the fixed random number storage register Ri in the process of step a12 when winning is detected at the left, middle, and right first type start ports 16, 3, and 17. Whether or not a big hit has already occurred is determined depending on whether or not the value of the fixed random number storage register Ri coincides with the set value 7 at the time, and the medium speed fluctuation display of the left symbol display LED (L) is displayed in the process of step c17. At the time of starting, the combination of jackpot symbols and the combination of missed symbols has been confirmed by the processing of step c14 to step c16, but normal display control is hindered by the influence of external noise and the like and finally displayed. It is also possible that the design will be crazy.
[0097]
However, in the present embodiment, when determining the final symbol combination, the current values of the display indices il, ic, ir, and iu corresponding to the symbols when the variable display is stopped are used instead of the symbol combinations that are determined in advance. Therefore, even if the display symbol is distorted, an accurate determination corresponding to the combination of the symbols actually displayed can be performed.
[0098]
In the embodiment, the probability of occurrence of jackpot is a value obtained by dividing the range of setting values corresponding to jackpot by the value range of the jackpot random number storage register RAN1, and in this example, the value of the setting value corresponding to jackpot is only 7. Since the possible values of the jackpot random number storage register RAN1 are integers from 0 to 204, the probability of jackpot occurrence is 1/205 (0.975 / 200). Accordingly, the jackpot of the mechanical rotary drum type symbol display device having four rotary drums each representing the symbols shown in Tables 1 to 4 and having the conditions shown in Table 5 set as a combination of hit symbols. Although it substantially coincides with the occurrence probability 70/14400 (0.972 / 200), the value of the comparison value used in the discrimination process in step a2 is changed, or the value of the comparison value used in the discrimination process in step c14 is used as a region. By setting it, it is possible to arbitrarily manipulate the probability of occurrence of a big hit.
[0099]
For example, if the value of the comparison value used in the determination process of step a2 is 210, the probability of occurrence of a jackpot is 1/210 (0.952 / 200), and the comparison value used in the determination process of step c14 is When the value X is set as an area where 5 <X <8, the probability of occurrence of a jackpot is 2/205 (1.951 / 200).
[0100]
Such an operation only affects the probability that the jackpot will be generated. The contents of the jackpot symbol and the missed symbol itself are processed by the task 2, and the left, middle, right, and top jackpot symbol data storage registers r0a to r3a and Since the left, middle, right, and outlier symbol data storage registers r0b to r3b are set at random, there is no possibility that a particular symbol combination is likely to occur, and there is no sense of incongruity.
[0101]
When the final combination of display symbols is a big hit, the value of the variation state storage flag Fb becomes 12 in the processing after the next cycle, so the CPU 32 performs steps c1, c9, c20, c25, After executing the discrimination process of step c30, step c36, step c41, step c46, step c58, step c63, step c68, step c79, and step c84, the process proceeds to step c94. The display switching process from c95 to step c98 is repeatedly executed.
[0102]
The CPU 32 that has started the display switching process increments the value of the switching number storage register C (step c95), and then determines whether or not the number of executions of the display switching process has reached the set value N (step c96). If the number of executions of the process is within the range of the set value N, each time the set time of the timer Ta elapses, the symbol display LEDs (L), (C), (R) of the dot matrix LED display body 22 The jackpot symbol display output is alternately switched between the symbol display LEDs (l), (c), and (r) of the dot matrix LED display 23, and the display is as if the jackpot symbol has moved back and forth. (Step c97), the lighting switching cycle is reset in the timer Ta (Step c98), and this display switching is performed until the value of the switching number storage register C reaches the set value N. Processing repeatedly to run.
[0103]
When it is detected in the determination process in step c96 that the number of executions of the display switching process has reached the set value N, the CPU 32 initializes the values of the switching number storage register C and the fluctuation state storage flag Fb (step c99, In step 100), 2 is set in the state storage flag Fa (step 101), and the execution of the processing of task 4 relating to the opening of the special winning opening 15 is permitted. When the value of the switching number storage register C reaches the set value N, the big hit symbol display returns to the dot matrix LED display 23 side.
[0104]
FIG. 21 is a flowchart showing an outline of task 4 processing. When 2 is set in the state storage flag Fa, the CPU 32 proceeds to step d2 after executing the discrimination processing in step d1, starts the opening / closing operation of the attacker-like big winning opening 15 driven to open / close by a solenoid or the like, The opening / closing process of step d2 is repeatedly executed at a predetermined processing period until the end condition of the opening / closing operation based on the elapse of the opening time or the detection of the number of winning game balls to the big prize opening 15 is established, and step d3 In the determination process, when the end condition is detected, the special winning opening 15 is closed in the process of step d4 to end the 1 opening operation, and the value of the state storage flag Fa is initialized in the process of step d5.
[0105]
As a result of initializing the value of the state storage flag Fa in the processing of task 3 or task 4, the determination results of step c1 and step c2 after the next cycle are both false, and the value of the storage state identification flag F0 is detected again by the CPU 32. (Step c3).
[0106]
Accordingly, when a random number is newly stored in the fixed random number storage register R0 by the second winning detection to the left, right, middle first-type start ports 16, 3, 17 or when a plurality of winning detections are detected, the fixed random number storage register R1. When the value stored thereafter is shifted, the symbol matching process is started again up to 4 times including the first time by the process after step c4.
[0107]
【The invention's effect】
According to the structure of Claim 1, a symbol display control means is When the judgment result by the judging means is out of order, and setting of the outage stop symbol combination is performed, the off symbol combination stored in the off symbol combination storage means is set so that the off symbol combination is stopped and displayed. On the other hand, if the set stop symbol combination is in a predetermined reach state, the symbols are variably displayed in the first reach state, then the outlier symbol combination in the first reach state is displayed, and then the second After the symbols are variably displayed in the reach state of 2, the control is performed so that the set stop symbol combination is stopped and displayed. Therefore, when the off symbol is stopped and displayed, it is different from the symbol variation display processing by the symbol display control means. Since the out-of-order symbol created and stored by another process executed at this timing is used as it is, the stop symbol can be selected or compensated for the stop symbol during fluctuation. Can be stopped displaying reliably failure symbol is not necessary to perform a troublesome process or perform. In addition, when the set stop symbol combination is in a predetermined reach state, a two-step reach state can be displayed. The player's expectation for the big hit can be maintained, and the interest of the game can be improved.
[Brief description of the drawings]
FIG. 1 is a side sectional view showing a main part of a symbol display device of a pachinko machine according to an embodiment of the present invention.
FIG. 2 is a front view showing a game board equipped with the symbol display device of the pachinko machine according to the embodiment.
FIG. 3 is a plan view showing a dot matrix LED display body that constitutes a part of the symbol display means of the embodiment;
FIG. 4 is a plan view showing another dot matrix LED display body that constitutes a part of the symbol display means of the embodiment;
FIG. 5 is a diagram showing an example of a visual recognition state of a dot matrix LED display body.
FIG. 6 is a principal block diagram showing a control unit of the symbol display device of the pachinko machine according to the embodiment.
FIG. 7 is a functional block diagram showing a CPU as function realizing means.
FIG. 8 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 9 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 10 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 11 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 12 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 13 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 14 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 15 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 16 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 17 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 18 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 19 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 20 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 21 is a flowchart showing a part of processing by the CPU of the embodiment;
FIG. 22 is an operation principle diagram showing the storage operation of the definite random number storage register Ri as the random number holding means.
FIG. 23 is a timing chart showing a symbol variation process in the symbol display device of the pachinko machine according to the embodiment;
[Explanation of symbols]
1 Game board
2 Symbol display unit that constitutes the main part of the symbol display device
3 Middle type 1 start port as start signal generating means
16 Left first type start port as start signal generating means
17 Right first type start port as start signal generating means
22 Dot matrix LED display body constituting symbol display means
23. Dot matrix LED display body constituting symbol display means
32 CPU as function realization means
r0 Left symbol data storage register constituting combination symbol generating means
r1 Middle symbol data storage register constituting combination symbol generating means
r2 Right symbol data storage register constituting combination symbol generating means
r3 Upper symbol data storage register constituting combination symbol generating means
Left big hit symbol data storage register constituting symbol memory means per r0a
Medium / large hit symbol data storage register constituting r1a hit symbol storing means
Right big hit symbol data storage register constituting symbol memory means per r2a
Upper jackpot symbol data storage register constituting symbol memory means per r3a
r0b Out-of-left symbol data storage register constituting off- symbol memory means
r1b Out-of-line symbol data storage register constituting off-line symbol storage means
r2b off-right symbol data storage register constituting off- symbol symbol storage means
r3b Outlier symbol data storage register which constitutes an outlier symbol storage means
RAN1 Random number storage register for jackpot constituting random number generating means
Ri Random number storage register constituting random number hold means
r0c Left display symbol storage register constituting final display symbol storage means
r1c Medium display symbol storage register constituting final display symbol storage means
r2c Right display symbol storage register constituting final display symbol storage means
r3c Upper display symbol storage register constituting final display symbol storage means
il indicator
ic display indicator
ir display index
iu display indicator

Claims (1)

A symbol display device is provided, and when a ball enters the start port, a plurality of symbols displayed on the symbol display device are displayed in a variable manner, and a big hit is made on condition that the plurality of symbols are displayed as a winning symbol combination. In bullet ball machines,
Determining means for determining whether or not the big hit is made in response to detection of a ball entering the start opening ;
A symbol display control means for setting a stop symbol combination to be stopped and displayed on the symbol display device according to a determination result by the determination means , and for stopping and displaying the plurality of symbols in the variable display with the set stop symbol combination. and,
A symbol combination creating step for creating the stop symbol combination by a separate process executed at a timing different from the symbol variation display process by the symbol display control means, and whether or not the created stop symbol combination is an out symbol combination. And a stop symbol combination creating processing means comprising: a symbol combination determining step for determining; and a symbol combination storing step for storing the disconnected symbol combination in the disconnected symbol combination storing means if the determination result is a disconnected symbol combination ,
The symbol display control means sets the symbol pattern combination stored in the symbol symbol combination storage means when the determination result by the criterion means is out of order and sets the symbol stop symbol combination. When the set combination of symbols to stop is displayed in a predetermined reach state while the symbol combination is controlled to be stopped, the first reach is displayed after the symbols are variably displayed in the first reach state. A bullet ball game machine , wherein after a symbol combination is displayed in a state, and thereafter the symbol is variably displayed in a second reach state, the set stop symbol combination is controlled to be stopped .

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