JP4656147B2 - 多孔質絶縁膜の形成方法および半導体装置 - Google Patents
多孔質絶縁膜の形成方法および半導体装置 Download PDFInfo
- Publication number
- JP4656147B2 JP4656147B2 JP2007535437A JP2007535437A JP4656147B2 JP 4656147 B2 JP4656147 B2 JP 4656147B2 JP 2007535437 A JP2007535437 A JP 2007535437A JP 2007535437 A JP2007535437 A JP 2007535437A JP 4656147 B2 JP4656147 B2 JP 4656147B2
- Authority
- JP
- Japan
- Prior art keywords
- raw material
- insulating film
- film
- compound
- cyclic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/665—Porous materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
本発明の多孔質絶縁膜の形成方法に用いられる環状有機シロキサン原料および化合物原料について説明する。
本発明においては、層間絶縁膜として好適な多孔質絶縁膜を、少なくとも環状有機シロキサン原料を反応室に供給し、プラズマ気相成長法によって絶縁膜を形成する方法において、環状有機シロキサン原料と、化合物原料との混合ガスを用いて形成することができる。
本発明の第二の実施の形態として、以下に気体化した原料を反応室に供給し、多孔質絶縁膜を形成する実施の形態について図2を用いて説明する。図2は、原料ガスとして使用しようとする環状有機シロキサンの沸点が低く、人為的に加熱しないときには当該環状有機シロキサンが液体状態となる場合に好適に用いることができるガス供給部の要部の一例を示す概略図である。
本発明の第三の実施の形態として、以下に気体化した原料を反応室に供給し、多孔質絶縁膜を形成する実施の形態について図3を用いて説明する。図3は、原料ガスとして使用しようとする環状有機シロキサンの沸点が低く、人為的に加熱しないときには当該環状有機シロキサンが液体状態となる場合に好適に用いることができるガス供給部の要部の一例を示す概略図である。
本発明の実施例として、環状有機シロキサン原料として、式4に示す構造を有する原料を用い、化合物原料としてイソプロピルアルコール(IPA)を用いた場合について詳しく述べる。成膜装置としては、第一の実施の形態に示すような、平行平板型のプラズマCVD装置を用い、原料供給システムとしては、第二の実施の形態に示すような、混合原料用のシステムを用いた。
本発明の実施例として、環状有機シロキサン原料として、式4に示す構造を有する原料を用い、化合物原料として式5を用いた場合について詳しく述べる。成膜装置としては、第一の実施の形態に示すような、平行平板型のプラズマCVD装置を用い、原料供給システムとしては、第二の実施の形態に示すような、混合原料用のシステムを用いた。
本発明の実施例5では、本発明にて形成した多孔質絶縁膜を半導体素子が形成された半導体基板上の多層配線に用いた場合の配線構造について詳しく説明する。
10 反応室
20 ガス供給部
50 プラズマCVD装置
100 液体の環状有機シロキサン原料と化合物原料との混合原料
101 液体の環状有機シロキサン原料
102 原料タンク
103 液体の化合物原料
112 気化部
112b 気化器
113 シリコン酸化膜
200 MOSFET
201 半導体基板
202a、202b シリコン酸化膜
210a、210b 金属配線材
211、211a、211b 絶縁性バリア膜
212、212a、212b、212c ビア層間絶縁膜
213 配線層間絶縁膜
214 デュアルダマシン溝
215、215a、215b バリアメタル膜
216、216a ハードマスク膜
217a、217b エッチストップ膜
218a、218b、218c、218d、218e、218f、218g SiCN膜
219a、219b、219c、219d、219e 多孔質絶縁膜
220a、220b、220c、220d、220e、220f CuAl
221a、221b、221c、221d、221e、221f Ta/TaN
222 TiN
223 タングステン
224 シリコン酸窒化膜
225a、225b Ti/TiN
226 AlCu
VU、VU1、VU2 気化制御ユニット
Claims (9)
- 少なくとも環状有機シロキサン原料を反応室に供給し、プラズマ気相成長法によって絶縁膜を形成する方法において、
前記環状有機シロキサン原料と、前記環状有機シロキサン原料を構成する化学構造の一部を含む化合物原料との混合ガスを用い、
前記化合物原料が、前記環状有機シロキサンの反応前駆体を含むことを特徴とする多孔質絶縁膜の製造方法。 - 前記混合ガスは、気化した状態で、前記環状有機シロキサン原料100体積%に対する前記化合物原料の混合割合が、5〜200体積%の範囲内であることを特徴とする請求項1に記載の多孔質絶縁膜の製造方法。
- 前記混合ガスは前記環状有機シロキサン原料と前記化合物原料との混合原料を気化させることで形成することを特徴とする請求項1又は2に記載の多孔質絶縁膜の製造方法。
- 前記化合物原料は、前記環状有機シロキサン原料の側鎖の一部を含む前記化合物原料であることを特徴とする請求項1乃至3のいずれか一項に記載の多孔質絶縁膜の製造方法。
- 前記化合物原料が、少なくともメタノール、エタノール、プロパノール又はイソプロパノールのいずれか一を含むことを特徴とする請求項1乃至7のいずれか一項に記載の多孔質絶縁膜の製造方法。
- 少なくとも環状有機シロキサン原料が反応室に供給され、プラズマ気相成長法によって形成された絶縁膜を有する半導体装置であって、
前記環状有機シロキサン原料と、前記環状有機シロキサンの反応前駆体である化合物原料と、の混合ガスを用いて形成された多孔質絶縁膜を有することを特徴とする半導体装置。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005264619 | 2005-09-13 | ||
| JP2005264619 | 2005-09-13 | ||
| PCT/JP2006/317819 WO2007032261A1 (ja) | 2005-09-13 | 2006-09-08 | 多孔質絶縁膜の形成方法および半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2007032261A1 JPWO2007032261A1 (ja) | 2009-03-19 |
| JP4656147B2 true JP4656147B2 (ja) | 2011-03-23 |
Family
ID=37864856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007535437A Expired - Fee Related JP4656147B2 (ja) | 2005-09-13 | 2006-09-08 | 多孔質絶縁膜の形成方法および半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8715791B2 (ja) |
| JP (1) | JP4656147B2 (ja) |
| WO (1) | WO2007032261A1 (ja) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2009051163A1 (ja) * | 2007-10-17 | 2011-03-03 | 日本電気株式会社 | 半導体装置およびその製造方法 |
| US7955950B2 (en) * | 2007-10-18 | 2011-06-07 | International Business Machines Corporation | Semiconductor-on-insulator substrate with a diffusion barrier |
| US8211776B2 (en) * | 2010-01-05 | 2012-07-03 | International Business Machines Corporation | Integrated circuit line with electromigration barriers |
| JP5864095B2 (ja) * | 2010-02-18 | 2016-02-17 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| TW201348496A (zh) * | 2012-02-15 | 2013-12-01 | 瑞薩電子股份有限公司 | 多孔性絕緣膜的製造方法以及包含該膜的半導體裝置 |
| JP5904866B2 (ja) | 2012-05-08 | 2016-04-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
| JP5837869B2 (ja) * | 2012-12-06 | 2015-12-24 | 株式会社フジキン | 原料気化供給装置 |
| US9076847B2 (en) | 2013-01-18 | 2015-07-07 | International Business Machines Corporation | Selective local metal cap layer formation for improved electromigration behavior |
| US9123726B2 (en) | 2013-01-18 | 2015-09-01 | International Business Machines Corporation | Selective local metal cap layer formation for improved electromigration behavior |
| JP6190192B2 (ja) * | 2013-07-16 | 2017-08-30 | ソニーセミコンダクタソリューションズ株式会社 | 放射線撮像装置および放射線撮像表示システム |
| US9865798B2 (en) | 2015-02-24 | 2018-01-09 | Qualcomm Incorporated | Electrode structure for resistive memory device |
| JP6109368B2 (ja) * | 2016-03-15 | 2017-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
| JP6862049B2 (ja) * | 2017-03-31 | 2021-04-21 | 東ソー株式会社 | 環状シロキサン化合物、その製造方法、それを用いてなる電気絶縁膜の製造法及び膜 |
| JP7391741B2 (ja) * | 2020-03-23 | 2023-12-05 | 株式会社東芝 | 構造体 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001332550A (ja) * | 2000-05-24 | 2001-11-30 | Canon Sales Co Inc | 半導体装置及びその製造方法 |
| JP2005051192A (ja) * | 2002-11-28 | 2005-02-24 | Tosoh Corp | 有機シラン、有機シロキサン化合物を含んでなる絶縁膜用材料、その製造方法および半導体デバイス |
| WO2005053009A1 (ja) * | 2003-11-28 | 2005-06-09 | Nec Corporation | 多孔質絶縁膜及びその製造方法並びに多孔質絶縁膜を用いた半導体装置 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5630878A (en) * | 1994-02-20 | 1997-05-20 | Stec Inc. | Liquid material-vaporizing and supplying apparatus |
| US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
| US20020062789A1 (en) * | 2000-11-29 | 2002-05-30 | Tue Nguyen | Apparatus and method for multi-layer deposition |
| JP4217870B2 (ja) * | 2002-07-15 | 2009-02-04 | 日本電気株式会社 | 有機シロキサン共重合体膜、その製造方法、成長装置、ならびに該共重合体膜を用いた半導体装置 |
| US7404990B2 (en) * | 2002-11-14 | 2008-07-29 | Air Products And Chemicals, Inc. | Non-thermal process for forming porous low dielectric constant films |
| JP4746829B2 (ja) | 2003-01-31 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7241704B1 (en) * | 2003-03-31 | 2007-07-10 | Novellus Systems, Inc. | Methods for producing low stress porous low-k dielectric materials using precursors with organic functional groups |
| EP1623454A2 (en) * | 2003-05-09 | 2006-02-08 | ASM America, Inc. | Reactor surface passivation through chemical deactivation |
| JP4610487B2 (ja) * | 2003-12-25 | 2011-01-12 | 株式会社Adeka | 金属化合物、薄膜形成用原料及び薄膜の製造方法 |
| JP2005294333A (ja) | 2004-03-31 | 2005-10-20 | Semiconductor Process Laboratory Co Ltd | 成膜方法及び半導体装置 |
| US7112541B2 (en) * | 2004-05-06 | 2006-09-26 | Applied Materials, Inc. | In-situ oxide capping after CVD low k deposition |
| JP2006004996A (ja) * | 2004-06-15 | 2006-01-05 | Semiconductor Process Laboratory Co Ltd | 層間絶縁膜及び拡散防止膜とこれらのソース材料、膜形成方法、膜形成用プラズマcvd装置 |
| JP2006004992A (ja) | 2004-06-15 | 2006-01-05 | Seiko Epson Corp | 研磨装置管理システム、管理装置、管理装置制御プログラム及び管理装置制御方法 |
-
2006
- 2006-09-08 JP JP2007535437A patent/JP4656147B2/ja not_active Expired - Fee Related
- 2006-09-08 US US11/991,745 patent/US8715791B2/en active Active
- 2006-09-08 WO PCT/JP2006/317819 patent/WO2007032261A1/ja not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001332550A (ja) * | 2000-05-24 | 2001-11-30 | Canon Sales Co Inc | 半導体装置及びその製造方法 |
| JP2005051192A (ja) * | 2002-11-28 | 2005-02-24 | Tosoh Corp | 有機シラン、有機シロキサン化合物を含んでなる絶縁膜用材料、その製造方法および半導体デバイス |
| WO2005053009A1 (ja) * | 2003-11-28 | 2005-06-09 | Nec Corporation | 多孔質絶縁膜及びその製造方法並びに多孔質絶縁膜を用いた半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US8715791B2 (en) | 2014-05-06 |
| JPWO2007032261A1 (ja) | 2009-03-19 |
| WO2007032261A1 (ja) | 2007-03-22 |
| US20100219512A1 (en) | 2010-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4812838B2 (ja) | 多孔質絶縁膜の形成方法 | |
| JP5168142B2 (ja) | 半導体装置 | |
| JP5267130B2 (ja) | 半導体装置およびその製造方法 | |
| CN102237272B (zh) | 半导体装置和半导体装置制造方法 | |
| US7163721B2 (en) | Method to plasma deposit on organic polymer dielectric film | |
| US11177167B2 (en) | Ultrathin multilayer metal alloy liner for nano Cu interconnects | |
| JP5093479B2 (ja) | 多孔質絶縁膜の形成方法 | |
| JP4656147B2 (ja) | 多孔質絶縁膜の形成方法および半導体装置 | |
| KR20200037053A (ko) | 다마신 프로세스에서의 금속 장벽의 선택적 성막 | |
| JP5349789B2 (ja) | 多層配線の形成方法 | |
| CN100479146C (zh) | 互连结构及其形成方法 | |
| JP2005033203A (ja) | シリコンカーバイド膜の形成方法 | |
| US7282441B2 (en) | De-fluorination after via etch to preserve passivation | |
| JP4900239B2 (ja) | 有機シリコン系膜の形成方法、当該有機シリコン系膜を有する半導体装置及びその製造方法 | |
| KR20010114051A (ko) | 반도체 소자의 금속 배선 형성 방법 | |
| JPWO2011158691A1 (ja) | 抵抗変化素子及び抵抗変化素子の製造方法 | |
| KR20160098502A (ko) | 진보된 배선들을 위한 유전체 캡핑 배리어로서의 금속-함유 필름들 | |
| JP4325569B2 (ja) | 有機シリコン系膜の形成方法、及び有機シリコン系膜を有する半導体装置 | |
| JP3843275B2 (ja) | 半導体装置の製造方法 | |
| JP2009081179A (ja) | Bcn系の絶縁膜及びその製造方法並びに半導体装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090820 |
|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20091015 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20100809 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20100826 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100914 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101105 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101130 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101213 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140107 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4656147 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |