JPS5857016B2 - Douki Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit suitable for displaying a signal other than a television signal from a broadcast station on a display unit of a television receiver or the like.

In television receivers, it has been considered to broadcast signals from an internal display data generation circuit other than an external station (broadcasting station) in the form of text or the like.

When trying to broadcast characters stored in the display data generation circuit in such a receiver (for example, the time by a clock circuit, the channel in a memory circuit, etc.), the display position on the screen must be stabilized. It is necessary to make it easy for viewers to see.

The present invention has been made in response to the above-mentioned circumstances, and in particular, stabilizes the synchronization relationship between the display data generation circuit and external station signals, and stabilizes the display position when switching display states by signals from the display data generation circuit. The purpose of this invention is to provide a synchronous circuit that obtains the following.

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, in the drawing, 11 is an input terminal of a received signal detection circuit 12 of the television receiver, and an output terminal of this detection circuit 12 is connected to a video signal amplification circuit 13.

The output end of this amplifier circuit 13 is connected to the cathode end of the cathode ray tube 14 to add a signal for broadcasting. It is driven by the oscillation circuit 17 and operates to scan the beam of the cathode ray tube and convert the video signal into an optical image.

Next, the configuration that is the main part of the present invention will be explained.

The output terminal of the video signal detection circuit 12 is connected to a capacitor C1.
It is connected to the base of the synchronous separation transistor Q1 via.

There is a resistor R between the base and emitter of this transistor Q0.
1 is connected, and its emitter is connected to the power supply terminal as well as to the emitter of a transistor Q2 (which is turned on when reading out the contents of a display data generation circuit in the receiver and displaying only this content, which will be described later), that is, during programming. Ru.

and transistor Q1. The collectors of Q2 are commonly connected and grounded via a resistor R3.

Further, a resistor is connected between the base and emitter of the transistor Q2, and the base of this transistor is connected to the collector of the transistor Q4.

Furthermore, the collector of the transistor Q2 is connected to a resistor R,
, R5 to the synchronizing pulse input terminal of the vertical synchronizing deflection circuit 16.

Furthermore, the connection point of the resistors R4, R, and the synchronization pulse input terminal are grounded via capacitors C2, Co, respectively, forming a time constant circuit.

Furthermore, the collector of the transistor Q2 is connected to a capacitor C.
3 to the synchronization pulse input terminal of the horizontal synchronization deflection circuit 17.

The transistor Q4 mentioned above is the transistor Q in the previous stage.
This element amplifies the output of transistor Q3, and its base is connected to the collector of transistor Q3.

The base of this transistor Q3 is grounded via a resistor R7 to set a bias, and is also connected via a resistor R6 to a fixed station C18 in the receiver and a discrimination signal output terminal 182 of an information storage section formed by a semiconductor integrated circuit.

The display data generation circuit 18 in the receiver has a clock circuit, a memory circuit, etc. therein, and when horizontal and vertical readout pulses are applied to the readout circuit section, the display data generation circuit 18 generates the display content (a signal substantially similar to a video signal). ) is displayed on the output terminal 18
1.

This display data generation circuit distinguishes between displaying broadcast images from a broadcast station (normal) and displaying only the stored contents of a broadcast program without broadcast images (program), and then Alternatively, a low level signal is output to the discrimination signal output terminal 182.

Various methods are available for deriving this discrimination signal; for example, an inversion circuit is provided in the display data generation circuit to invert between normal and programming.

It may be controlled by an operation signal from the viewer who selects between normal and program operation, or it may be automatically controlled by a drive signal based on time setting from a clock circuit or the like.

The transistor Q to which the above discrimination signal is applied
The emitter of transistor Q4 is grounded, the collector is connected to the power supply via resistor R8, and the emitter of transistor Q4 is grounded via resistor R0, resistor R1o, and both resistors R9
, R1o is connected to the base of a transistor Q5 that amplifies this signal.

The emitter of this transistor Q5 is grounded, the collector is connected to the base of the transistor Q6, and the resistor R
11 to the power supply.

The emitter of the transistor Q is connected to the collector of the transistor Q7 via a resistor R15 and serves as a current supply source.

The emitter of this transistor Q is grounded, the base thereof is grounded via a resistor R14, and is connected to the vertical pulse output terminal of the vertical synchronization deflection circuit 16 via a resistor R15.

Further, the collector of the transistor Q7 is connected via a resistor R05 to the base of a transistor Q9 which amplifies this output.

The base of this transistor Q is grounded via a capacitor C4 that forms a time constant circuit together with the resistor R16.

Furthermore, the collector of the transistor Q9 is connected to the resistor R1 of the transistor Q that supplies current to this element.
7 and is also connected to the vertical pulse input/output terminal 183 of the display data generating circuit 18 mentioned above.

The emitter of this transistor Q9 is grounded.

The emitter of the transistor Q3 is connected to the power supply, its collector is grounded through a series circuit of resistors R18 and R19, and the base of the transistor Q16 is connected to the connection point between these two resistors Rta t RIQ. .

The emitter of this transistor Q1 is grounded, and the collector is connected to a power supply via a resistor R20 and to the base of a transistor Qll.

The emitter of this transistor is grounded, and the collector is connected to the vertical synchronization pulse input terminal of the vertical synchronization deflection circuit 16 mentioned above.

Next, the operation of the circuit of the present invention will be explained.

First, in the normal operation, only the character display content output of the display data generating circuit 18 is applied to the receiver, and the rest does not affect the receiver.

That is, a normal discrimination signal (bi-level) is derived from the display data generation circuit 18.

At this time, transistor Q3 is on, so transistor Q4. Q5 is off, transistor Q6 is on, transistor Qa = Qo is also on, transistor QIO
is on and transistor Qll is off.

Since transistor Q4 is off, transistor Q2
is off and transistor Q1 is on.

Therefore, the transistor Q1 performs a normal synchronization separation operation, and the separated synchronization pulse is applied as a vertical synchronization pulse to the vertical synchronization deflection circuit 16 via an integrating circuit consisting of resistors R4 and R5 and a capacitor C6°C2.

At this time, the pulse obtained from the vertical synchronization deflection circuit 16 is amplified by the transistor Q7, and the resistors R16, R16,
The signal is amplified and shaped by an NPN transistor Q9 via an integrating circuit consisting of a capacitor C4, and is applied to the vertical pulse output terminal 183 of the display data generating circuit 18.

When a vertical pulse is introduced into this input terminal 183, this display data generating circuit 18 operates to read out the memory content (data) of the circuit section to be read by counting horizontal pulses using this vertical pulse as a reference. .

At this time, the falling edge of the vertical pulse is at the horizontal pulse input terminal 184.
If the horizontal pulse applied to the horizontal pulse overlaps with a specific phase, jitter is likely to occur in the display position corresponding to l horizontal scanning (that is, the position of the stored content relative to the display position on the screen).

Therefore, resistor R15? Adjust the value of R16 capacitor C4.

In this configuration example, the larger the time constant (Ft15 + Rla) C4 (where R15t R16*C4 is the value of the element indicated by the same signal), the more the vertical pulse falls compared to the original vertical pulse. Since there is a delay, adjusting to the best phase relationship as described above eliminates the relative positional deviation in the display of the stored contents.

Furthermore, according to this configuration, since an NPN transistor is used as the transistor Q9 that introduces vertical pulses into the display data generation circuit 18, the rounding of the waveform due to the human power capacitance and other capacitance of the IC can be reduced, and the falling edge of the pulse applied to the IC can be sharpened. , which reduces the probability of a worst-case phase relationship with the horizontal pulse.

In the above case, it is effective to extremely stabilize the relative position of the stored content in the display data generation circuit 18 with respect to the video signal from the broadcasting station, and the display data generation circuit 18 superimposes it on the video signal. This is convenient when displaying the stored contents (time, channel characters, etc.).

Although not specifically shown in the embodiment, a specific section of the video signal, for example, a section corresponding to the corner of the screen, is converted to a specific black or white level using a level conversion circuit, and the display data described above is generated in this section. When inserting the stored contents in the circuit 18, stable image display is possible because the relationship between the display position of the video signal from the broadcasting station and the display position of the stored contents is stable as described above.

In this state, even if the stored contents of the memory circuit are to be switched and displayed, for example, if the channel characters are displayed and then the time is displayed by the clock circuit, the set position for displaying the contents will not be disturbed. Can be displayed stably.

Next, when programming, that is, when displaying only the stored contents of the display data generation circuit 18, this display data generation circuit 18
A program discrimination signal (low level) is derived from.

In this case, the video signal from the broadcasting station is cut, for example, before the amplifier circuit 13.

Therefore, since the vertical synchronization deflection circuit 16 cannot obtain a reference synchronization pulse, the vertical synchronization circuit will freely oscillate as it is.

That is, according to the program discrimination signal, transistor Q3 is turned off, transistors Q4 and Q2 are turned on, transistor Q is turned on, and transistors Qe and Qa -
Q9 is turned off.

As a result of the above, the potential between the collector and the emitter of transistor Q1 is approximately the same, so that transistor Q1 does not perform a synchronous separation function, and only a DC voltage appears at the collector of transistor Q1.

Therefore, as mentioned above, the vertical synchronization circuit becomes free oscillating, and the frequency becomes about 53 Hz, compared to about 60 Hz during image reception.

Therefore, in the present invention, in the display data generation circuit 18,
Divide the frequency of the horizontal pulse to create a vertical synchronizing pulse to maintain normal oscillation of the vertical synchronizing circuit.

Note that in this case, the horizontal synchronous circuit becomes free oscillation.

That is, the output of the horizontal synchronization forward circuit 17 is
5 and is also applied to the horizontal pulse input terminal 184 of the display data generation circuit 18.

The display data generating circuit 18 divides the frequency of this horizontal pulse to generate a vertical pulse and outputs it to the vertical pulse input/output terminal 183.

Therefore, the vertical pulse of this input/output terminal is resistor R171R.
18 to drive transistor QIO, transistor Q11 is turned off during the vertical pulse.

On the other hand, current from the power supply flows through the transistor Q2 and resistors R4 and R5, turning on the transistor Q11.
Upon turning off, a vertical synchronization pulse is generated at the connection point between resistor R5 and capacitor C8, and vertical synchronization is established by this pulse.

According to the above programming operation, the horizontal pulse is divided into vertical pulses and the sync separation circuit is turned off.

Therefore, even when the storage contents in the display data generation circuit 18 are changed, for example, when changing from a time display state to a channel display state, the display position is faithfully determined to the memory address of the memory circuit, and display disturbances due to synchronization are eliminated. .

Similarly, when new content is input to the memory circuit, vertical and horizontal synchronization is stable.

When the memory circuit is an IC, it is known that its capacity tends to change when input (memory information) is applied.

Therefore, when synchronizing pulses of video signals from broadcasting stations are used, for example, when changing channels to input stored contents or change read addresses, the display position of stored contents may shift. According to this method, since the synchronization separation circuit is turned off and vertical pulses are obtained by dividing the horizontal pulse as a reference, it is possible to always obtain a horizontally and vertically stable display.

In addition, to provide a supplementary explanation of the display data generation circuit, if a circuit is connected to each other at the vertical pulse input/output terminal 183 and the horizontal pulse input terminal 184, and a horizontal pulse is applied to the vertical pulse input/output terminal 183, For example, a pulse detection circuit that turns on is provided, and this circuit is set to simultaneously reset a counter provided at the horizontal pulse input terminal 184 (in normal mode). The connected pulse detection circuit is turned off, and the pulse detection circuit is connected so that it is turned on again at the output of the counter after a predetermined number of counts (during programming).

According to the synchronization circuit of the present invention described above, which includes various types of versatility, it is possible to program a receiver by providing an accessory device attached to a fixed station IC for storage.

For example, a clock circuit is installed inside or outside the display data generation circuit, the on/off of the receiver is set by a timer, and the clock circuit's time display data is read from a fixed station and the time is set for a certain period of time at the beginning of a program. It can also be displayed.

Further, a timer can be set so that time display data from the display data generation circuit is read out and displayed during the program.

In a receiver that operates in this manner, the present invention is designed to stabilize synchronization in vertical and horizontal screen scanning. Precisely determined by the synchronization pulse of the signal.

In other words, the vertical pulse from the synchronous separation circuit is applied to the vertical pulse output terminal of the fixed station IC via the adjustable integration circuit and the NPN transistor with a sharp fall, so the phase relationship with the horizontal pulse can be optimized. This has the advantage that the data read timing in the display data generation circuit is determined accurately with respect to the video signal.

(2) Next, during programming, when data to be displayed in the display data generation circuit is read out, the horizontal and vertical synchronization divides the horizontal pulse and uses it as a vertical pulse, and the synchronization separation circuit is turned off.

Therefore, when the display data generation circuit is switched to read a plurality of types of data separately, the set display position on the screen does not shift and is stable.

Note that as a means for reading out multiple types of data (time and channels) separately, a switch linked to the channel switching device of the receiver, a switch linked to a manual push button, etc. can be used, and the readout circuit section of the fixed station IC can be used. The necessary data is generated manually.

As described above, the present invention provides a synchronization circuit that stabilizes the synchronization relationship between the display data generation circuit and external station signals, and also stabilizes the display position when switching display states by signals from a fixed station. can.

[Brief explanation of the drawing]

The figure is a circuit diagram showing an embodiment of the synchronous circuit of the present invention. 12...Video signal detection circuit, 13...
Video signal amplification circuit, 14...Cathode ray tube, 15.
...In-plane yoke, 16...Vertical synchronous end circuit, 17...Horizontal synchronous end circuit, 18...
...Display data generation circuit, Q1 to Qll...
transistor.

Claims (1)

[Claims] 1. Synchronization separation means for separating and extracting a vertical synchronization signal and a horizontal synchronization signal as an external synchronization signal according to a switching signal from a video signal; and the horizontal synchronization signal, which is an external synchronization signal from the synchronization separation means. A horizontal synchronization oscillation circuit that oscillates in synchronization with a synchronization signal when it is applied, and freely oscillates when there is no horizontal synchronization signal; an external synchronization state in which each of the oscillation circuits oscillates using the external synchronization signal, and an internal synchronization state in which the free oscillation output of the horizontal synchronization circuit is used without using the external synchronization signal. When the switching signal to be switched is generated and the display control operation is performed by the external synchronization signal, the vertical synchronization signal of the external synchronization signal is used as the operation reference signal, and when the display control operation is performed by internal synchronization, the display control operation is performed using the external synchronization signal. Synchronization control means uses the oscillation output of the horizontal synchronization oscillator in the free oscillation state as an operation reference signal and generates an internal synchronization signal for the vertical synchronization oscillation circuit; a transmission path for supplying the external vertical synchronization signal to the control means, and in the internal synchronization state, according to the switching signal, the horizontal synchronization oscillation output in the free oscillation state is used to obtain the horizontal synchronization signal within the synchronization control means. A synchronization circuit comprising: a synchronization signal selection circuit having a transmission path for supplying an internal synchronization signal to a synchronization signal input terminal of the vertical synchronization oscillation circuit.